KR0157151B1 - High speed trunk interface block in atm switch - Google Patents

Abstract

The present invention relates to a high speed trunk line matching device (HTIH) for matching a synchronous transport module-4 (STM-4) relay line in an asynchronous transfer mode (ATM) exchange, wherein the switch has a link speed of 155 Mb / s to In order to provide a high-speed trunk line matching device that implements the maintenance function, data transfer function, and overhead processing function necessary for matching the STM-4 relay line, the STM-4 processing unit 21 performs serial data and parallel data. Interconverting bit synchronization and PLL circuits 33; An STM-4 transceiver 32 which multiplexes / demultiplexes an STM-4 frame and an STM-1 frame with each other; And an overhead processor 34 for converting an analog signal and a digital signal. The STM-1 processor 22 terminates an STM-1 frame, receives and transmits an ATM cell, and transmits an ATM cell. 1 STM-1 transceiver 41 to be carried on the payload to transmit; A network parameter controller 42 for determining whether a promised traffic characteristic is satisfied; An ATM processor 43 for receiving and receiving a cell and determining and processing whether it is a cell to be transmitted or a cell to be processed by itself; An IMI matching unit 44 that matches the ATM processing unit 43 and an external link matching device 3; A clock generator 45 for generating a clock; And a processor 46 that performs initialization operations and maintenance functions, thereby achieving effects such as efficient function implementation, maintenance, reliable function separation, and miniaturization of a high-speed ATM trunk line matching device.

Description

High-speed trunk line matching device in asynchronous transfer mode (ATM) exchange

1 is a connection diagram of the present invention.

2 is a basic configuration of the present invention.

3 is a block diagram of an STM-4 processing unit according to the present invention.

4 is a block diagram of an STM-1 processing unit according to the present invention.

5 is a timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1: high speed relay line matching device 2: power station

3: link matching device 4: network synchronizer device

5: alarm collecting device 6: telephone

21: STM-4 processing unit 22: STM-1 processing unit

23: optical transceiver 31: STM-4 transceiver

32: optical transceiver 33: bit synchronization and PLL circuit

34: overhead processor 41: STM-1 transceiver

42: network parameter control unit 43: ATM processing unit

44: IMI matching unit 45: clock generator

46: processor

The present invention provides a high-speed trunk interface matching device (HTIH) for matching a synchronous transport module-4 (STM-4) relay line in an asynchronous transfer mode (ATM) exchange. It is about.

The trunk line for the STM-4 interfaces network-nodes at a transmission rate of 622 Mb / s over fiber. The 622 Mb / s STM-4 frame consists of four 155 Mb / s STM-1 frames.

Conventional relay line matching device transmits low speed data using metal wires in a similar synchronous manner, and transmission device using optical cable performs high speed data transmission but performs ATM layer processing for asynchronous transfer mode switching and ATM switching. I never do that.

Therefore, a function of matching an ATM cell of a received 622 Mb / s STM-4 frame to an ATM switch having a 155 Mb / s link speed, transmitting an ATM cell received from the exchange to a network, and a high-speed relay line There is a need for a relay line matching device that can perform functions such as management.

Accordingly, the present invention provides a high-speed trunk line matching device that implements the maintenance function, data transfer function, and overhead processing function necessary for matching a 622Mb / s STM-4 relay line to a switch having a link speed of 155Mb / s. Its purpose is to.

In order to achieve the above object, the present invention is a high-speed trunk line matching device comprising a plurality of STM-1 (Synchronous Transport Module-1) processing unit in conjunction with a STM-4 (Synchronous Transport Module-4) processing unit, the STM- 4 The processor extracts the clock from the serial data received from the external optical transceiver, converts the serial data into parallel data, synchronizes the reference clock input from the STM-1 processor, and transmits the received parallel data. A bit synchronous and phase locked loop (PLL) circuit for converting data into the optical transceiver; STM-1 frames are terminated from the data received from the bit synchronization and PLL circuits, demultiplexed into STM-1 frames, and transmitted to the STM-1 processor, and STM-1 received from the plurality of STM-1 processors. An STM-4 transceiver for multiplexing frames to generate an STM-4 frame and transmitting the STM-4 frame to the bit synchronization and PLL circuits; And an analog signal received from an external telephone, converted into a digital signal, transmitted to the STM-4 transceiver, and the digital signal received from the STM-4 transceiver is converted into an analog signal and transmitted to the telephone. The STM-1 processor receives a signal from the STM-4 transceiver, terminates an STM-1 frame, receives an ATM cell, finds a valid ATM cell from a cell header, and transmits the signal according to a reference clock. An STM-1 transceiver configured to receive an ATM cell and load the STM-1 payload into an STM-1 payload according to a reference clock to the STM-4 processor; It receives the ATM cell from the STM-1 transceiver and determines whether it satisfies the traffic characteristics promised when setting up the call, and transmits a tagging or cell discarding function to the violated cell and vice versa. A network parameter controller for receiving a signal and transmitting the received signal to the STM-1 transceiver; A routing tag is added and transmitted to switch to a designated switch path according to a virtual channel identifier (VCI) and a virtual path identifier (VPI) of an ATM cell received from the network parameter controller. Receives and determines whether it is a cell to be transmitted to the network-node interface or a cell to be processed by itself, and when it is a cell to be transmitted to the network-node interface, it is transmitted to the network parameter controller and a maintenance function to be processed by itself. The ATM processing unit to process itself; An IMI (Inter Module Interface) matching unit which transmits / receives a cell with the ATM processing unit and transmits an external link matching device and serial data at an emitter coupled logic (ECL) level; A clock generator which receives a clock from an external network device and supplies the clock to the IMI matching unit, and generates a reference clock and supplies the clock to the STM-1 transceiver; And perform an initialization operation and maintenance function, communicate with the STM-1 transceiver, a network parameter controller, and an ATM processor, control the STM-4 processor, provide overhead communication, and provide an external alert collection device. And a processor for transmitting an alarm signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a connection diagram with other blocks in accordance with the present invention, 1 is a high-speed relay line matching device, 2 is a power station, 3 is a link matching device, 4 is a network synchronizer device, 5 is an alarm collecting device, 6 is a telephone Indicates.

The high-speed trunk line matching device 1 communicates with the power station 2 via a network node interface (NNI) 7. When the high speed data relay apparatus 1 receives information from the power station 2, the high speed data relay apparatus 1 detects an error and, in the case of a valid ATM cell, determines whether it is a cell to be processed or a cell to be exchanged. In the case of a signal cell to be transmitted to a mobile station, necessary routing information is added and transmitted to the link matching device (ALIH: Access Link Interface Hardware Block) 3 through an inter module interface (IMI) 8.

When a switched ATM cell or a cell for communication between internal processors is received from the link matching device 3 through the intermodule interface 8, the high-speed trunk line matching device 1 transmits to the power station whether it is a cell to be processed. It is determined whether the cell should be transmitted, and if it is a cell to be transmitted, it is loaded on the STM-4 frame and transmitted to the power station 2 through the network-node interface 7.

The high-speed trunk line matching device 1 receives STM-4 overhead information from the power station 2, selects other line information for voice call between the operators, and converts the digital signal into an analog signal (D / A). (6), the voice signal is received from the telephone (6), and the analog signal is converted into a digital signal (A / D) and added to the overhead of the STM-4 frame and transmitted to the large station (2).

Network Synchronization Hardware Block (NSHH) 4 is a clock for 622Mb / s data transmission through network-node interface 7, a clock for 155Mb / s data transmission through inter-module interface 8 and A reference clock is provided for synchronizing this clock, and the high-speed trunk line matching device 1 generates a necessary clock from this reference clock to maintain synchronization of the entire network. Meanwhile, an alarm gathering interface hardware block (AGIH) 5 transmits a failure state of the high-speed relay line matching device 1 and a board disconnection state to the system operator to take necessary measures.

2 is a basic configuration diagram of the present invention, and a high-speed trunk line matching board (HTLA) performing optical / electric, all / optical conversion functions for matching the network-node interface 7 of 622Mb / s. Line Interface Board Assembly (23), High Speed Trunk Physical Layer Interface Board Assembly (HTPA) for accommodating one STM-4 processor 21 and one STM-1 processor 22 ( 24, and a high-speed trunk ATM layer interface board assembly (HTAA) 21, which accommodates one STM-1 processor 22 for matching switch links. The HTLA 23 and the HTPA 24 are composed of 622 Mb / s of serial data for transmission and reception, serial data for reception, and a loss of signal (LOS) indicating loss of a received signal.

Maintenance, data forwarding, and overhead processing are required to match the 622Mb / s STM-4 trunk with a switch with 155Mb / s link speed.

The maintenance function monitors the performance of the network-node interface 7 and is necessary for minimizing information loss and for rapid recovery in the event of a failure.

The data transfer function is divided into a receiver and a transmitter to transmit ATM cells. The receiver demultiplexes the STM-4 signals received from the network-node interface 7 into four STM-1 signals and then performs an STM-1 frame. The ATM cell is extracted, and routing information for switching inside the exchange is added to the switch for the ATM cell that complies with the promised traffic. Meanwhile, the transmitter classifies whether the cell received by the switch is a cell to be transmitted to the network-node interface 7 or a cell for communication between the internal processors of the exchange and is an ATM cell to be transmitted to the network-node interface 7. Is inserted into the payload of the STM-1 frame and then multiplexed into the STM-4 frame and transmitted to the network-node interface 7 through the optical path.

The overhead processing function transmits information such as link status for maintenance and includes voice communication function and data transmission function necessary for the operator.

3 is a configuration diagram of the STM-4 processing unit according to the present invention, wherein 31 is an STM-4 transceiver, 32 is an optical transceiver, 33 is a bit synchronization and PLL circuit, and 34 is an overhead processor.

The optical transceiver 32 converts an optical signal received from the network-node interface 7 into an electrical signal and transmits the optical signal to the bit-synchronous and phase-locked loop (PLL) circuit 33 and the bit-sync and PLL. It consists of an optical transmitter for converting the electrical signal received by the circuit 33 into an optical signal and transmitting it to the network interface 7.

The bit synchronization and PLL circuit 33 extracts a clock from the serial data received from the optical transceiver 32, converts the 622Mb / s serial data into 77.76 Mb / s 8-bit parallel data, and converts the STM-1 processor 22 In synchronization with the reference clock input from)) and transmits to the STM-4 transceiver 31 with a 77.76Mhz clock. In addition, the parallel data received from the STM-4 transceiver 31 performs the function of converting the serial data to the optical transceiver 32.

The STM-4 transceiver 32 terminates the STM-4 frame from the data received from the bit synchronization and PLL circuit 33, demultiplexes into four STM-1 frames, and transmits the same to the STM-1 processor 22. . In addition, the STM-1 frames received from the four STM-1 processing units 22 are multiplexed to generate one STM-4 frame, which is transmitted to the bit synchronization and PLL circuit 33.

The overhead processing unit 34 is for processing the overhead function of the STM-4 frame, and provides functions such as providing a data channel for the operator and a pruning line for the operator voice communication in order to provide a service necessary for the operator.

The batting line is connected to the general telephone 6 to provide a voice call function between the network-node interface 7 and the operator, if necessary, and converts the analog signal into a digital signal to the STM-4 transceiver 34. The digital signal received from the STM-4 transceiver 34 is converted into an analog signal and transmitted to the telephone 6. It also supplies the telephone 6 with the necessary call current and interprets the complex frequency code (DTMF: Dual Tone Multi Frequency) received from the power station 2 so that the operator can receive the call if it corresponds to his / her number. do.

The data channel is serially communicated as a High Level Data Link Control (HDLC) signal, and is seldomized by the processor 46 to be transmitted and received upward through the first STM-1 processor 22. The STM-4 processor 21 performs necessary control of the STM-4 processor 21 in the first STM-1 processor 22 without mounting a processor.

4 is a block diagram of an STM-1 processing unit according to the present invention, 41 is an STM-1 transceiver, 42 is a network parameter controller, 43 is an ATM processor, 44 is an IMI matching unit, 45 is a clock generator, and 46 is a processor. Respectively.

The STM-1 transceiver 41 receives a signal from the STM-4 transceiver 31, terminates the STM-1 frame, receives 53 ATM ATM cells, finds a valid ATM cell from the cell header, and retrieves a network parameter. It transmits to a control unit (NPC: Network Parameter Control) 42. In addition, the ATM cell received from the network parameter controller 42 is loaded on the STM-1 payload to transmit the STM-1 signal to the STM-4 processor 21. At this time, the reference clock is input from the clock generator 45 to operate.

The network parameter controller 42 receives an ATM cell from the STM-1 transceiver 41 to determine whether a traffic characteristic promised when setting up a call is tagged, tagging or cell carding for the violated cell. After performing the function), it transmits the data to the ATM processor 43. On the contrary, the cell is received from the ATM processor 43 and transmitted to the STM-1 transceiver 41.

The ATM processor 43 routes the switch to switch to a designated switch path according to the virtual channel identifier (VCI) and the virtual path identifier (VPI) of the ATM cell received from the network parameter controller 42. Adds a tag and transmits the signal to the IMI matching unit 44, and receives a signal from the IMI matching unit 44 to determine whether it is a cell to be transmitted to the network-node interface 7 or a cell to be processed by itself. In the case of a cell to be transmitted to the node interface 7, the maintenance function to be transmitted to the STM-1 transceiver 41 through the network parameter controller 42 and to be processed by itself is processed by the ATM processor 42 itself or by a processor. Transmit at 45. For the maintenance of the system, each circuit is provided with a physical loopback and can loop back to a specific virtual channel or virtual box.

The IMI matching unit 44 transmits and receives the switch link and the 155 Mb / s serial data of the link matching device 3 at an emitter coupled logic (ECL) level.

The clock generator 45 receives a 20.53 MHz clock from the network synchronizer 4 and supplies it to the IMI matching unit 44, and generates a 19.44 MHz clock to supply the STM-1 transceiver 41. In addition, the first STM-1 processor 22 of the four STM-1 processors 22 generates a 19.44 MHz clock and supplies it to the bit synchronization and PLL circuit 33 of the STM-4 processor 21.

The processor 46 performs initialization and maintenance functions of its own hardware, and communicates with the inside of the system such as the STM-1 transceiver 41, the network parameter controller 42, and the ATM processor 43. In addition, the processor 46 controls the STM-4 processor 21 to provide overhead HDLC communication, generates a signal for the alarm, and transmits an alarm signal to the alarm collection device 5 through the connector of the back board. do.

5 is a timing diagram according to the present invention, wherein a signal transmitted from the HTPA 24 to the HTAA 22 is composed of a transmission clock of 19.44 MHz, seven parallel transmission data, and a transmission frame pulse, and the HTPA from the HTAA 22. The signal received at (24) consists of a receive clock of 19.44Mhz, seven parallel receive data, and a transmit frame pulse. The C1 byte of the STM-1 frame is located at the clock fall time immediately before the transmit / receive frame.

As described above, the present invention can obtain the effects of efficient function implementation, maintenance, reliable function separation, and miniaturization of a high speed ATM trunk line matching device.

Claims (2)

In the high-speed trunk line matching device including a plurality of STM-1 (Synchronous Transport Module-1) processing units 22 that interoperate with an STM-4 (Synchronous Transport Module-4) processing unit 21, the STM-4 processing unit 21 ) Extracts the clock from the serial data received from the external optical transceiver 32, converts the serial data into parallel data, and transmits it in synchronization with the reference clock input from the STM-1 processor 22, A bit synchronization and phase locked loop (PLL) circuit 33 for receiving parallel data, converting the data into serial data, and transmitting the same to the optical transceiver 32; Terminate STM-4 frames from the data received from the bit synchronization and PLL circuit 33, demultiplex them into STM-1 frames, and transmit them to the STM-1 processing unit 22, and transmit the plurality of STM-1 processing units ( An STM-4 transceiver 32 which multiplexes the STM-1 frame received from the 22) to generate an STM-4 frame and transmits the STM-4 frame to the bit synchronization and PLL circuit 33; And receiving an analog signal from an external telephone 6, converting the analog signal into a digital signal, transmitting the analog signal to the STM-4 transceiver 34, and analyzing the digital signal received from the STM-4 transceiver 34. An overhead processor 34 for converting into a log signal and transmitting the log signal to the telephone 6, and the STM-1 processor 22 receives a signal from the STM-4 transceiver 31 to receive a STM- signal. STM-4 processing unit 21 terminates one frame, receives an ATM cell, finds a valid ATM cell from the cell header, transmits it according to a reference clock, receives an ATM cell, and loads the STM-1 payload into an STM-1 payload. STM-1 transmitting and receiving unit 41 for transmitting according to the reference clock; The ATM cell is received from the STM-1 transceiver 41 to determine whether the traffic characteristic promised when setting up a call is transmitted, and a tagging or cell discarding function is performed for the violated cell. On the contrary, a network parameter controller 42 for receiving a cell and transmitting it to the STM-1 transceiver 41; A routing tag is added and switched to switch to a designated switch path according to a virtual channel identifier (VCI) and a virtual path identifier (VPI) of an ATM cell received from the network parameter controller 42. In addition, the network parameter controller 42 determines whether the cell is to be transmitted to the network-node interface 7 or a cell to be processed by the network-node interface 7 by receiving a signal. The maintenance function to be transmitted to and processed by itself is an ATM processor 43 which processes itself; An IMI (Inter Module Interface) matching unit 44 which transmits and receives a cell with the ATM processor 43 and transmits an external link matching device 3 and serial data to an ECL (Emitter Coupled Logic) level; A clock generator 45 which receives a clock from an external network device 4 and supplies the clock to the IMI matching unit 44, generates a reference clock, and supplies the clock to the STM-1 transceiver 41; And perform an initialization operation and maintenance function, communicate with the STM-1 transceiver 41, the network parameter controller 42, and the ATM processor 43, and control the STM-4 processor 21 to over. And a processor (46) for providing head communication and transmitting an alarm signal to an external alarm collection device (5). The high speed relay line according to claim 1, wherein the first STM-1 processor 22 of the plurality of STM-1 processors 22 generates a reference clock and supplies the reference clock to the bit synchronization and PLL circuit 33. Matching device.