KR20040013189A - NAND type flash memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce the size by forming gate spacings below the photolithography resolution and make it unnecessary to form a high density source/drain region in the memory cell transistor. CONSTITUTION: A plurality of gates are formed at regular intervals on a semiconductor substrate(200). The first and the second spacers(260) are respectively formed at on side of each side gate among the plurality of gates. Low density impurity regions(241) are formed in the substrate at both sides of each gate, respectively. High density impurity regions(243) are formed in the substrate under the first and the second spacers.

Description

NAND type flash memory device and method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a NAND type flash memory device capable of reducing a gap between gates below a resolution limit and a method of manufacturing the same.

Among the nonvolatile memory devices, a flash memory device is a device for programming or erasing all memory cells connected to any one word line.

1 is a layout diagram of a conventional NAND flash memory device. 2A to 2F illustrate a process cross-sectional view for explaining a method of manufacturing a conventional NAND flash memory device, and illustrate a cross-sectional structure along the line 2A-2A 'of FIG. 1. 2A to 2F illustrate a cross-sectional structure of one cell string in the conventional NAND flash memory device.

Referring to FIG. 1, in the conventional NAND type flash memory device, a plurality of active regions 105 extending in one direction are arranged at regular intervals, and are formed to extend across the plurality of active regions 105. A string selection line (SSL) 120-1 and a ground selection line (GSL) 120-2, and the string selection line 120-1 and a ground selection line 120-2. And a plurality of word lines 120-3 arranged at regular intervals between the lines and across the active region 105.

Referring to FIG. 2F, in a conventional NAND type flash memory device, a cell string includes two selection transistors 120-1a and (a) connected to a string select line 120-1 and a ground select line 120-2. 120-2a and a plurality of memory cell transistors 120-connected to a corresponding word line of the plurality of word lines 120-3 and arranged between the selection transistors 120-1a and 120-2a. 3a).

Each of the transistors 120-1a, 120-2a, and 120-3a includes a gate electrode 120, a spacer 150 formed on both substrates of the gate electrode 120, and the gate electrode 120. The impurity region 140 includes LDD structures 141 and 143 formed on both substrates.

The operation of the conventional NAND flash memory device having the structure as described above is as follows.

When the erase voltage is applied to the semiconductor substrate 100 during the erase operation and the reference voltage (ground voltage) of OV is applied to the plurality of word lines 120-3, all data stored in the gate of the cell transistor are erased. .

When data is programmed, data is programmed in one memory cell transistor among the plurality of memory cell transistors, and a power supply voltage Vcc and a ground voltage Vss correspond to the string selection line 120-1 and the ground selection line. The program voltage is applied to a word line 120-2, and a program voltage is applied to a word line to which the selected memory cell transistor is connected among a plurality of word lines.

Next, a method of manufacturing a conventional NAND flash memory device will be described with reference to FIGS. 2A to 2F.

Referring to FIG. 2A, a gate oxide film 110, a first polysilicon film 121 for floating gate 121, a dielectric film 123 including an ONO film, and a second polysilicon film 125 for a control gate are formed on a semiconductor substrate 100. ) And the silicide film 127 are sequentially deposited. A photosensitive film 130, for example, a positive photoresist film is coated on the silicide film 127.

Referring to FIG. 2B, the positive photoresist layer 130 is exposed using a gate forming mask (not illustrated). The positive photoresist layer 130 is divided into an exposed portion 133 and a non-exposed portion 131. It is done.

Referring to FIG. 2C, when the positive photoresist layer 130 is developed, the exposed portion 133 is removed by a developer to obtain a photoresist pattern 135 formed of the non-exposed portion 131.

Referring to FIG. 2D, the silicide layer 127, the first and second polysilicon layers 121, 125, and the dielectric layer 123 under the photoresist layer pattern 135 are etched. As a result, a gate 120 including the first polysilicon film 121, the dielectric film 123, the second polysilicon film 125, and the silicide film 127 is obtained on the gate oxide film 110.

Referring to FIG. 2E, after removing the photoresist pattern 135, a low concentration impurity region 141 is formed on both sides of the gate 120 by ion implantation of a predetermined conductivity type, for example, an n-type impurity, into the substrate 100. ).

Referring to FIG. 2F, a spacer 150 is formed on a sidewall of the gate 120 by a conventional spacer forming method, and then impurities having the same conductivity type as the low concentration impurity region 141 are formed as a substrate, for example, n +. A high concentration impurity region 143 is formed by ion implantation of a type impurity. Thus, a source / drain region 140 including a low concentration impurity region 141 and a high concentration impurity region 143 is formed. As a result, a cell string including the selection transistors 120-1a and 120-2a and the plurality of memory cell transistors 120-3a is formed.

In the conventional NAND type flash memory device as described above, as the size of the device is reduced, the gap between gates becomes finer, and the limitation of minimizing the gap between gates due to the resolution limitation in the photolithography process is problematic. there was. In addition, when the gap between the gates is narrowed according to the size reduction of the device, there is a problem that it is difficult to form the impurity region of the LDD structure for the subsequent source / drain.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and the gate interval can be narrowed below the resolution limit in the photo process, thereby eliminating the need for a high concentration source / drain region in the memory cell transistor. SUMMARY OF THE INVENTION An object of the present invention is to provide a NAND type flash memory device capable of further reducing the size of and a method of manufacturing the same.

1 is a layout diagram of a conventional NAND flash memory device;

2A through 2F are cross-sectional views illustrating a method of manufacturing a conventional NAND flash memory device.

3 is a layout diagram of a NAND type flash memory device according to an embodiment of the present invention.

4A to 4G are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

200 semiconductor substrate 205 active region

210: gate oxide film 221, 225: polysilicon film

223 dielectric film (ONO film) 227 silicide

230: photosensitive film 241: low concentration impurity region

243: high concentration impurity region 250: mask

260 spacer

The present invention for achieving the above object is a plurality of gates formed at regular intervals from each other on the semiconductor substrate; First and second spacers formed on one side of gates at both ends of the plurality of gates; A low concentration impurity region formed on both substrates of each of the gates; A semiconductor memory device including a high concentration impurity region formed on a substrate under the first and second spacers is provided.

In addition, the present invention includes a first transistor and a second gate formed on the semiconductor substrate; A plurality of gates for a memory cell transistor arranged between the first and second gates; First and second spacers formed on one side of the first and second gates; A low concentration impurity region formed on both substrates of each of the gates; A NAND type flash memory device including a high concentration impurity region formed in a substrate under the first and second spacers formed at one side of the first and second gates may be provided.

In addition, the present invention includes a plurality of active regions elongated in one direction on the semiconductor substrate; A string selection line and a ground selection line formed to intersect the plurality of active regions; A plurality of word lines arranged between the string selection line and a ground selection line to intersect the plurality of active regions; Low concentration impurity regions respectively formed on the active regions on both sides of the selection line and the word line; A NAND type flash memory device including first and second spacers formed on one side of each selection line, and high concentration impurity regions formed in an active region under the first and second spacers formed on one side of the first light second gate; It characterized in that to provide.

In addition, the present invention comprises the steps of forming a gate electrode material on a semiconductor substrate; Forming a photoresist film on the gate electrode material; Firstly exposing the photosensitive film using a gate forming mask; Second exposure of the photoresist film using the gate forming mask; Developing the photoresist to form a photoresist pattern; Patterning a gate electrode material using the photoresist pattern as a mask to form a gate electrode; Forming a low concentration impurity region using the gate electrode as a mask; Forming a mask to expose one side of the gate electrode at both ends; Forming a spacer on one side of the exposed gate electrode; And forming a high concentration impurity region only on one side of the gate by using the mask and the spacer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.

3 shows a layout diagram of the NAND type flash memory device of the present invention. 4A to 4G are cross-sectional views illustrating a process cross-sectional view for explaining a method of manufacturing a NAND type flash memory device according to the present invention. 4A to 4G show a cross-sectional structure of one cell string in the NAND type flash memory device of the present invention.

Referring to FIG. 3, in the NAND type flash memory device of the present invention, a plurality of active regions 205 extending in length in one direction are arranged at regular intervals, and extend across the plurality of active regions 205. The formed string select line 220-1 and the ground select line 220-2 and the string select line 220-1 and the ground select line 220-2 are arranged at a predetermined interval, and the active region ( And a plurality of word lines 220-3 formed across 205.

Referring to FIG. 4G, in the NAND type flash memory device of the present invention, the cell string includes two select transistors 220-1a connected to the string select line 220-1 and the ground select line 220-2. And a plurality of memory cell transistors 220 connected to a corresponding word line of the plurality of word lines 220-3 and arranged between the selection transistors 220-1a and 220-2a. -3a).

Each of the memory cell transistors 220-3a includes a gate electrode 220 and a low-performance impurity region 241 formed on both substrates of the gate electrode 220. On the other hand, each of the selection transistors 220-1a and 220-2a is disposed on the gate electrode 220, the spacer 250 formed on one side of the gate electrode 220, and the one side of the gate electrode 220. The low concentration impurity region 241 is formed and the impurity region 240 of the LDS structures 241 and 243 formed on the other substrate of the gate electrode 220.

Next, a method of manufacturing the NAND type flash memory device of the present invention will be described with reference to FIGS. 4A to 4G.

Referring to FIG. 4A, a gate oxide film 210, a first polysilicon film 221 for a floating gate, a dielectric film 223 formed of an ONO film, and a second polysilicon film 225 for a control gate are formed on a semiconductor substrate 200. ) And the silicide film 227 are sequentially deposited. A photosensitive film 230, for example, a negative photoresist film 230, is coated on the silicide film 227. In this case, an insulating film such as an oxide film or a nitride film may be formed on the silicide film 227.

Referring to FIG. 4B, the negative photosensitive film 230 is first exposed using a gate forming mask (not shown). The negative photoresist film 230 is divided into an exposed portion 233 and a non-exposed portion 231.

Referring to FIG. 4C, the gate forming mask is aligned to expose a portion of the non-exposed area 231 between the exposure area 233 to expose the photosensitive film 230 to the second exposure. Accordingly, in the second exposed photoresist film 230, the non-exposed portions 231 and the exposed portions are alternately repeated, and the portion of the exposed portion where the gate of the cell transistor is to be formed is first exposed (233), and the memory cell. In the portion where the gate of the transistor is to be formed, the first exposed portion 233 and the second exposed portion 235 are alternately repeated.

Referring to FIG. 4D, when the photoresist film 230 is developed, since the photoresist film 230 is negative, the exposed portions 233 and 235 remain as they are, and the non-exposed portions 231 are removed by the developer to expose the exposed portion 233. 235 is obtained.

In the embodiment of the present invention, by using the same gate forming mask, a portion of the non-exposed portions between the first exposed portions of the negative photoresist film is subjected to secondary exposure and then developed to form a photoresist pattern, thereby lowering the resolution limit compared to the prior art. It is possible to form a photosensitive film pattern of a fine interval.

Referring to FIG. 4E, the silicide layer 227, the first and second polysilicon layers 221, 225, and the dielectric layer 223 under the photoresist layer pattern 237 are etched. As a result, a gate 220 including the first polysilicon film 221, the dielectric film 223, the second polysilicon film 225, and the silicide film 227 is obtained on the gate oxide film 110.

Referring to FIG. 4F, the photoresist layer pattern 237 is removed, and then a low concentration impurity region 241 is formed on both sides of the gate 120 by ion implantation of a predetermined conductivity type, for example, an n-type impurity, into the substrate 200. ).

Referring to FIG. 4G, a mask 250 is formed to cover the gate electrode 220 of the memory cell transistor 220-3a and the gates of the selection transistors 220-1a and 220-2a. The spacer 260 is formed only on one side of the exposed gates of the selection transistors 220-1a and 220-2a by a spacer forming method, and formed on one side of the selection transistors 220-1a and 220-2a. A high concentration impurity region 243 is formed by ion implanting a high concentration impurity, for example, an n + type impurity, only into the low concentration impurity region 241.

As a result, one cell string including two select transistors 220-1a and 220-2a and a plurality of memory cell transistors 220-3a formed therebetween is formed.

As another example of forming a high concentration impurity region of the present invention, as shown in FIG. 4F, a low concentration impurity region 241 is formed, and in FIG. 4G, spacers 260 are formed on both sides of the gate 220, and the gate is covered. After the mask 250 is formed, a high concentration impurity region 243 is formed by ion implantation of a high concentration impurity.

The NAND type flash memory device of the present invention having the configuration as described above forms a gap between gates to be narrower than the resolution, thereby enabling the transistor to operate even when a high concentration impurity region does not exist. Program, read, and erase operations can be performed like devices.

In the embodiment of the present invention, the gate electrode 120 has a stacked structure of the first polysilicon film, the dielectric film, and the control gate for the second polysilicon film and the silicide film, but the present invention is not limited thereto. . For example, it is not only applicable to semiconductor devices having structures such as metal-nitride-oxide-silicon (MNOS) and metal-oxide-nitride-oxide-silicon (MONOS), but also uses various types of dielectric films instead of ONO films. It is possible.

Therefore, according to the present invention as described above, a gate electrode having a space below the resolution limit is formed by performing two exposure steps and one development step by using a negative photoresist film, so that high concentration source / drain regions are unnecessary. As a result, the size of the device can be reduced and the difficulty of the LDD forming process according to the size reduction of the device can be solved.

In addition, there is an advantage that the process can be simplified by performing two exposure processes using the same mask.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (17)

A plurality of gates formed at regular intervals from each other on the semiconductor substrate; First and second spacers formed on one side of gates at both ends of the plurality of gates; A low concentration impurity region formed on both substrates of each of the gates; And a high concentration impurity region formed in the substrate under the first and second spacers. The semiconductor device according to claim 1, wherein the gate has a stacked structure of a floating gate, a dielectric film, and a control gate. 2. The semiconductor device according to claim 1, wherein the gate has a stacked structure of a first polysilicon film for a floating gate, a dielectric film, a second polysilicon film for a control gate, and a silicide film formed on a gate oxide film. The semiconductor device according to claim 1, wherein the gate is made of an oxide film, a nitride film and a metal material. The semiconductor memory device according to claim 1, wherein the gate has a stacked structure of an oxide film, a nitride film, an oxide film, and a metal material. 2. The semiconductor memory device according to claim 1, wherein gates at both ends of the gates are gates of a selection transistor, and a plurality of gates arranged between the gates of the selection transistors are gates of memory cell transistors. First and second gates for a selection transistor formed on the semiconductor substrate; A plurality of gates for a memory cell transistor arranged between the first and second gates; First and second spacers formed on one side of the first and second gates; A low concentration impurity region formed on both substrates of each of the gates; And a high concentration impurity region formed in the substrate under the first and second spacers formed at one side of the first and second gates. A plurality of active regions extending in one direction on the semiconductor substrate; A string selection line and a ground selection line formed to intersect the plurality of active regions; A plurality of word lines arranged between the string selection line and a ground selection line to intersect the plurality of active regions; Low concentration impurity regions respectively formed on the active regions on both sides of the selection line and the word line; First and second spacers formed on one side of each selection line; And a high concentration impurity region formed in active regions under the first and second spacers formed at one side of the first light second gate. Forming a gate electrode material on the semiconductor substrate; Forming a photoresist film on the gate electrode material; Firstly exposing the photosensitive film using a gate forming mask; Second exposure of the photoresist film using the gate forming mask; Developing the photoresist to form a photoresist pattern; Patterning a gate electrode material using the photoresist pattern as a mask to form a gate electrode; Forming a low concentration impurity region using the gate electrode as a mask; Forming a mask to expose one side of the gate electrode at both ends; Forming a spacer on one side of the exposed gate electrode; And forming a high concentration impurity region only on one side of the gate by using the mask and the spacer. 10. The method of claim 9, wherein the gate has a stacked structure of a floating gate, a dielectric film, and a control gate. 10. The semiconductor memory device of claim 9, wherein the gate comprises a stacked structure of a first polysilicon film for a floating gate, a dielectric film, and a control layer formed on a gate oxide film, and a second polysilicon film for a gate and a silicide film. Way. 10. The method of claim 9, wherein the gate is formed of an oxide film, a nitride film, and a metal material. 10. The method of claim 9, wherein the gate has a stacked structure of an oxide film, a nitride film, an oxide film, and a metal material. 10. The method of claim 9, wherein the mask is formed of an oxide film or a nitride film. The method of manufacturing a semiconductor memory device according to claim 9, wherein said photosensitive film is negative. 16. The semiconductor memory device according to claim 15, wherein a non-exposed portion between the first and second exposed portions is exposed during the second exposure of the photosensitive film to form a photosensitive film pattern composed of the first and second exposed portions. Manufacturing method. 10. The method of claim 9, wherein gates at both ends of the gates are gates of a selection transistor, and a plurality of gates arranged between the gates of the selection transistors are gates of memory cell transistors.