KR20040010445A - Structure and fabricating method of high-voltage MOS transistor - Google Patents

Abstract

PURPOSE: A structure of a high-voltage MOS transistor and a fabricating method thereof are provided to obtain a gate induced breakdown voltage of a high level by forming a field buffer layer on both sides of a bottom side of a gate electrode. CONSTITUTION: A structure of a high-voltage MOS transistor includes the first conductive type semiconductor substrate, an isolation layer, a gate electrode, a field buffer layer, the second conductive type low-density source/drain region(210), and the second conductive type high-density source/drain region(220). The isolation layer is formed on the first conductive type semiconductor substrate. The gate electrode is formed by inserting a gate insulating layer between the isolation layers. The field buffer layer is formed on both sides of a bottom side of the gate electrode. The second conductive type low-density source/drain region(210) is formed around the field buffer layer. The second conductive type high-density source/drain region(220) is formed by using the gate electrode and the field buffer layer as masks.

Description

Structure of high voltage MOS transistor and manufacturing method thereof {Structure and fabricating method of high-voltage MOS transistor}

The present invention relates to a structure of a high voltage metal oxide semiconductor (MOS) transistor and a method of manufacturing the same. A method of manufacturing a transistor having a gate induced breakdown voltage (hereinafter referred to as 'GIBV').

A non-volatile memory device is a product that can maintain its state with or without power once it is inputted and can also program, erase, and read data. The nonvolatile memory device may be classified into a programmable ROM (PROM), an erasable PROM (EPROM), and an electrically EPROM (EEPROM). Among them, the demand for flash EEPROM that can program and erase data by electric method is increasing. Flash EEPROM memory devices are an advanced form of EEPROM that can be electrically erased at high speed without removing them from the circuit board.The memory cell structure is simple, so the manufacturing cost per unit memory is low and the data is refreshed to preserve data. The advantage is that no function is required.

In a flash EEPROM device, a memory cell operated by an external peripheral circuit has a gate structure in which a floating gate and a control gate are stacked. The program operation of the memory cell is performed by injecting a part of hot electrons in a channel into a floating gate through a tunnel oxide film (or a gate oxide film) by F-N tunneling or hot electron injection. In order to perform such a program operation, 0V is generally applied to a bulk substrate and a high voltage of 20V or more is applied to a control gate provided as a word line of a cell array. At this time, a voltage of 10 MV / cm or more is induced at both ends of the tunnel oxide film, and electrons are injected from the substrate to the floating gate. Meanwhile, the erase operation of the memory cell is performed by applying 0V to the control gate and -20V to the bulk substrate to release electrons injected into the floating gate to the substrate by the voltage difference between the control gate and the substrate.

Therefore, in the flash EEPROM device, an external circuit for driving a memory cell must exist, and the circuit is mainly composed of a MOS transistor having a high voltage junction breakdown voltage of 20V or more. The high voltage formed by the MOS transistor is transferred to a word line of a cell array used as a control gate along a lead made of a conductor such as a metal to program the cell. Therefore, as described above, a process of manufacturing a MOS transistor that forms a high voltage junction breakdown voltage and transfers it to a word line is very important. Such MOS transistors are commonly referred to as high voltage transistors and are formed in different regions from low voltage transistors.

In addition, power device products, such as LCD Driver IC (LDI) products, have a low voltage operation for driving logic circuits and high voltages for driving LCD panels. It requires both high voltage operation. Therefore, LCD driving devices must also be composed of MOS transistors having high voltage junction breakdown voltages of 20V or more like flash EEPROM devices.

1 is a cross-sectional view of a high voltage MOS transistor having a conventional double diffused drain (hereinafter referred to as 'DDD') junction structure.

Referring to FIG. 1, a conventional high-voltage MOS transistor having a DDD structure includes a polysilicon layer 12 and a tungsten silicide layer 13 doped with impurities through a gate oxide film 11 on the p-type semiconductor substrate 10. ) Has a gate electrode formed of a stacked polycide structure. Sandwiching the gate electrode (12, 13) ^_ the n source / drain region 14 and the n ⁺ source / drain region 16 to the surface of the substrate 10 is formed. The ^n_ source / drain region overlaps the gate electrode while completely encapsulating the n ⁺ source / drain region. Here, reference numeral 15 denotes a sidewall spacer oxide film provided to form the n ⁺ source / drain region.

A high voltage having the aforementioned DDD transistor Mohs junction structure serves to relieve the electric field (electric field) be applied between the, ^_ n source / drain regions are n ⁺ source / drain region and the gate electrode. Thus, a high level of gate induced breakdown voltage and punch-through characteristics can be obtained. However, in order to form the DDD junction structure n ^_ wherein the ion implantation step of an impurity n ^_ high temperature for a deep diffusion of impurities, as well as require a heat treatment for a long time, to increase the thickness of the gate oxide film in order to obtain high GIBV value do. Such high temperature, long heat treatment and thick gate oxide film degrade the performance of the MOS transistor.

2 is a cross-sectional view of a high voltage MOS transistor having a conventional mask lightly doped drain (hereinafter referred to as MLDD) junction structure.

Referring to FIG. 2, a conventional high voltage MOS transistor having an MLDD structure includes a polysilicon layer 22 and a tungsten silicide layer 23 doped with impurities through a gate oxide film 21 on the p-type semiconductor substrate 20. ) And a gate electrode formed of a stacked polyside structure. More specifically, the gate electrodes 22 and 23 across the surface of said substrate n ^_ source / drain region 24 and n ⁺ source / drain region 26 to be formed. ^_ The n source / drain regions is fully formed long toward the channel than the n ⁺ source / drain regions serves to reduce the electric field to be applied between the n ⁺ source / drain region and the gate electrode. Here, n ⁺ source / drain regions are formed using photoresist as a mask. Here, reference numeral 25 denotes sidewall spacers provided to form n ⁺ source / drain regions for logic.

However, to be formed according to the high-voltage transistor having a Mohs MLDD junction structure described above, a sufficiently long length of the n ^_ source / drain regions in order to obtain high GIBV value, and to increase the thickness of the gate oxide film. This has a problem of increasing the area of the MOS transistor and decreasing the current driving capability. In addition, in the photoresist process to provide a sufficient separation distance between the channel and the n ⁺ source / drain region, an error due to an error in mask alignment may occur.

Accordingly, the present invention is to solve the above problems of the prior art, to provide a structure and a method of manufacturing a transistor having a high level of gate induced breakdown voltage by forming an electric field relaxation separator on the lower side of the gate electrode. There is an object of the present invention.

1 and 2 are cross-sectional views of a high voltage MOS transistor according to the prior art.

3A to 3E are cross-sectional views of a method of manufacturing a high voltage MOS transistor according to the present invention.

The object of the present invention is a semiconductor substrate of the first conductivity type; An isolation layer formed over the semiconductor substrate by a predetermined distance: a gate electrode formed by disposing a gate insulation layer between the isolation layers; Field relaxed separators formed on both sides of the lower portion of the gate electrode; A low concentration source / drain region of a second conductivity type formed around the field relaxation separator with the gate electrode as a mask; And a high concentration source / drain region of a second conductivity type formed using the gate electrode and the field relaxation separator as a mask.

In addition, the object of the present invention comprises the steps of stacking and patterning the first insulating film and the second insulating film on a semiconductor substrate of the first conductivity type; Forming a device isolation trench and a field relaxation trench using the patterned first insulating film and the second insulating film as an etch mask; Gap-filling and planarizing an insulating film in each of the trenches to form a device isolation layer and an electric field relaxation separator; Removing the second insulating film and the first insulating film; Stacking a gate insulating film and a first conductor on the substrate, and patterning the first conductor to form a gate electrode; Implanting impurities of a second conductivity type using the gate electrode as a mask to form a low concentration source / drain region; And implanting impurities of a second conductivity type using the gate electrode and the field relaxation separator as a mask to form a high concentration source / drain region.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, FIG. 3A is a cross-sectional view illustrating a process of stacking and patterning first and second insulating films on a first conductive semiconductor substrate. In more detail, the first insulating film 110 for the buffer and the second insulating film 120 for the etch stop film are sequentially stacked on the entire upper surface of the first conductive semiconductor substrate 100. Preferably, a silicon oxide film is used as the buffer first insulating film and a nitride film is used as the second insulating film for the etch stop film. Thereafter, a photolithography (130) process is performed to form the device isolation region and the field relaxation region.

Next, FIG. 3B is a cross-sectional view illustrating the steps of forming the device isolation trench 150 and the field relaxation trench 160. A photoresist process is performed on the semiconductor substrate on which the device isolation region and the field relaxation region are patterned to expose only the device isolation region. The exposed device isolation regions are then etched to form device isolation trenches of a first thickness. Thereafter, the photoresist is removed and the device isolation trench of the first thickness is further etched by the second thickness using the patterned first and second insulating layers as an etching mask. At the same time, using the patterned first and second insulating layers as an etch mask, a field relaxation trench having a second thickness is formed. That is, the device isolation trench has a depth equal to the first thickness plus the second thickness, and the field relaxation trench has a depth of the second thickness. Preferably, the device isolation trench has a depth of 1000 to 5000 microns and is formed of a conventional trench (STI) or a self-aligned trench (SA-STI). In addition, the field relaxation trench is characterized in that it is formed having a depth of 50 to 5000Å and a width of 100 to 50000Å.

Next, FIG. 3C is a cross-sectional view illustrating a step of gap-filling and planarizing the device isolation trench and the field relaxation trench. First, a liner oxide layer 170 is formed on an inner wall of the device isolation trench and the field relaxation trench formed to have the predetermined depth. The liner oxide film is formed by a thermal oxidation process. Thereafter, each trench in which the liner oxide layer is formed is filled with a predetermined insulating material to form the device isolation layer 180 and the field relaxation separator. Preferably, a material such as TEOS (tetraethylorthosilicate) having flowability as the insulating material and having excellent step coverage is used. Thereafter, the semiconductor substrate is planarized by performing a chemical mechanical polish (CMP) process until the second insulating layer for the etch stop layer appears.

Thereafter, the second insulating film and the first insulating film remaining on the semiconductor substrate on which the planarization is completed are removed. The first and second insulating layers are removed by wet etching, and the upper portion of the semiconductor substrate on which the etching is completed has a convex shape between the device isolation insulating film and the field relaxation insulating film.

3D is a cross-sectional view showing a step of forming a gate electrode. First, an insulating film 190 for a gate electrode and a predetermined conductor 200 are sequentially stacked on the entire upper surface of the semiconductor substrate from which the first and second insulating films are removed. Subsequently, a region in which the gate electrode is to be formed is patterned through a photolithography process and etching is performed to form a gate electrode. Preferably, the gate electrode is formed of a polyside structure in which a polysilicon layer doped with impurities and a metal silicide layer are stacked. The field relaxation separator is positioned on both sides of the lower surface of the gate electrode.

An oxide spacer may be further formed on the sidewall of the gate electrode, and the gate electrode may be formed in a salicide structure due to the addition of the spacer. The oxide spacer serves as an insulating layer for preventing current leakage between a conductor of the gate electrode and a source / drain region to be formed in the future.

3E is a cross sectional view showing a step of forming a source / drain region. A second conductivity type impurity opposite to the semiconductor substrate is implanted at a low concentration 210 using the gate electrode and the device isolation layer provided with the field relaxation separator as a mask. The implanted low-concentration second conductivity type impurities are formed on both side surfaces of the lower portion of the gate electrode while surrounding the field relaxation separator. Thereafter, a second conductivity type impurity is implanted at a high concentration 220 using the gate electrode, the field relaxation separator, and the device isolation layer as a mask. The implanted high concentration second conductivity type impurity region and low concentration second conductivity type impurity region become source / drain regions.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the structure of the high voltage MOS transistor of the present invention and the method of manufacturing the same have an effect of manufacturing a transistor having a high level of gate induced breakdown voltage by forming an electric field relaxation separator on both lower sides of the gate electrode.

That is, a high gate induced breakdown voltage can be obtained without increasing the thickness of the gate insulating film because a high concentration source / drain region and a high voltage applied to the gate electrode are caught by a sufficiently thick field relaxation separator.

Claims (9)

In the structure of the high voltage MOS transistor, A semiconductor substrate of a first conductivity type; An isolation layer formed on the semiconductor substrate at a predetermined distance from the semiconductor substrate; A gate electrode formed by interposing a gate insulating film between the device isolation layers; Field relaxed separators formed on both sides of the lower portion of the gate electrode; A low concentration source / drain region of a second conductivity type formed around the field relaxation separator with the gate electrode as a mask; And High concentration source / drain regions of a second conductivity type formed using the gate electrode and the field relaxation separator as a mask The structure of the high voltage MOS transistor comprising a. The method of claim 1, The structure of the high voltage MOS transistor, characterized in that the thickness of the field relaxation separator is thinner than the thickness of the device separator. The method of claim 1, The field relaxation separator has a width of 100 to 50000 kW and a thickness of 50 to 5000 kW. The method of claim 1, The device isolation layer is formed of a conventional trench or a self-aligned trench structure of a high voltage MOS transistor. In the manufacturing method of a high voltage MOS transistor, Stacking and patterning a first insulating film and a second insulating film on a first conductive semiconductor substrate; Forming a device isolation trench and a field relaxation trench using the patterned first insulating film and the second insulating film as an etch mask; Gap-filling and planarizing an insulating film in each of the trenches to form a device isolation layer and an electric field relaxation separator; Removing the second insulating film and the first insulating film; Stacking a gate insulating film and a first conductor on the substrate, and patterning the first conductor to form a gate electrode; Implanting impurities of a second conductivity type using the gate electrode as a mask to form a low concentration source / drain region; And Implanting impurities of a second conductivity type using the gate electrode and the field relaxation separator as a mask to form a high concentration source / drain region Method of manufacturing a high voltage MOS transistor, characterized in that comprises a. The method of claim 5, And forming an oxide spacer on sidewalls of the gate electrode when the gate electrode is formed. The method of claim 5, And the first insulating film and the second insulating film serve as buffer films and etch stop films, respectively. The method of claim 5, Forming the device isolation trench and the field relaxation trench Forming a photoresist pattern that only opens the device isolation region; Etching only the open device isolation region to form a device isolation trench of a first depth; Removing the photoresist pattern and forming a field relaxed trench of a second depth; And Further etching the device isolation trench of the first depth by a second depth Method of manufacturing a high voltage MOS transistor, characterized in that comprises a. The method of claim 5, And planarizing the insulating film formed in the trench is performed until the second insulating film is formed by using a CMP process.