KR20040009425A - High speed encoder - Google Patents

Abstract

PURPOSE: A high-speed encoder is provided to reduce the critical path, the delay time, and the power consumption by using a folding interpolation method and an encoding method. CONSTITUTION: A high-speed encoder includes a switch(120), an encoder(130), a selection controller(140), a selector(150), the first high-order bit generator(160), and the second high-order bit generator(170). The switch(120) selects high-order data codes or low-order data codes according to high-order/low-order selection signals of a code generator(110). The encoder(130) is used for encoding the selected data codes to generate low-order binary codes. The selection controller(140) is used for providing code selection signals according to the predetermined data codes of the selected data codes. The selector(150) is used for selecting one code from output codes of the encoder(130) according to the code selection signals. The first high-order bit generator(160) is used for providing the first high-order bits by using the predetermined data codes of the high-order data codes and the low-order data codes. The second high-order bit generator(170) is used for providing the second high-order bits by using the predetermined data codes of the high-order data codes.

Description

High Speed Encoder {HIGH SPEED ENCODER}

The present invention relates to a high-speed encoder applied to an A / D converter suitable for high-speed image processing, and more particularly, to implement an encoder used inside the A / D converter for image signal processing. By using the encoding technique of generating BCD codes of upper bits and lower bits by using them and selecting the remaining bits using upper bits, the critical path for high-speed processing of an input signal to a predetermined bit of BCD code can be reduced. The present invention relates to a high-speed encoder capable of high-speed processing by reducing time and reducing power consumption by lowering current consumption.

In general, an encoder is applied to an A / D converter (ADC) for image and audio signal processing by a CMOS process using a silicon process, and in such an A / D converter (ADC), an analog signal is input. The encoder, which is a digital block that encodes the generated thermometer code to binary code, does not take up a large portion of the logic of the analog part in the entire circuit, but the A / D converter is faster. In addition, due to the development requirements to obtain high resolution, the encoder in the A / D converter requires a new high speed structure.

FIG. 1 is a block diagram of a general A / D converter. Referring to FIG. 1, a general A / D converter includes a code generator for converting an input analog signal into a thermometer code, and a thermometer code from the code generator. An encoder for encoding a binary code, and a latch for synchronizing an output of the encoder.

2A and 2B are conceptual diagrams of converting signals from 0V-3V to BCD codes in general, and FIGS. 3A and 3B are conceptual diagrams of general 8 to 3 encoders. Referring to FIGS. 2A and 2B, the decimal BCD encoder is an input signal. Are encoders that convert decimal sizes having different sizes to binary codes. Referring to FIGS. 3A and 3B, the 8 to 3 encoders are encoders that convert 8 inputs to 2-bit outputs.

In addition, low power, high speed operation at high clock frequency requires a new architecture, and the importance of circuit design technology for high speed operation continues to increase. On the other hand, the encoder is an essential element in the signal processing of the A / D converter and is also an important part affecting the processing speed and performance of the system.

4 is a block diagram of a conventional 64 to 6 encoder. Referring to FIG. 4, a conventional 64 to 6 encoder is configured to output 16 input bits into 4 bits to output 64 input signals as 6 bit BCD codes. 16 to 4 encoders 10, four 4 to 2 encoders 20 encoding four bits each of the outputs of the 16 to 4 encoders 10, and 4 to 2 encoders 20 outputs. It includes two 4 to 3 encoders 30 for encoding four bits of the three bits.

FIG. 5 is a configuration diagram of the 16 to 4 encoder of FIG. 4. Referring to FIG. 5, the 16 to 4 encoder 10 receives 4 of 16 inputs and encodes 3 bits to encode 3 bits. And 4 to 2 encoders 11b which receive 4 of the outputs of the 4 to 3 encoders 11a and encode the 2 bits.

Normally, the processing speed of the encoder is determined by the number of critical paths. Referring to FIGS. 4 and 5, in the conventional encoder, 16 to 4 encoders 10 are provided in two stages, and 4 to 2 encoders 20 and 4 to. Each of the three encoders 30 is composed of four stages.

However, in such a conventional encoder, a priority is determined based on an input value corresponding to a BCD value of an input bit, and is obtained by comparison with a priority encoder having a desired value and a logical element for each input signal. The Comparator Encoder did not produce satisfactory results in the computational current and delay time.

In addition, such a conventional 64 to 6 encoder has a hassle to pass a large number of buffers for the next signal to be used in the switching block selected as the first signal in the logic configuration, and the input signal to the desired output code. In order to convert, it has to go through four levels of critical paths, so that high-speed processing is difficult and power consumption increases accordingly.

The present invention has been made to solve the above problems, and an object of the present invention is to implement an encoder used in an A / D converter for image signal processing, and to use a higher weight value for each input signal. The present invention relates to a high-speed encoder capable of reducing a critical path for high-speed processing of an input signal into a BCD code of a predetermined bit by an encoding technique of generating a bit and a low bit BCD code and selecting the remaining bits using the high bit.

In addition, another object of the present invention is to reduce the critical path for the high-speed processing of the input signal to the BCD code of a predetermined bit, thereby reducing the delay time to enable high-speed processing, lower current consumption It is to provide a high speed encoder that can reduce power consumption.

1 is a block diagram of a general A / D converter.

2A and 2B are conceptual diagrams for converting a typical 0V-3V signal to a BCD code.

3A and 3B are conceptual diagrams of a general 8 to 3 encoder.

4 is a configuration diagram of a conventional 64 to 6 encoder.

FIG. 5 is a configuration diagram of the 16 to 4 encoder of FIG. 4.

6 is a block diagram of a 64 to 6 encoder according to the present invention.

FIG. 7 is an input / output code table for explaining the code generator of FIG. 6.

8 is a configuration diagram of the switching unit of FIG. 6.

9 is an operation explanatory diagram of the RF F / F of FIG. 8.

FIG. 10 is a diagram illustrating the multiplexer of FIG. 8.

FIG. 11 is a code table for describing an operation of the encoder of FIG. 6.

12 is a graph showing an output delay time.

Explanation of symbols on the main parts of the drawings

110: code generation unit 120: switching unit

121: RS F / F section 122: multiplexer section

130: encoder unit 131-134: first to fourth 7 to 3 encoder

140: selection control unit 150: selection unit

160: second higher bit generator 170: first higher bit generator

As a technical means for achieving the above object of the present invention, the present invention divides an input signal into a higher level and a lower level, and quantizes the input signal in comparison with a plurality of corresponding reference signals. Converts each input value into a higher data code and a lower data code, and applies an encoder to an A / D converter including a code generator for providing an upper / lower selection signal for selecting the upper data code or the lower data code. The switching unit may select the upper data code or the lower data code according to an upper / lower selection signal of the code generator. An encoder unit for encoding a plurality of data codes selected by the switching unit into a plurality of lower binary codes each having a predetermined bit; A selection control unit which provides a code selection signal according to a preset code among a plurality of data codes selected by the switching unit; A selection unit for selecting one of a plurality of output codes of the encoder unit according to a code selection signal of the selection control unit; A first upper bit generator for providing a first upper bit by using a preset data code among lower data codes of the switching unit and a preset data code among the upper data codes; And a second upper bit generator configured to provide a second upper bit by using a preset data code among the upper data codes of the switching unit.

Hereinafter, the configuration and operation of the high-speed encoder according to the present invention with reference to the accompanying drawings will be described in detail. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

The A / D converter to which the high speed encoder of the present invention is applied divides an input signal into a high level and a low level by using a folding interpolation technique, and quantizes the input signal by comparing with a plurality of corresponding reference signals. Each level input value is converted into an upper data code Inb and a lower data code In, and an upper / lower selection signal SS for selecting the upper data code Inb or the lower data code In It includes a code generator 110 to provide.

FIG. 6 is a block diagram of a 64 to 6 encoder according to the present invention. Referring to FIG. 6, the high speed encoder according to the present invention includes the upper data according to the upper / lower selection signal SS of the code generator 110. A switch 120 that selects a code Inb or a lower data code In, and an encoder that encodes a plurality of data codes selected by the switch 120 into a plurality of lower binary codes each having a predetermined bit. A selection control unit 140 for providing a code selection signal CS according to a preset code among a plurality of data codes selected by the switching unit 120, and a code of the selection control unit 140. A selection unit 150 for selecting one of a plurality of output codes of the encoder 130 according to a selection signal CS, a data code set in advance among lower data codes In of the switching unit 120, and , Previously set among the higher data codes (Inb) A first higher bit generator 160 providing a first higher bit using a data code, and a second higher bit using a data code preset among the upper data codes Inb of the switching unit 120; It includes a second higher bit generator 170 for providing.

Here, the high speed encoder of the present invention encodes 64 data codes into 6-bit binary codes at a high speed of about 200Msps, and distinguishes the lower 32 and the upper 32 by folding interpolation. It is possible to fold and separate each of the 32 folded data codes to provide a 6-bit binary code that eventually encodes the input 64 bits into the output 6 bits.

FIG. 7 is an input / output code table for explaining the code generator of FIG. 6. Referring to FIG. 7, the code generator 110 divides an input signal into 64 equal levels in order of level, and divides the 64 input data into 32 upper ranks. The data code Inb1-32 and the 32 lower data codes In1-In32 are provided, and the switching unit 120 is configured to identify the uppermost data code or the lower data code based on the input In1. Lsb6).

FIG. 8 is a configuration diagram of the switching unit of FIG. 6, FIG. 9 is an operation explanatory diagram of the RF F / F of FIG. 8, and FIG. 10 is a configuration diagram of the multiplexer of FIG. 8. 8 through 10, the switching unit 120 converts the 32 upper data codes Inb1-32 and 32 lower data codes In1-In32 of the code generator 110 into a constant code. The RS latch unit 121 and the 32 upper data codes Inb1-32 or 32 lower data codes In1-In32 outputted by the RS latch unit 121 to the upper / lower selection signal SS. It includes a multiplexer unit 122 to select according to.

FIG. 11 is a code table for describing an operation of the encoder of FIG. 6. Referring to FIG. 11, the encoder 130 may include 32 lower data codes In or 32 selected by the switching unit 120. The upper data code Inb is encoded into a plurality of output codes each having three bits (Lsb1-Lsb3).

The encoder 130 may include a first 7 to 3 encoder 121 for encoding seven In [2: 8] or Inb [2: 8] of the 32 data codes input into the first output code of three bits. A second 7 to 3 encoder 122 that encodes 7 In [10:16] or Inb [10:16] of the 32 data codes input into a 3 bit second output code, and 32 data inputs A third 7 to 3 encoder 123 for encoding seven In [18:24] or Inb [18:24] of the code into a third output code of three bits, and seven In [of 32 data codes inputted; 26:32] or Inb [26:32], which includes a fourth 7 to 3 encoder 124 that encodes a third bit of fourth output code.

The selection control unit 140 generates a code selection signal (CS: CS1, CS2) according to In [9, 17, 25] or Inb [9, 17, 25] of the plurality of data codes selected by the switching unit 120. The selector 150 may be configured to provide the first, second, third, and fourth output codes of the encoder 130 according to the code selection signal CS of the selection controller 140. And selects one to provide the lower three bits (Lsb1-Lsb3), wherein the second higher bit generator 160 is selected from In [17] of the lower data code In of the switching unit 120, and The second upper bit Lsb4 is provided using Inb [9,25] among the upper data codes Inb. The first upper bit generator 170 is configured to provide a first upper bit Lsb5 by using Inb [16, 17] among the upper data codes Inb of the switching unit 120.

Operation of the preferred embodiment of the present invention configured as described above will be described in detail below based on the accompanying drawings.

In the high-speed encoder of the present invention, analog signals encode 64 data codes into 6-bit binary codes at a high speed of about 200Msps, and the 64 data codes can be distinguished from the lower 32 and the upper 32 by folding interpolation. It folds and separates the folded 32 data codes to provide a 6-bit binary code that eventually encodes the input 64 bits into the output 6 bits.

6 to 12, the operation of the high speed encoder according to the present invention will be described. First, in FIG. 6, the switching unit 120 of the high speed encoder according to the present invention is higher / lower than the code generator 110. The upper data code Inb or the lower data code In is selected according to the selection signal SS. For example, when the upper / lower selection signal SS is "0", the lower data code In is selected. In the case of "1", the upper data code Inb may be selected.

Referring to the operation of the code generator 110 included in the A / D converter to which the high-speed encoder of the present invention is applied, the folding interpolation unit uses a folding interpolation technique to fold an input signal into a higher level and a lower level. Provide a level selection signal for dividing the upper level and the lower level, and then, a comparing unit quantizes the input signal by magnitude by comparing the lower level and the upper level with a plurality of reference signals, respectively, The latch section then holds the output of the comparison section.

Referring to FIG. 7, the code generator 110 provides 32 upper data codes Inb1-32 and 32 lower data codes In1-In32, and the switching unit 120 is input to In1. On the basis of this, the most significant bit Lsb6 for identifying the upper data code or the lower data code is provided. This most significant bit Lsb6 is output first of the output bits as shown in FIG.

8 to 9, the RS latch unit 121 of the switching unit 120 includes 32 upper data codes Inb1-32 and 32 lower data codes In1-1 of the code generator 110. In32) is converted into a predetermined code, and then the multiplexer 122 of the switching unit 120 receives the 32 upper data codes Inb1-32 or 32 lower lower codes output by the RS latch unit 121. The data codes In1-In32 are selected according to the upper / lower selection signal SS.

As shown in FIG. 9, each RS F / F of the RS latch unit 121 converts an input thermometer code into a constant signal, thereby converting the signal from 'high' to 'the' of the thermometer code. It keeps the signal constantly changing from 'low' or 'low' to 'High' as a constant signal, that is, logic "1" or "0", thus reducing the power consumption for continuous high-speed switching. .

6 to 8, the encoder unit 130 of the present invention has 32 latch outputs of the switching unit 120 (actually 62 including an inverting signal, and the first signal of the latch output is selected from the selection signal). The signal of the most significant bit (lsb6) is received as an input.Latch output shows that the latch signal is changed from signal 2 to signal 32 in the interval where the first signal of the latch is toggled (High-> Low). In the section where the first is "high", all the outputs of the latch are input to the lower data code In and the upper data code Inb as input to the encoder unit 130, and the first latch signal, the remaining section, is low. In the in period, if the lower data code (IN) is changed to the upper data code (INB) and the upper data code (INB) is changed to the lower data code (IN) through the switch and applied to the original logic, do.

Next, the encoder 130 encodes a plurality of data codes selected by the switching unit 120 into a plurality of lower binary codes each having a predetermined bit, which will be described later with reference to FIG. 11.

Referring to FIG. 11, the encoder unit 130 has 32 lower data codes In or 32 upper data codes Inb selected by the switching unit 120 each having 3 bits Lsb1 to Lsb3. The encoder 7 encodes a plurality of output codes. More specifically, the first 7 to 3 encoders 121 of the encoder unit 130 include 7 In [2: 8] or Inb [2 of 32 data codes. : 8] is encoded into the first output code of 3 bits, and the second 7 to 3 encoder 122 encodes 7 In [10:16] or Inb [10:16] of 3 out of 32 input data codes. And a third 7 to 3 encoder 123 converts 7 In [18:24] or Inb [18:24] out of 32 data codes into a 3 bit third output code. Encode The fourth 7 to 3 encoder 124 encodes seven In [26:32] or Inb [26:32] of the 32 data codes input into the fourth output code of three bits.

Next, the selection control unit 140 provides the code selection signals CS: CS1 and CS2 according to a preset code among a plurality of data codes selected by the switching unit 120. The selection control unit 140 provides a code selection signal CS according to In [9,17,25] or Inb [9,17,25] among the plurality of data codes selected by the switching unit 120. This is shown in Table 1 below.

Input [9,17,25] Selection signal (CS) 25 17 9 CS1 CS2 0 0 0 0 0 0 0 One 0 One 0 One One One 0 One One One One One

Next, the selection unit 150 selects one of a plurality of output codes of the encoder unit 130 according to the code selection signal CS of the selection control unit 140. The selector 150 selects one of the first, second, third, and fourth output codes of the encoder 130 according to the code selection signal CS of the selection controller 140 to lower three bits. (Lsb1-Lsb3) is provided.

As described above, the selector 150 has a structure of a fast condition selection encoder that obtains lsb [3: 1] by using four selectors therein, and up to lsb [3: 1] input. It converts all the numbers in and outputs it, which means that lsb [3: 1] has a repeating value when considering binary code. The criterion for selecting this is to select some of the first to fourth output codes of the encoder 140, i.e., some of the lsb [3: 1], by the combination of Lsb [9,17,25]. The choice is made.

For example, the 6-bit binary numbers "000111" and "001111" have the same value as lsb [3: 1] with 111, which can be obtained by signals 2 through 8 and 10 through 16 of the latch, respectively. These values use different inputs, which in each case have the same delay. Eventually, lsb [3: 1] is obtained using signals 2 through 8 and 10 through 16 of the encoder 140. Lsb 4,5 values (00 and 01) using signals 9 and 17, which are not used here, select lsb [3: 1] to obtain the desired lsb [3: 1]. Can be. In this way, the encoder section output code of one of the four encoders of the encoder section 140, which can make lsb [3: 1] that can be obtained in advance as the input of the encoder, is selected by the selection signal CS (00, 01, 10, 11). Selector 150 selects and provides lsb [3: 1].

6, 8 and 11, in the encoder generating lsb [3: 1], LSB3 is equal to IN4, and LSB2 is obtained by outputting IN6 when LSB3 is '1'. If it is '0', it can be obtained by outputting IN2. If LSB3 and LSB2 are '1', IN7 is obtained. If LSB3 is '1' and LSB2 is '0', IN5 is outputted. If LSB3 is '0', LSB2 and LSB1 can be obtained in the same way.

Next, the first upper bit generator 160 uses a data code preset in the lower data code In of the switching unit 120 and a data code preset in the upper data code Inb. A first upper bit is provided, which will be described in detail. The second upper bit generating unit 160 includes In [17] among the lower data codes In of the switching unit 120 and the upper data code. Among Inb, Inb [9, 25] is used to provide a second upper bit Lsb4.

Next, the second higher bit generator 170 provides a second higher bit by using a data code preset among the upper data codes Inb of the switching unit 120. The first upper bit generator 170 may provide a first upper bit Lsb5 using Inb [16,17] among the upper data codes Inb of the switching unit 120. High speed encoder.

12 is a graph showing an output delay time. Referring to FIG. 12, in the encoder of the present invention, as described above, the critical path is three stages, which is smaller than that of a conventional encoder, and accordingly, an encoder The circuit delay, the critical delay, can be reduced, and conditional select can be used to improve delay and power consumption.

As described above, the biggest feature of the high-speed encoder of the present invention is a switch block that uses a smaller signal drive buffer than the previous one for high-speed operation, and reduces the power consumption of the latch output signal that is continuously toggled. By simply connecting the proposed low power latch in front of the encoder, the encoder can operate with a certain value so that the gain can be gained in the power plane, and lsb [3: 1] becomes a critical path. In order to effectively obtain the signal, the entire input signal is taken simultaneously and the number of cases up to lsb [3: 1] is calculated. Finally, the lsb [6: 4] is computed at the same time as the input. have.

According to the present invention as described above, by converting an input signal such as an output video signal or an audio signal into a lower bit by using a folding interpolation technique, by implementing the encoding technique to select the lower bit by using an upper bit, the input signal It is possible to reduce the critical path for the high-speed processing to the BCD code of a predetermined bit, thereby reducing the delay time is possible to high-speed processing, it is possible to reduce the power consumption by reducing the current consumption.

More specifically, the delay and power consumption can be improved by using the condition selection method proposed to reduce the critical delay, which is the problem of the encoder circuit, and the proposed RS latch in the switching circuit. The output of "Return to Zero" is made "Non return to zero" to reduce the power consumption of the clock switching, reducing the power of the circuit by 40% in terms of speed and power in comparison with the 6-bit encoder in general. More than 50% of reduction was seen. In addition, according to the above, it is possible to manufacture an encoder that can operate at 500MHz using a 0.35㎛ processor, which can operate in less than 0.5ns in the process of 0.18㎛ or less currently used in applications of more than 1㎓ It is expected to be applicable to high-speed ADCs that can be applied.

The above description is only a description of specific embodiments of the present invention, and the present invention is not limited to these specific embodiments, and various changes and modifications of the configuration are possible from the above-described specific embodiments of the present invention. It will be apparent to those skilled in the art to which the present invention pertains.

Claims (9)

The input signal is divided into a high level and a low level, and quantized by comparison with a plurality of corresponding reference signals, and each of the quantized high level input value and the low level input value is respectively an upper data code Inb and a lower data code In. And an encoder applied to an A / D converter including a code generator 110 for providing an upper / lower selection signal SS for selecting the upper data code Inb or the lower data code In. To A switching unit (120) for selecting the upper data code (Inb) or the lower data code (In) according to the upper / lower selection signal (SS) of the code generator (110); An encoder 130 for encoding a plurality of data codes selected by the switching unit 120 into a plurality of lower binary codes each having a predetermined bit; A selection control unit 140 for providing a code selection signal CS according to a preset code among a plurality of data codes selected by the switching unit 120; A selection unit 150 for selecting one of a plurality of output codes of the encoder unit 130 according to the code selection signal CS of the selection control unit 140; A first higher bit generator that provides a first upper bit by using a data code preset in the lower data code In of the switching unit 120 and a data code preset in the upper data code Inb. 160; And And a second upper bit generator (170) for providing a second upper bit by using a data code preset in the upper data code (Inb) of the switching unit (120). The method of claim 1, wherein the switching unit 120 And a high order bit (Lsb6) for identifying the upper data code or the lower data code based on the input In1. The method of claim 2, wherein the code generator 110 provides 32 upper data codes Inb1-32 and 32 lower data codes In1-In32, The switching unit 120 includes an RS latch unit 121 for converting 32 upper data codes Inb1-32 and 32 lower data codes In1-In32 of the code generator 110 into a predetermined code; A multiplexer unit 122 for selecting 32 upper data codes Inb1-32 or 32 lower data codes In1-In32 output by the RS latch unit 121 according to the upper / lower selection signal SS. High speed encoder). The method of claim 3, wherein the encoder unit 130 A high speed encoder, characterized by encoding the 32 lower data codes (In) or 32 upper data codes (Inb) selected by the switching unit 120 into a plurality of output codes having 3 bits (Lsb1-Lsb3). . The method of claim 4, wherein the encoder unit 130 A first 7 to 3 encoder 121 for encoding seven In [2: 8] or Inb [2: 8] of the 32 data codes input into a first output code of three bits; A second 7 to 3 encoder 122 for encoding seven In [10:16] or Inb [10:16] of the 32 data codes to be input into a third output code of three bits; A third 7 to 3 encoder 123 for encoding seven In [18:24] or Inb [18:24] of the 32 data codes input into a third output code of three bits; And And a fourth 7 to 3 encoder 124 for encoding seven In [26:32] or Inb [26:32] of the 32 data codes input into the fourth output code of three bits. High speed encoder. The method of claim 5, wherein the selection control unit 140 And a code select signal (CS) according to In [9, 17, 25] or Inb [9, 17, 25] among a plurality of data codes selected by the switching unit (120). The method of claim 6, wherein the selection unit 150 The lower 3 bits Lsb1 to Lsb3 are selected by selecting one of the first, second, third and fourth output codes of the encoder 130 according to the code selection signal CS of the selection controller 140. High speed encoder, characterized in that provided. The method of claim 7, wherein the second higher bit generator 160 The second upper bit Lsb4 is provided by using In [17] in the lower data code In of the switching unit 120 and Inb [9,25] in the upper data code Inb. High speed encoder. 10. The method of claim 8, wherein the first higher bit generator 170 The high speed encoder according to claim 1, wherein the first upper bit (Lsb5) is provided using Inb [16,17] among the upper data codes (Inb) of the switching unit (120).