KR20040008909A - Data processing unit and method with multi-request channel DMA - Google Patents

Abstract

PURPOSE: A data processing device and method including multi request channel direct memory access is provided to increase a processing speed by supplying a plurality of processing paths as to a specific master of a multi-master, thereby exchanging data with other slave instead of a split state in a plurality of split states. CONSTITUTION: A plurality of multi masters and a plurality of multi slaves transmit/receive data to a system bus(100). The master(123) is a DMA unit and includes two DMA channel(123-1) and DMA channel(123-2) capable of exchanging data interactively and independently by a DMA request signal. Two DMA request signals(DMA_req1, DMA_req2) are generated, the first DMA channel(123-1) is opened by the first DMA request signal(DMA_req1), and data are exchanged. In addition, the second DMA channel(123-2) is opened by the second DMA request signal(DMA_req2), and data are exchanged. Two DMA channel are not opened simultaneously, and thus one DMA channel is opened selectively.

Description

Data processing unit and method with multi-request channel DMA

The present invention relates to a data processing apparatus having a multimaster, and more particularly, to provide a multi-request channel direct memory access that can exchange data with a slave even in a split state by providing a plurality of processing paths to a specific master among the multimasters. It relates to a data processing apparatus provided.

Most systems equipped with microprocessors have a central data bus, and different units with different speeds can be connected to each other. According to the request and use permission, the unit can input / output data with the authority of the bus, and the slave unit receives the data from the bus or outputs the required data according to the manual request.

1 is a block diagram of a conventional data processing apparatus.

Referring to FIG. 1, a conventional data processing apparatus includes a plurality of multi masters 21-23 and multiple slaves 31-34 for exchanging data with a system bus 10, and has one DMA 23. As slaves, each slave 21-23 interacts with the bus by a DMA request signal DMA_req.

In the data processing apparatus as described above, the master and the slave send and receive data through the bus. Since the master operates through the system clock, the data processing speed is high, while the slaves may have relatively slow data processing speed.

In a data processing device having different processing speeds as described above, when one master acquires the authority of a bus and exchanges data with a desired slave, the data is divided and remaining when the slave cannot process longer than a specified time. The data is exchanged later. This data exchange method is called a split data transfer method.

At this time, the slave generates a split signal, which takes a long time to process the current data, and thus is a signal to pass the bus to another master.

Using the split data exchange method as described above, a bus can be used by any other master except for the master exchanging data with the slave, thereby partially preventing the bus from being idle without transmitting any data. .

However, in the split data transfer method, when a slave having a slow processing speed generates a split signal by using a DMA, the master, which has exchanged data with the slave requesting the split, is transferring split data with the slave, and thus may be used for other data exchange. Can't. Therefore, the master does not actually perform any data processing, and there is a problem of waiting for the slow processing of the slave to end in an idle state.

In addition, if another master uses the bus for another data exchange, the frequency of bus usage can be maintained. However, if the master is stuck in the split, the bus becomes idle, which reduces the efficiency of the bus. There was a problem of deterioration.

In particular, the direct memory access (DMA) unit in the master is connected to the memory by a DMA request signal and is frequently used as a master.This DMA unit requests data exchange from another slave while exchanging data with a slow processing slave. When the system enters the split state when there is a problem, all systems are stopped until the processing of the slave having the slow processing speed is completed.

The present invention solves the problems of the prior art as described above, and the present invention provides a plurality of processing paths for a specific master of the multimaster, so that data can be exchanged with a slave other than the split state even in a plurality of split states. It is an object of the present invention to provide a multi-request channel data processing apparatus and method that can improve the processing speed.

1 is a block diagram of a data processing apparatus having a conventional multimaster;

2 is a block diagram of a data processing apparatus having multi-request channel direct memory access according to an embodiment of the present invention;

3 is a configuration diagram of a DMA unit having a multi-request channel in the data processing apparatus of the present invention;

4 is a waveform diagram for explaining the operation of the data processing apparatus of the present invention;

* Description of the symbols for the main parts of the drawings *

100: system bus 121-123: multi-master

123-1, 123-2: DAM channel 131-133: multi slave

The present invention for achieving the above object is a system bus; A plurality of multi-masters and multi-slaves for exchanging data, wherein a specific master of the plurality of multi-masters operates as an independent master and exchanges data independently by a plurality of request signals. It is characterized by providing a data processing apparatus having a.

The specific master is a DMA unit, in which a plurality of DMA channels exchange data with a slave corresponding to each other independently by a plurality of DMA request signals, and a plurality of DMA channels of the DMA unit are not opened at the same time. Only one corresponding DMA channel of the plurality of DMA channels is selectively opened by one corresponding request signal to exchange data with the corresponding slave.

The present invention is a system bus; A data processing apparatus comprising a plurality of multi masters and multiple slaves for exchanging data, and wherein one of the plurality of multi masters is a DMA unit having a plurality of DMA channels capable of exchanging data independently of each other. When one of the plurality of DMA channels exchanges data with the slave according to a DMA request signal generated from a corresponding one of the slaves of the slave, and the slave requests splitting during the data exchange with the DMA channel, The DMA channel is split, and the remaining DMA channel is characterized in that it provides a data processing method for exchanging data with the remaining slaves except the slave in the data exchange according to the DMA request signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.

2 is a block diagram of a data processing apparatus of the present invention.

Referring to FIG. 2, the data processing apparatus of the present invention includes a plurality of multi masters 121-123 and multiple slaves 131-133 for exchanging data with the system bus 100. One master 123 of the plurality of multi-masters 121-123 is a DMA unit, and includes two DMA channels (DMA channels 1 and 123-1), each capable of exchanging data independently by a DMA request signal. (DMA channels 2 and 123-2).

In the present invention, two DMA request signals DMA_req1 and DMA_req2 are generated, and the first DMA channel 123-1 of the two DMA channels 123-1 and 123-2 is generated by the first DMA request signal DMA_req1. The data is opened to exchange data, and the second DMA channel 123-2 is opened by the second DMA request signal DMA_req2 to exchange data.

At this time, two DMA channels 123-1 and 123-2 are not opened at the same time, and only one of them is selectively opened.

The operation of the data processing apparatus of the present invention having the configuration as described above will be briefly described as follows.

First, the DMA request signal DMA_req generated from a corresponding slave among the plurality of slaves 131 to 133 is detected, and it is determined whether data exchange with the slave that generated the DMA request signal DMA_req is possible. As a result, when data can be exchanged with the slave that generated the DMA request signal DMA_req, an acknowledgment is generated to exchange data with the slave. In this case, the request signal is also called a request channel, and a plurality of request signals are called a multi request channel.

For example, the first DMA channel 123-1 of the two DMA channels 123-1 and 123-2 is opened by the first DMA request signal DMA_req1 to exchange data. When the slave exchanging data with 123-1 generates a split signal and requests split, the second DMA channel 123-2 is opened by the second DMA request signal DMA_req2.

Therefore, the second DMA channel 123-2 exchanges data with the remaining slaves except the split slave. Thus, one DMA unit 123 operates like two masters, and the idle state of the bus due to the operation stop of the DMA in which the slave having a slow processing speed occurs is prevented.

In the embodiment of the present invention, one DMA unit is illustrated as having two DMA channels, but a plurality of DMA channels are provided to exchange data independently by a plurality of DMA channel request signals as described above. It may be.

3 is a block diagram of a DMA unit 123 having two DMA channels and operating as independent masters in the data processing apparatus of FIG. 2.

The DMA unit 123 has respective buffers for a pure DMA memory block 123-8, a channel switch 123-7, a first DMA channel 123-1 and a second DMA channel 123-2. And control bus blocks 123-3 and 123-4, and respective system bus interface logic blocks 123-5 and 123 for the first DMA channel 123-1 and the second DMA channel 123-2. -6) each.

The pure DMA block 123-8 is a block that interfaces with a memory and performs an operation of reading and writing to a memory with an address and data. Since the channel switch 123-7 has only one pure memory block 123-8, which is a path for reading and writing data in the memory, for two DMA channels 123-1 and 123-2. It is a control logic for multiplexing the signals provided from the DMA channels 123-1 and 123-2 to the pure DMA block 123-8 by the DMA request signals DMA_req1 and DMA_req2.

Which channel of the two DMA channels 123-1 and 123-2 is open to exchange data and whether the other channel is to be exchanged due to splitting during data exchange. Should be judged.

The buffer and control blocks 123-3 and 123-4 of each channel are composed of conventional circuits that support reading and writing of a plurality of buffers, and circuits that need to store a state when a split occurs. It is.

The system bus interface logic blocks 123-5 and 123-6 of the respective channels maintain appropriate states for the respective DMA channels 123-1 and 123-2 to function as bus masters. Will perform the action.

4 shows an operation waveform diagram illustrating an operation in which two DMA channels 123-1 and 123-2 exchange data independently of each other in the data processing apparatus of the present invention.

Referring to FIG. 4, when two DMA channels 123-1 and 123-2 exchange data independently from each other, the first slave 131 of the multi-slaves 131-133 is multi-master. If a DMA request signal (DMA_req_slave 1) is generated that requests the use of the DMA unit 123 among the 121-123, the first DMA channel 123- of the DMA unit 123 at the moment when the DMA request signal DMA_req_slavw1 is activated. In 1), it is determined whether to permit the slave.

If it is determined that it is possible to use the first DMA channel 123-1 of the DMA unit 123 for the first slave 131, the permission signal DMA_ch1_ack is activated. When the permission signal DMA_ch1_ack becomes active, it can be seen that normal data exchange occurs with the first slave 131, so that data exchanged with the first slave 131 is loaded on the data bus 100.

The first slave 131 always reports the status of the data exchange. The first slave 131 shows a signal of Respond_slave 1 as a result of the report. At first, the first slave 131 generates a NORMAL signal to process the data normally. Report that it is done.

When a certain time elapses during the report, a split signal is generated, and it takes too much time to process the current data, thereby generating a signal to immediately pass the bus to another master.

At this time, the second slave 132 generates a request signal DMA_req_slave2 for using the DMA unit 123. When the request signal DMA_req_slave2 is activated, the second channel 123-2 of the DMA unit 123 is activated. ) Will open to exchange data. Therefore, data exchanged with the second slave 132 is carried on the system bus 100.

As described above, when the split signal occurs while the first slave 131 exchanges data, the DMA permission signal DMA_ack is not generated in the prior art, so that the DMA unit does not exchange data with the first slave 121. I could not wait to complete other processing until it was completed. However, in the present invention, the permission signal (DMA_ch2_ack) is generated on the second DMA channel 123-2 of the DMA unit 123, and the second DMA channel 123-2 is opened to exchange data with the second slave 132. .

As described above, the present invention provides a plurality of data processing paths in the DMA unit to enable data exchange with other slaves even in the split state, thereby preventing the idle state of the bus and improving the processing speed.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (5)

System bus; It has a number of multi masters and multiple slaves to send and receive data, And a specific master of the plurality of multi-masters includes a plurality of channels that operate as independent masters and exchange data independently from each other by a plurality of request signals. The method of claim 1, The specific master is a DMA unit, and the data processing apparatus is characterized in that a plurality of DMA channels exchange data with corresponding slaves independently of each other by a plurality of DMA request signals. The method of claim 2, A plurality of DMA channels of the DMA unit is not opened at the same time, only a corresponding DMA channel of the plurality of DMA channels is selectively opened by a corresponding one of the plurality of DMA request signals to exchange data with the corresponding slave. Data processing apparatus. The method of claim 3, wherein The corresponding DMA request signal is generated from a corresponding one of the plurality of slaves. System bus; A data processing apparatus having a plurality of multi masters and multiple slaves for exchanging data, wherein the one of the plurality of multi masters is a DMA unit having a plurality of DMA channels capable of exchanging data independently of each other. One of the plurality of DMA channels exchanges data with the slave according to the DMA request signal generated from the corresponding one of the plurality of slaves, If the slave requests a split during data exchange with the DMA channel, the DMA channel during the data exchange is in a split state, and the remaining DMA channels exchange data with the remaining slaves except the slave with the data exchange according to the DMA request signal. Data processing method characterized in that.