KR101065585B1 - Dynamic memory controller, multi-media application processorMAP apparatus comprising the same controller, and method of accessing the same dynamic memory - Google Patents

Abstract

The present invention provides a dynamic memory controller and a multimedia application processor (MAP) device including the controller, and a dynamic memory access method for controlling access to dynamic memory through a multi-port efficiently. The dynamic memory controller includes an interface unit (date I / F unit) having at least two or more data slave I / Fs connected to the data bus through multiple ports; And connected between the interface unit and dynamic RAM (DRAM) so that each port of the multi-port can access a different bank of the dynamic memory. And an input / output controller configured to control data input / output to the dynamic memory through a pre command, wherein the input / output controller is configured to issue an act command to other ports while a first port of the multi-port is being accessed. Applying to dynamic memory allows the other ports to access the dynamic memory even before the access of the first port is terminated.

Description

Dynamic memory controller, multi-media application processor (MAP) apparatus comprising the same controller, and method of accessing the same dynamic memory }

The present invention relates to a computer processor device of the present invention, and more particularly, to a dynamic memory controller for controlling access to a dynamic memory and a multimedia application processor (MAP) device including the controller.

In general, dynamic memory, that is, DRAM (Dydamic Random Access Memory) is used as a main memory of the computer, the development of the performance of its high-speed operation is steadily made. However, the operation speed of the DRAM does not keep up with the operation speed of the processor, the performance of which is being improved further. For this reason, DRAM access and cycle times are hindering the performance of computer systems.

Recently, the trend is to use synchronous DRAMs, ie, synchronous DRAMs (SDRAMs), which operate in synchronization with clock signals, for computers so that the DRAMs can be used in processors operating at high speeds. In addition, with the use of SDRAM, multimedia application processor (MAP) devices or complex System on Chip (SoC) devices are using multi-port rather than single-port. This is to increase the bus utilization of the data bus when accessing the SDRAM from the master block.

On the other hand, the SDRAM is formed in banks, and each bank of the multi-port accesses each bank of the SDRAM to input and output data. Each port's access to SDRAM is controlled by the SDRAM controller. If any port is currently being accessed by one bank, no other port can access it, and all the I / O operations for the port being accessed must be performed before the next port can be accessed.

In general, data input / output to the SDRAM by the SDRAM controller is performed by data input / output signals synchronized with a clock signal. That is, through an act, a data input / output instruction, and a pre-charge instruction. In the related art, a pre-charge command must be performed on a port currently being accessed to perform an act command on the next port. Here, the act command corresponds to a signal indicating the start of access to the corresponding port, and the data input / output command corresponds to a signal for actually inputting / outputting the data of the corresponding port by reading or writing to the dynamic memory, and the pre-charge command Corresponds to the signal indicating that the input / output operation for the port has been completed.

Accordingly, there is a current aspect in which time for waiting for an act instruction after a data input / output instruction to which data is actually input / output is wasted. As a result, access to SDRAM is not fully utilized, and as a result, communication with the processor is still insufficient.

Accordingly, an object of the present invention is to provide a dynamic memory controller and a multimedia application processor (MAP) device including the controller, and a dynamic memory access method for controlling access to dynamic memory through a multi-port efficiently. There is.

In order to achieve the above object, the present invention provides an interface unit having at least two or more data slave I / F (data slave I / F) connected to the data bus via a multi-port (date I / F unit); And connected between the interface unit and dynamic RAM (DRAM) so that each port of the multi-port can access a different bank of the dynamic memory. And an input / output controller configured to control data input / output to the dynamic memory through a pre command, wherein the input / output controller is configured to issue an act command to other ports while a first port of the multi-port is being accessed. And applying to dynamic memory to allow the other ports to access the dynamic memory even before access of the first port is terminated.

In the present invention, the dynamic memory includes a synchronous dynamic memory (SDRAM), a double speed synchronous dynamic memory (Double Date Rate-SDRAM: DDR-SDRAM), a double speed synchronous dynamic memory (Double Date Rate 2-SDRAM: DDR2). SDRAM), and double dynamic synchronous dynamic memory 3 (Double Date Rate 3 -SDRAM: DDR3-SDRAM) can be any of these.

In addition, the dynamic memory controller may include an arbitration device connected between the interface unit and the input / output controller to selectively connect the data slave interface to the input / output controller.

In an embodiment of the present invention, the data bus may be an advanced high performance bus (AHB), and the input / output controller may determine an address mapping control unit for determining a start address and an address increment of a dynamic memory according to a command from the AHB. A row / column address mapping unit for converting the address and the address increment determined by the mapping controller to match the dynamic memory command format, and the act for accessing the multiport to the dynamic memory. And a state machine unit for generating a data input / output signal having a data input / output signal and a pre-charge command signal.

In the present invention, when two of the multi-ports are attempting to access the dynamic memory, the act instruction for the second port to the dynamic memory before performing the pre-charge command for the first port being accessed. Can be applied. For example, a control signal for data input / output may include an act command for the first port, a data input / output command for the first port, an act command for the second port, a data input / output command for the second port, and the first port. The pre-charge command for the second port and the pre-charge command for the second port.

In the present invention, when three or more ports of the multi-ports are attempting to access the dynamic memory, the control signal for data input / output is transmitted to the second port before performing the pre-charge command for the first port being accessed. May be applied in the order of the act command for the second port, the act command for the third port before performing the pre-charge command for the second port, and the act instruction for the n + 1 port before performing the pre-charge command for the n-th port. have. Meanwhile, the data input / output command may be selectively applied between the pre-charge commands according to the size of data.

The present invention also provides a processor unit having a core processor to achieve the above object; A memory unit having a dynamic memory; A controller unit having a dynamic memory controller of claim 1; And a data bus connecting each component of the controller unit and each component of the processor unit.

In the present invention, when two of the multi-ports are attempting to access the dynamic memory, an act command for the second port may be authorized before performing the pre-charge command for the first port being accessed. In addition, when three or more ports of the multi-ports are attempting to access the dynamic memory, a control signal for data input / output may be applied to the second port before performing a pre-charge command on the first port being accessed. It may be applied in order of an act command, an act command for a third port before performing a pre-charge command for the second port, and an act command for an n + 1 port before performing a pre-charge command for the n-th port. .

Furthermore, in order to achieve the above object, the present invention provides a method for inputting / outputting data into different banks of dynamic memory in which each port of a multi-port connected to a data bus is provided. Applying an act command; Applying a data input / output command for the first port to the dynamic memory after the act command; And applying a pre-charge command for the first port to the dynamic memory when data input / output is terminated, and before the pre-charge command, execute an act command for another port to the dynamic memory for the other port. The data input / output method according to claim 1, wherein the other port is accessible to the dynamic memory during the access of the first port.

According to the present invention, the data input / output method includes a method for a second port between a data input / output command and a pre-charge command step for the first port when two ports of the multi ports are attempting to access the dynamic memory. Applying an act command, and applying a data input / output command for the second port, and applying a pre-charge command for the second port after the pre-charge command for the first port. It may include.

In addition, the data input / output method may, when three or more of the multi-ports are attempting to access the dynamic memory, issue an act command to the second port before applying the pre-charge command to the first port. Authorizing, acting on a third port prior to issuing a pre-charge command for the second port, and performing a pre-charge command on the nth port before performing an n + 1 port. And may apply the act command.

The dynamic memory controller and its dynamic memory access method according to the present invention have been generated by waiting for a precharge command for a port being accessed by issuing an Act command to another port in advance even while any arbitrary port is accessing the dynamic memory. The waste of time can be significantly reduced.

Accordingly, the dynamic memory controller and the dynamic memory access method of the present invention can be utilized in various application processors using dynamic memory, including multimedia application processor, by enabling dynamic memory utilization, shortening the access time, and smooth communication with the processor. Can be.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when a component is described as being connected to another component, it may be directly connected to another component, but a third component may be interposed therebetween. In addition, in the drawings, the structure or size of each component is exaggerated for convenience and clarity of explanation, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. It is to be understood that the terminology used is for the purpose of describing the present invention only and is not used to limit the scope of the present invention.

1 is a schematic block diagram of a dynamic memory controller structure according to an embodiment of the present invention.

Referring to FIG. 1, the dynamic memory controller 100 according to the present exemplary embodiment includes an interface unit (date I / F unit) 110, an input / output controller 130, and an arbitration device 120. Here, the interface unit 110 includes at least two data slave I / Fs, the input / output controller 130 controls data input / output to the dynamic memory 300, and the mediation apparatus includes an input / output controller ( The connection between the 130 and the interface unit 110.

In more detail, the interface unit 110 is composed of two or more slave interfaces 112 and connected to the data bus 200, for example, an advanced high performance bus (AHB) through a multi-port. In other words, the interface unit 110 is a multi-port interface. Meanwhile, the interface unit 110 also includes a resist slave interface 114 connected by a register. This resist slave interface 114 receives a register access command from the AHB 200. Here, the AHB is taken as an example of the data bus, but the data bus is not limited to the AHB. That is, all kinds of data buses that can be connected through multi-ports can be used in this embodiment.

Each slave interface 112 of the interface unit 110 receives a data access command from the AHB 200 and accesses the dynamic memory, such as the SDRAM 300. On the other hand, access to SDRAM 300 is a selective access, not a concurrent access. The device for such selective access is the arbitration device 120. The arbitration apparatus 120 selects only an access command of one slave interface among multiple ports, that is, data access commands input through a plurality of slave interfaces, and transmits the selected command to the next processor, that is, the input / output controller 130.

The input / output controller 130 includes an address mapping control unit 132, an address mapping unit 134, and a state machine 136. The input / output controller 130 receives a data access command from the slave interface 112 to control actual data input / output to the SDRAM 300.

Briefly explaining the functions of the respective components of the input and output control unit 130,

The address mapping controller 132 appropriately determines the start address and address increment of the memory, that is, the SDRAM, in accordance with the transferred data access command. In addition, the address mapping unit 134 converts the address and the address increment determined by the address mapping control unit 132 to conform to the SDRAM 300 data input / output command format. On the other hand, the state machine 136 is a final output terminal of the input / output control unit 130, generates an actual SDRAM data input and output command, and controls the data input and output to the SDRAM. For example, data input / output instructions include act instructions, data input / output instructions such as read or write, and pre-charge instructions.

Meanwhile, the flash counter 140 disposed in the dynamic memory controller 100 continuously refreshes the dynamic memory. The read buffer 150 temporarily stores data output from the SDRAM and transfers the data to the address mapping control unit 132.

Unlike the conventional method, the dynamic memory controller 1000 applies a data input / output command to the SDRAM 300 so that the multi-port can quickly access the SDRAM 300. That is, in the case of SDRAM, when multiple ports attempt to access different banks, the act command is not limited to the pre-charge command for the port currently being accessed. Thus, an act command for another port, for example a second port, may be applied to the SDRAM before receiving a pre-charge command for the port being accessed, for example the first port. Accordingly, even if the first port is accessing the SDRAM, the second port can be accessed to the SDRAM. Of course, input / output of data by the second port is possible after substantial data input / output by the first port being accessed is performed. However, the act command for the second port is applied before the pre-charge command of the first port and the data input / output for the second port is performed immediately after the data input / output of the first port. Very fast access to SDRAM.

A description of the process of accessing the SDRAM to the SDRAM will be described in more detail through a timing diagram in the description of FIGS. 2 and 3.

In the present embodiment, the SDRAM has been described as an example, but dynamic memory, that is, double date synchronous dynamic memory (Double Date Rate-SDRAM: DDR-SDRAM), double speed synchronous dynamic memory 2 (Double Date Rate 2-SDRAM: DDR2-SDRAM) Of course, the dynamic memory controller of the present embodiment can be applied to all dynamic memories such as double speed synchronous dynamic memory 3 (Double Date Rate 3-SDRAM).

FIG. 2 is a timing diagram in which two ports access dynamic memory through the dynamic memory controller of FIG. 1.

Referring to FIG. 2, while the port 0, that is, the first port is accessing and writing data to the dynamic memory, an act command ACT B1 is applied to the port 1, the second port. In addition, a write command WR_CMD B1 for the second port is applied immediately after the actual writing of the data to the first port is completed, and data writing is performed. Then, the pre-charge command PRE B0 is applied to the first port, and when the writing of data to the second port is finished, the pre-charge command PRE B1 is applied to the second port so that the SDRAM for the second port is applied. I / O to the data is terminated.

Conventionally, since the act command for the second port was issued after the pre-charge command for the first port, access is possible after the clock timing T8 or the second port, and the data write was subsequently made. However, when accessing using the dynamic memory controller of the present embodiment, the act command for the second port is applied after the clock timing T3, so that the data for the second port immediately after the write of the actual data to the first port is finished. Writing can proceed. Thus, the time until the command for pre-charge after writing data to the first port and then the time until the act command for the second port can be shortened.

In the figure, the act command for the second port is written to the clock immediately after the first port data write command WR_CMD B0, but it may be in any clock if data write in progress of the first port is in progress. Further, the data write command WR_CMD B1 for the second port may also be at any clock after the end of writing to the first port. However, in order to make access to the second port as fast as possible, it is preferable that a data write command for the second port is applied to the next clock immediately after the end of the data write for the first port. In conclusion, an Act command and a Data Write command for another port may be authorized at any clock before the pre-charge command for the port being accessed. However, as described above, the data write command may be applied only after the actual data write to the port is terminated during the access. Although only the data writing is described so far, the same principle can be applied to data reading.

3 is a timing diagram in which three ports access dynamic memory through the dynamic memory controller of FIG. 1.

Referring to FIG. 3, after a data write command for port 0, that is, a first port, an act command for port 1, that is, a second port, is applied, and data for the second port immediately after completion of data write for the first port. A write command is authorized, followed by a pre-charge command for the first port. On the other hand, immediately after the pre-charge command for the first port, an act command for port 2, that is, a third port, is applied, and when data writing to the second port ends, a data write command for the third port is applied. Then a pre-charge command for the second port is applied. Finally, when data writing to the third port is terminated, a pre-charge command for the third port is applied.

Although the timing diagram in the figure illustrates a case where three ports access dynamic memory, data input / output commands may be applied in the same order even when more ports attempt access. That is, an act command for the fourth port is applied after the pre-charge command PRE B1 for the second port, and a data write command for the fourth port is applied when data writing to the third port is terminated. Continuous dynamic memory access is possible.

Meanwhile, such three or more multi-port access operations are not limited to the illustrated timing diagram. That is, the act command and the data write command for the next port to be accessed may be located at any clock before the pre-charge command for the port currently being accessed. However, as described above, the data write command is possible after the actual data write of the accessing port is finished. Therefore, the data write command for the next access port is preferably located at the next clock immediately after the data write of the accessing port is finished. Do.

Up to now, as explained through the clock timing diagram, the dynamic memory controller of this embodiment applies each of the slave interfaces of the multi-port by applying an Act command or a data write command to another port before the pre-charge command to the port being accessed. To allow them to access dynamic memory quickly. Thus, in any computer processor device or system, such as a multimedia application processor (MAP) device or a complex System on Chip (SoC) system, that accesses SDRAM through multiple ports, the dynamic memory controller of the present embodiment may utilize the data bus. utilization, and also enables smooth communication with high speed processors.

4 is a block diagram of a multimedia application processor device including the dynamic memory controller of FIG. 1 according to another embodiment of the present invention.

Referring to FIG. 4, the multimedia application processor (MAP) device of the present embodiment may include a processor unit 4000 including a core processor (CPU) 4100, a direct memory access (DMA) 4200, and the like. The memory unit 2000 including the memory 2100, the NAND flash 2200, and the like, and the controller unit 1000 and the controller unit 1000 including the dynamic memory controller 100 and the NAND flash memory controller 200. It includes a data bus 3000 that connects each component of the and the components of the processor 4000.

The data bus 3000, for example, AHB, is connected to each component of the controller unit 1000 through a multi-port, and is also connected to each of the components in the controller unit 1000 through a multi-port. For example, a plurality of slave interfaces in the dynamic memory controller 100 are connected through a multi port. On the other hand, the data bus 3000 is not limited to the AHB as described above.

The dynamic memory controller 100 of the multimedia application processor device of the present embodiment has the structure described with reference to FIG. 1 to access each port of the slave interface to the dynamic memory 2100, for example, SDRAM. The dynamic memory controller 100 accesses each port to the SDRAM as described with reference to FIGS. 2 and 3. Meanwhile, the dynamic memory here is not limited to SDRAM, but double-speed synchronous dynamic memory (Double Date Rate-SDRAM: DDR-SDRAM), double-speed synchronous dynamic memory 2 (Double Date Rate2-SDRAM: DDR2-SDRAM), 2 Any dynamic memory using multiple ports, such as Double Date Rate 3-SDRAM (DDR3-SDRAM) is applicable.

Therefore, the multimedia application processor device of the present embodiment uses a dynamic memory such as SDRAM as the main memory and controls access to the dynamic memory through the dynamic memory controller 100 described above. Accordingly, the multimedia application processor device of the present embodiment can smoothly and efficiently transmit data between the core processor 4100 or various peripheral devices related to the multimedia and the like through dynamic ports.

5A is a flowchart illustrating a process in which two ports access dynamic memory according to another embodiment of the present invention.

Referring to FIG. 5A, the present embodiment first applies an act command for a first port to a dynamic memory (S100), and then applies a data input / output command, for example, a write or read command, for a next port to a dynamic memory. (S110). Next, an act command for the second port is applied before the pre-charge command for the first port (S120), and when data input / output for the first port is completed, the data input / output command for the second port is applied to the dynamic memory ( S130).

Thereafter, a pre-charge command for the first port is applied (S140), and when data input / output for the second port is terminated, the pre-charge command for the second port is finally applied to the dynamic memory ( S150), dynamic memory access to the first and second ports is terminated.

In the dynamic memory access method through the two ports of the present embodiment, the act command for the second port is previously applied to the dynamic memory before the pre-charge command for the first port being accessed is applied, so that The waste of access time wasted while waiting for the pre-charge command.

FIG. 5B is a flowchart illustrating a process in which N ports access dynamic memory when two ports of FIG. 5A are expanded to N ports.

Referring to FIG. 5B, the access method of the present embodiment is a case where the port is expanded to three or more, and the basic principle is similar to that of FIG. 5A. In more detail, when N is 1, the process of applying a pre-charge command for the first port to the dynamic memory (S240) is the same as the process of FIG. 5A. However, if more ports are attempted to access, after determining whether the N + 1 port, that is, the second port is the port to which the last access is attempted (S250), and if there is a next port to access, that is, a third port That is, the act command for the third port is performed after the pre-charge command for the first port (S220).

This process continues until the last port appears, and if the N + 1 port is the last port, the pre-charge command for N + 1 is applied to the dynamic memory (S260), thereby completing the access process for all ports. do.

The dynamic memory access method of this embodiment shows an example in which three or more multi-ports access dynamic memory through a dynamic memory controller. Therefore, as long as the act instruction for the other port is applied to the dynamic memory before the pre-charge instruction for the port being accessed is granted, the various ports can access the dynamic memory through a different order from the present embodiment. .

The dynamic memory access method of this embodiment shows that even when there are three or more multi-ports attempting to access, the dynamic memory can be accessed at high speed in the same manner when two ports are used. It can be seen that it is possible to further reduce the access time of.

So far, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a schematic block diagram of a dynamic memory controller structure according to an embodiment of the present invention.

FIG. 2 is a timing diagram in which two ports access dynamic memory through the dynamic memory controller of FIG. 1.

3 is a timing diagram in which three ports access dynamic memory through the dynamic memory controller of FIG. 1.

4 is a block diagram of a multimedia application processor device including the dynamic memory controller of FIG. 1 according to another embodiment of the present invention.

5A is a flowchart illustrating a process in which two ports access dynamic memory according to another embodiment of the present invention.

FIG. 5B is a flowchart illustrating a process in which N ports access dynamic memory when two ports of FIG. 5A are expanded to N ports.

Claims (17)

An interface unit (date I / F unit) having at least two data slave I / Fs connected to the data bus via multiple ports; And Connected between the interface unit and dynamic RAM (DRAM) to allow each port of the multi-port to access a different bank of dynamic memory, And an input / output controller configured to control data input / output to the dynamic memory through an act, data input / output, and pre-charge command. The input / output controller may include a first port of the multiports in a first bank of the dynamic memory. Applying an act instruction to other dynamic ports during access to the dynamic memory, thereby allowing the other ports to access another bank of the dynamic memory even before the access of the first port is terminated controller. The method according to claim 1, The dynamic memory may be a synchronous dynamic memory (SDRAM), a double speed synchronous dynamic memory (Double Date Rate-SDRAM: DDR-SDRAM), a double speed synchronous dynamic memory (Double Date Rate 2-SDRAM: DDR2-SDRAM), 2 A dynamic memory controller, characterized in that at least one of double speed synchronous dynamic memory 3 (Double Date Rate 3-SDRAM). The method according to claim 1, Dynamic memory controller, And an arbitration device connected between the interface unit and the input / output control unit to selectively connect the data slave interface to the input / output control unit. The method according to claim 1, The data bus is an AHB (Advanced High performance Bus), The input / output controller may include an address mapping control unit for determining a start address and an address increment of a dynamic memory according to a command from the AHB, and converting the address and address increment determined by the address mapping control unit into the dynamic memory command format. Generating a data input / output signal having an address mapping unit which converts to fit, and the act, data input / output and pre-charge command signals for accessing the multi-port to the dynamic memory. A dynamic memory controller comprising a state machine unit. 5. The method of claim 4, When two of the multi-ports are trying to access the dynamic memory, And apply an act command for a second port to the dynamic memory before performing a pre-charge command for the first port being accessed. 6. The method of claim 5, The control signal for data input / output may include an act command for the first port, a data input / output command for the first port, an act command for the second port, a data input / output command for the second port, and a command for the first port. And a pre-charge command for the second port and a pre-charge command for the second port. 5. The method of claim 4, When three or more of the multi-ports are trying to access the dynamic memory, The control signal for data input / output may include an act command for a second port before performing a pre-charge command for the first port being accessed, an act command for a third port before performing a pre-charge command for the second port, and Dynamic memory controller, characterized in that is applied in the order of act command for the n + + 1 port before performing the pre-charge command for the n-th port. The method according to claim 6 or 7, The data input / output command may be selectively applied between the pre-charge commands according to the size of data. The method according to claim 1, The dynamic memory controller is used in a computer processor device that uses an access method to the dynamic memory through a multi-port. The method according to claim 1, The data slave is connected to the data bus through the multi port, And the input / output control unit is connected between the interface unit and the dynamic memory to control each port of the multi-port to access different banks of the dynamic memory. A processor unit having a core processor; A memory unit having a dynamic memory; A controller unit having a dynamic memory controller of claim 1; And And a data bus connecting the respective components of the controller unit and the respective components of the processor unit. A method in which each port of a multiport connected to a data bus inputs and outputs data to different banks of dynamic memory, Applying an act command to the dynamic memory for a first port of the multi-ports; Applying a data input / output command for the first port to the dynamic memory after the act command; And And applying a pre-charge command to the first port to the dynamic memory when data input / output is terminated. Applying an act instruction to another port to the dynamic memory before the pre-charge command, such that the other port can access another bank of the dynamic memory while the first port is accessing the first bank of the dynamic memory. Data input and output method characterized in that. 13. The method of claim 12, The dynamic memory may be a synchronous dynamic memory (SDRAM), a double speed synchronous dynamic memory (Double Date Rate-SDRAM: DDR-SDRAM), a double speed synchronous dynamic memory (Double Date Rate 2-SDRAM: DDR2-SDRAM), 2 A data input / output method comprising at least one of double speed synchronous dynamic memory 3 (Double Date Rate 3-SDRAM). 13. The method of claim 12, The act, input / output, and pre-charge command signals are data input / output signals for access control of each port to the dynamic memory, and in a state machine of a dynamic memory controller controlling data input / output to the dynamic memory. And a data input / output method, characterized in that it is generated. 13. The method of claim 12, Data input / output method When two of the multi-ports are trying to access the dynamic memory, Applying an act command for a second port between a data input / output command for the first port and a pre-charge command step, and applying a data input / output command for the second port, And applying a pre-charge command for a second port after the pre-charge command for the first port. 13. The method of claim 12, The data input / output method is When three or more of the multi-ports are trying to access the dynamic memory, The act instruction for the third port may be issued before the act of applying a pre-charge command to the second port, the act of applying a pre-charge command to the second port. And authorizing an act command for the n + 1th port prior to performing the pre-charge command for the nth port. The method according to claim 15 or 16, The data input / output command may be selectively applied between the pre-charge commands according to the size of data.

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