KR20040008489A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20040008489A KR20040008489A KR1020020042128A KR20020042128A KR20040008489A KR 20040008489 A KR20040008489 A KR 20040008489A KR 1020020042128 A KR1020020042128 A KR 1020020042128A KR 20020042128 A KR20020042128 A KR 20020042128A KR 20040008489 A KR20040008489 A KR 20040008489A
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- South Korea
- Prior art keywords
- bit line
- plug
- line contact
- storage electrode
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000003860 storage Methods 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 I형 활성영역을 적용하여 반도체소자의 고집적화 및 넷 다이(net die)를 증가시킴으로써 소자의 수율을 향상시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which improves the yield of a device by applying an I-type active region to increase integration of a semiconductor device and increase a net die. .
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 제조방법을 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1 은 종래기술에 따른 반도체소자의 제조방법에 의해 형성된 소자의 레이아웃도이다.1 is a layout diagram of a device formed by a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(도시안됨)에 활성영역(12)을 정의하는 소자분리영역(10)을 형성한다. 이때, 상기 활성영역(12)은 T형으로 형성된다.First, an isolation region 10 defining an active region 12 is formed on a semiconductor substrate (not shown). In this case, the active region 12 is formed in a T-shape.
다음, 상기 반도체기판 상부에 게이트절연막(도시안됨), 게이트전극용 도전층(도시안됨) 및 마스크절연막(도시안됨)의 적층구조를 형성한다. 이때, 상기 마스크절연막은 질화막 또는 산화막으로 형성된다.Next, a stacked structure of a gate insulating film (not shown), a gate electrode conductive layer (not shown), and a mask insulating film (not shown) is formed on the semiconductor substrate. In this case, the mask insulating film is formed of a nitride film or an oxide film.
그 다음, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴이 적층되는 게이트전극(14)을 형성한다.Next, the stack structure is etched using a gate electrode mask as an etch mask to form a gate electrode 14 on which a mask insulating film pattern is stacked.
다음, 전체표면 상부에 상기 활성영역(12)에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분을 노출시키는 제1층간절연막(도시안됨)을 형성한다.Next, a first interlayer insulating film (not shown) is formed on the entire surface to expose portions of the active region 12, which are intended to be bit line contacts and storage electrode contacts.
그 다음, 전체표면 상부에 도전층(도시안됨)을 증착한 후 평탄화시켜 상기 콘택홀을 매립하는 랜딩플러그(15)를 형성한다. 이때, 상기 랜딩플러그(15)는 상기 활성영역(10)과 완전히 중첩되도록 형성되며 상기 비트라인 콘택으로 예정되는 랜딩플러그(15)와 저장전극 콘택으로 예정되는 랜딩플러그(15)는 일직선상에 형성되지 않는다.Next, a conductive layer (not shown) is deposited on the entire surface and then planarized to form a landing plug 15 filling the contact hole. In this case, the landing plug 15 is formed to completely overlap the active region 10, and the landing plug 15 intended as the bit line contact and the landing plug 15 intended as the storage electrode contact are formed in a straight line. It doesn't work.
다음, 전체표면 상부에 비트라인 콘택으로 예정되는 부분을 노출시키는 비트라인 콘택홀이 구비되는 제2층간절연막(도시안됨)을 형성한다. 이때, 상기 비트라인 콘택홀은 상기 랜딩플러그(15)와 완전히 중첩되도록 형성된다.Next, a second interlayer insulating film (not shown) having a bit line contact hole for exposing a portion intended as a bit line contact is formed over the entire surface. In this case, the bit line contact hole is formed to completely overlap the landing plug 15.
그 다음, 상기 비트라인 콘택홀을 통하여 상기 랜딩플러그(15)에 접속되는 비트라인 콘택플러그(16)를 형성한다.A bit line contact plug 16 is then formed which is connected to the landing plug 15 through the bit line contact hole.
다음, 상기 비트라인 콘택플러그(16)에 접속되는 비트라인(18)을 형성한다.Next, a bit line 18 connected to the bit line contact plug 16 is formed.
그 다음, 전체표면 상부에 저장전극 콘택으로 예정되는 부분을 노출시키는 저장전극 콘택홀(도시안됨)을 구비하는 제3층간절연막(도시안됨)을 형성한다.Next, a third interlayer insulating film (not shown) having a storage electrode contact hole (not shown) exposing a portion intended as the storage electrode contact is formed over the entire surface.
이때, 상기 저장전극 콘택홀은 상기 비트라인 콘택홀과 일직선 상에 형성되지 않는다.In this case, the storage electrode contact hole is not formed in line with the bit line contact hole.
다음, 상기 저장전극 콘택홀을 통하여 상기 랜딩플러그(15)에 접속되는 저장전극 콘택플러그(19)를 형성한다. (도 1 참조)Next, a storage electrode contact plug 19 connected to the landing plug 15 is formed through the storage electrode contact hole. (See Figure 1)
그러나, 상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 활성영역이 T형으로 형성되고, 랜딩플러그 형성 시 후속공정으로 형성되는 비트라인 콘택플러그 및 저장전극 콘택플러그와의 중첩을 고려하여 상기 랜딩플러그의 면적을 확보하기 위하여 셀 크기가 증가되어 웨이퍼에서 넷 다이(net die)의 효율이 저하되고, 그에 따른 공정 수율을 저하시키는 문제점이 있다.However, in the method of manufacturing a semiconductor device according to the related art as described above, the active region is formed in a T-type, in consideration of overlapping with a bit line contact plug and a storage electrode contact plug, which are formed in a subsequent process when forming a landing plug. In order to secure the area of the landing plug, the cell size is increased, and thus the efficiency of the net die in the wafer is reduced, and thus the process yield is reduced.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 활성영역을 I형으로 형성하고, 상기 활성영역에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분에 접속되는 랜딩플러그를 형성하되, 상기 랜딩플러그 상부의 면적을 감소시키지 않고 넷 다이 효율을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, forming an active region of the I-type, and forming a landing plug connected to the portion of the active region to be scheduled as a bit line contact and a storage electrode contact, the landing plug It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the net die efficiency without reducing the area of the upper portion.
도 1 은 종래기술에 따른 반도체소자의 제조방법에 의해 형성된 소자의 레이아웃도.1 is a layout view of a device formed by the method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법에 의한 레이아웃도.2A to 2D are layout views according to a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10, 30 : 소자분리영역 12, 32 : 활성영역10, 30: isolation region 12, 32: active region
14, 34 : 게이트전극 15, 36 : 랜딩플러그14, 34: gate electrode 15, 36: landing plug
16, 38 : 비트라인 콘택플러그 18, 40 : 비트라인16, 38: bit line contact plug 18, 40: bit line
19, 42 : 저장전극 콘택플러그19, 42: storage electrode contact plug
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판에 활성영역을 정의하는 소자분리영역을 형성하되, 상기 활성영역은 I형으로 형성하는 공정과,Forming a device isolation region defining an active region on the semiconductor substrate, wherein the active region is formed in an I-type;
상기 반도체기판 상부에 게이트절연막을 형성한 후, 게이트전극 및 소오스/드레인영역으로 구성된 트랜지스터를 형성하는 공정과,Forming a transistor including a gate electrode and a source / drain region after forming a gate insulating film over the semiconductor substrate;
전체표면 상부에 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분에 접속되는 랜딩플러그를 구비하는 제1층간절연막을 형성하되, 상기 랜딩플러그는 상기 활성영역과 일직선상에 형성하는 공정과,Forming a first interlayer insulating film having a landing plug connected to a portion defined as a bit line contact and a storage electrode contact on an entire surface, the landing plug being formed in line with the active region;
전체표면 상부에 상기 랜딩플러그에 접속되는 비트라인 콘택플러그를 구비하는 제2층간절연막을 형성하되, 상기 랜딩플러그와 비트라인 콘택플러그는 소정 두께 중첩되도록 형성하는 공정과,Forming a second interlayer insulating film having a bit line contact plug connected to the landing plug on the entire surface, wherein the landing plug and the bit line contact plug are formed to overlap a predetermined thickness;
전체표면 상부에 상기 랜딩플러그에 소정 두께 접속되는 저장전극 콘택플러그를 구비하는 제3층간절연막을 형성하되, 상기 저장전극 콘택플러그는 상기 비트라인 콘택플러그와 일직선상에 형성되지 않도록 형성하는 공정과,Forming a third interlayer insulating film having a storage electrode contact plug connected to the landing plug at a predetermined thickness on an entire surface thereof, wherein the storage electrode contact plug is not formed in line with the bit line contact plug;
상기 비트라인 콘택플러그 및 저장전극 콘택플러그는 상기 랜딩플러그의 상부 및 측벽에 접속되는 것을 포함하는 것을 특징으로 한다.The bit line contact plugs and the storage electrode contact plugs may be connected to upper and sidewalls of the landing plugs.
이하, 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법에 의한 레이아웃도이다.2A to 2D are layout views according to a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(도시안됨)에 활성영역(32)을 정의하는 소자분리영역(30)을 형성한다. 이때, 상기 활성영역(12)은 I형으로 형성된다.First, an isolation region 30 defining an active region 32 is formed on a semiconductor substrate (not shown). At this time, the active region 12 is formed in the I-type.
다음, 상기 반도체기판 상부에 게이트절연막(도시안됨), 게이트전극용 도전층(도시안됨) 및 마스크절연막(도시안됨)의 적층구조를 형성한다. 이때, 상기 마스크절연막은 질화막 또는 산화막으로 형성된다.Next, a stacked structure of a gate insulating film (not shown), a gate electrode conductive layer (not shown), and a mask insulating film (not shown) is formed on the semiconductor substrate. In this case, the mask insulating film is formed of a nitride film or an oxide film.
그 다음, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴이 적층되는 게이트전극(34)을 형성한다. (도 2a 참조)Next, the stack structure is etched using a gate electrode mask as an etch mask to form a gate electrode 34 on which a mask insulating film pattern is stacked. (See Figure 2A)
다음, 전체표면 상부에 상기 활성영역(32)에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분을 노출시키는 제1층간절연막(도시안됨)을 형성한다.Next, a first interlayer insulating film (not shown) is formed on the entire surface of the active region 32 to expose portions of the active region 32, which are intended as bit line contacts and storage electrode contacts.
그 다음, 전체표면 상부에 도전층(도시안됨)을 증착한 후 평탄화시켜 상기 콘택홀을 매립하는 랜딩플러그(36)를 형성한다. 이때, 상기 랜딩플러그(36)는 상기 활성영역(30)과 완전히 중첩되도록 형성되며 상기 비트라인 콘택으로 예정되는 랜딩플러그(36)와 저장전극 콘택으로 예정되는 랜딩플러그(36)는 일직선상에 형성된다. (도 2b 참조)Then, a conductive layer (not shown) is deposited on the entire surface and then planarized to form a landing plug 36 filling the contact hole. In this case, the landing plug 36 is formed to completely overlap the active region 30, and the landing plug 36 intended as the bit line contact and the landing plug 36 intended as the storage electrode contact are formed in a straight line. do. (See Figure 2b)
다음, 전체표면 상부에 비트라인 콘택으로 예정되는 부분을 노출시키는 비트라인 콘택홀이 구비되는 제2층간절연막(도시안됨)을 형성한다. 이때, 상기 비트라인 콘택홀은 상기 랜딩플러그(36)의 일측 일부에 중첩되도록 형성되며, 상기 랜딩플러그(36)의 상부 및 측면을 노출시킨다.Next, a second interlayer insulating film (not shown) having a bit line contact hole for exposing a portion intended as a bit line contact is formed over the entire surface. In this case, the bit line contact hole is formed to overlap a portion of one side of the landing plug 36, and exposes the top and side surfaces of the landing plug 36.
그 다음, 상기 비트라인 콘택홀을 통하여 상기 랜딩플러그(36)에 접속되는 비트라인 콘택플러그(38)를 형성한다.A bit line contact plug 38 is then formed which is connected to the landing plug 36 through the bit line contact hole.
다음, 상기 비트라인 콘택플러그(38)에 접속되는 비트라인(40)을 형성한다. (도 2c 참조)Next, a bit line 40 connected to the bit line contact plug 38 is formed. (See Figure 2c)
그 다음, 전체표면 상부에 저장전극 콘택으로 예정되는 부분을 노출시키는 저장전극 콘택홀(도시안됨)을 구비하는 제3층간절연막(도시안됨)을 형성한다. 이때, 상기 저장전극 콘택홀은 상기 랜딩플러그(36) 일측 일부에 중첩되도록 형성되며, 상기 랜딩플러그(36)의 상부 및 측면을 노출시킨다Next, a third interlayer insulating film (not shown) having a storage electrode contact hole (not shown) exposing a portion intended as the storage electrode contact is formed over the entire surface. In this case, the storage electrode contact hole is formed to overlap a portion of one side of the landing plug 36 and exposes the top and side surfaces of the landing plug 36.
이때, 상기 저장전극 콘택홀은 상기 비트라인 콘택홀과 일직선상에 형성되지 않는다.는다.In this case, the storage electrode contact hole is not formed in line with the bit line contact hole.
다음, 상기 저장전극 콘택홀을 통하여 상기 랜딩플러그(36)에 접속되는 저장전극 콘택플러그(42)를 형성한다. 이때, 상기 저장전극 콘택플러그(42)는 상기 비트라인 콘택플러그(38)가 랜딩플러그(36)에 접속되는 방향의 반대방향에 접속된다. (도 2d 참조)Next, a storage electrode contact plug 42 connected to the landing plug 36 is formed through the storage electrode contact hole. In this case, the storage electrode contact plug 42 is connected to a direction opposite to the direction in which the bit line contact plug 38 is connected to the landing plug 36. (See FIG. 2D)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 활성영역을 I형으로 형성하고, 상기 활성영역에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분에 접속되는 랜딩플러그를 형성한 후 상기 랜딩플러그에 접속되는 비트라인 콘택플러그 및 저장전극 콘택플러그를 형성함으로써 상기 랜딩플러그의 상부 및 측면을 콘택영역으로 사용하여 다이 내에서 셀효율을 증대시키고, 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the active region is formed in an I type, and after forming a landing plug connected to a portion of the active region which is intended to be a bit line contact and a storage electrode contact. By forming bit line contact plugs and storage electrode contact plugs connected to the landing plugs, the upper and side surfaces of the landing plugs are used as contact regions, thereby increasing cell efficiency in the die, and consequently, high integration of semiconductor devices is advantageous. There is this.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8084801B2 (en) | 2005-10-18 | 2011-12-27 | Samsung Electronics Co., Ltd. | Cell structure for a semiconductor memory device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8084801B2 (en) | 2005-10-18 | 2011-12-27 | Samsung Electronics Co., Ltd. | Cell structure for a semiconductor memory device and method of fabricating the same |
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