KR20040005385A - Method for forming gate in semiconductor device - Google Patents

Method for forming gate in semiconductor device Download PDF

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Publication number
KR20040005385A
KR20040005385A KR1020020039920A KR20020039920A KR20040005385A KR 20040005385 A KR20040005385 A KR 20040005385A KR 1020020039920 A KR1020020039920 A KR 1020020039920A KR 20020039920 A KR20020039920 A KR 20020039920A KR 20040005385 A KR20040005385 A KR 20040005385A
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South Korea
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hard mask
gate
pattern
forming
semiconductor device
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KR1020020039920A
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Korean (ko)
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조성필
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주식회사 하이닉스반도체
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Priority to KR1020020039920A priority Critical patent/KR20040005385A/en
Publication of KR20040005385A publication Critical patent/KR20040005385A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for forming a gate of a semiconductor device is provided to easily obtain fine line-width of a gate by etching sidewalls of a hard mask using isotropic etching. CONSTITUTION: A gate oxide layer(200), a conductive layer(300) and a hard mask are sequentially formed on a semiconductor substrate(100). A hard mask pattern is formed by selectively etching the hard mask. A fine hard mask pattern(400b) is formed by etching sidewalls of the hard mask pattern using isotropic etching of wet-etching. Then, the conductive layer is selectively etched using the fine hard mask pattern(400b) as a mask, thereby forming a gate.

Description

반도체 소자의 게이트 형성방법{METHOD FOR FORMING GATE IN SEMICONDUCTOR DEVICE}Gate forming method of semiconductor device {METHOD FOR FORMING GATE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는 게이트 선폭을 미세하게 형성할 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of forming a fine gate line width.

일반적으로, 반도체 소자에 있어서 스위칭(Switching) 기능은 게이트(Gate)와 소오스-드레인 (Source-Drain)으로 구성된 트랜지스터가 맡고 있는데, 신호전달 기능을 담당하는 게이트(Gate)는 반도체 소자를 구성하는 가장 중요한 라인중 하나로 인식된다.In general, a switching function of a semiconductor device is a transistor composed of a gate and a source-drain. The gate, which is responsible for the signal transmission function, is the most constituent of the semiconductor device. It is recognized as one of the important lines.

종래 기술에 따른 반도체 소자의 게이트 형성방법을 도 1 내지 도 4를 참조하여 설명하면 다음과 같다.A method of forming a gate of a semiconductor device according to the prior art will now be described with reference to FIGS. 1 to 4.

종래 기술에 따른 반도체 소자의 게이트 형성방법은, 도 1에 도시된 바와 같이, 반도체 기판(10)상에 게이트 산화막(20)과 폴리실리콘막(30) 및 하드마스크(40)를 형성한다. 계속하여, 게이트 패터닝을 하기 위하여 하드마스크(40)상에 감광막 패턴(50)을 형성한다.In the gate forming method of the semiconductor device according to the related art, as shown in FIG. 1, the gate oxide film 20, the polysilicon film 30, and the hard mask 40 are formed on the semiconductor substrate 10. Subsequently, the photoresist pattern 50 is formed on the hard mask 40 for gate patterning.

이어서, 도 2에 도시된 바와 같이, 감광막 패턴(50)을 마스크로 하는 건식각 공정으로 하드마스크(40)를 선택적으로 제거하여 하드마스크 패턴(40a)을 형성한다.Subsequently, as shown in FIG. 2, the hard mask 40 is selectively removed by a dry etching process using the photoresist pattern 50 as a mask to form the hard mask pattern 40a.

다음으로, 도 3에 도시된 바와 같이, 감광막 패턴(50)을 제거하고 하드마스크 패턴(40a)을 마스크로 하는 건식각으로 폴리실리콘막(30)을 선택적으로 제거하여 폴리실리콘막 패턴(30a)과 하드마스크 패턴(40a)으로 구성된 게이트(60)를 형성한다.Next, as shown in FIG. 3, the polysilicon film pattern 30a is removed by selectively removing the photoresist film pattern 50 and selectively removing the polysilicon film 30 by dry etching using the hard mask pattern 40a as a mask. And a gate 60 including the hard mask pattern 40a.

한편, 공정에 따라서는 하드마스크(40)를 형성하지 않을 수 있다.In some embodiments, the hard mask 40 may not be formed.

그러나, 종래 기술에 따른 반도체 소자의 게이트 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the conventional method of forming a gate of a semiconductor device has the following problems.

종래 기술에 있어서는, 예를 들어 248nm 파장을 갖는 DUV 스텝퍼(Deep Ultra Violet Stepper)라는 노광장비와 소정 형태의 감광막으로 일정 대상물을 패터닝하여 원하는 폭의 게이트를 형성한다.현재 사용되고 있는 DUV 스텝퍼를 기준으로 패터닝할 수 있는 한계는 약 100nm 정도까지이다. 이는 DUV 스텝퍼의 광원 파장이 248nm임을 감안할 때 이론적으로 패터닝할 수 있는 공정능력이다.In the prior art, for example, a target of a desired width is formed by patterning a predetermined object with an exposure apparatus called a DUV stepper having a wavelength of 248 nm and a photosensitive film of a predetermined type. A gate having a desired width is formed. The limit for patterning is up to about 100 nm. This is a theoretical capability to pattern, given that the light source wavelength of the DUV stepper is 248 nm.

그렇지만, 최근 집적도를 향상시키기 위한 일환으로 게이트 선폭을 100nm 이하로 패터닝하기 위해서는 광원파장이 193nm인 ArF 스캐너(Scanner) 등의 고가의 장비를 사용하여야 하며, 또한 이에 상응하는 감광막이 개발이 우선되어야 하는 등의 어려움이 있기 때문에 게이트 선폭의 미세화는 노광 장비와 감광막 패턴의 선폭에 의해 제한되고 있다.However, in order to improve the integration density in recent years, in order to pattern the gate line width to 100 nm or less, expensive equipment such as an ArF scanner having a light source wavelength of 193 nm should be used, and a corresponding photoresist film should be developed first. Due to such difficulties, the miniaturization of the gate line width is limited by the line width of the exposure equipment and the photoresist pattern.

이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 옥사이드 하드마스크와 습식각을 이용하여 미세한 선폭의 게이트를 형성할 수 있는 반도체 소자의 게이트 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above problems in the prior art, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of forming a gate having a fine line width using an oxide hard mask and wet etching. have.

도 1 내지 도 4는 종래 기술에 따른 반도체 소자의 게이트 형성방법을 도시한 공정별 단면도.1 to 4 are cross-sectional views illustrating processes of forming gates of semiconductor devices according to the related art.

도 5 내지 도 9는 본 발명에 따른 반도체 소자의 게이트 형성방법을 도시한 공정별 단면도.5 to 9 are cross-sectional views illustrating processes for forming gates of semiconductor devices according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100; 반도체 기판200; 게이트 산화막100; A semiconductor substrate 200; Gate oxide

300; 도전막400; 하드마스크300; Conductive film 400; Hard mask

400a; 하드마스크 패턴400b; 하드마스크 미세 패턴400a; Hard mask pattern 400b; Hardmask Fine Pattern

500; 감광막 패턴600; 게이트 패턴500; Photoresist pattern 600; Gate pattern

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 게이트 형성방법은, 반도체 기판상에 게이트 산화막과 도전막과 하드마스크를 순차로 형성하는 단계; 상기 하드마스크를 선택적으로 제거하여 하드마스크 패턴을 형성하는 단계; 상기 하드마스크 패턴을 일부 제거하여 하드마스크 미세 패턴을 형성하는 단계; 및 상기 하드마스크 미세 패턴을 마스크로 하는 식각으로 상기 도전막을 선택적으로제거하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a gate of a semiconductor device, the method comprising: sequentially forming a gate oxide film, a conductive film, and a hard mask on a semiconductor substrate; Selectively removing the hard mask to form a hard mask pattern; Removing a portion of the hard mask pattern to form a hard mask fine pattern; And selectively removing the conductive layer by etching using the hard mask fine pattern as a mask.

본 발명에 의하면, 노광 공정에 의해 형성될 수 있는 패턴의 한계를 습식 식각의 등방성 식각성을 이용하여 하드마스크 패턴 측벽을 식각하여 극복하는 것으로, 고가의 장비를 필요치 않고 기존의 장비들을 이용하여 더욱 미세한 게이트 선폭을 얻을 수 있는 잇점이 있다According to the present invention, by overcoming the limitation of the pattern that can be formed by the exposure process by etching the hard mask pattern sidewall by using the isotropic etching of wet etching, it is possible to use the existing equipment without using expensive equipment. The advantage is that a fine gate line width can be obtained.

이하, 본 발명에 따른 반도체 소자의 게이트 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a gate of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 5 내지 도 9는 본 발명에 따른 반도체 소자의 게이트 형성방법을 도시한 공정별 단면도이다.5 to 9 are cross-sectional views of processes illustrating a method of forming a gate of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 게이트 형성방법은, 도 5에 도시된 바와 같이, 반도체 기판(100)상에 게이트 산화막(200)과 도전막(300)과 하드마스크(400)를 순차로 형성한다. 이때, 상기 하드마스크(400)는 SiO2계열 물질로 형성한다.In the gate forming method of the semiconductor device according to the present invention, as shown in FIG. 5, the gate oxide film 200, the conductive film 300, and the hard mask 400 are sequentially formed on the semiconductor substrate 100. In this case, the hard mask 400 is formed of a SiO 2 based material.

계속하여, 상기 하드마스크(400)를 선택적으로 식각하기 위하여 사진 공정 등으로 상기 하드마스크(400)상에 일정한 형태를 지닌 감광막 패턴(500)을 형성한다.Subsequently, in order to selectively etch the hard mask 400, a photosensitive film pattern 500 having a predetermined shape is formed on the hard mask 400 by a photo process or the like.

이어서, 도 6에 도시된 바와 같이, 상기 감광막 패턴(500)을 마스크로 하는 식각 공정으로 상기 하드마스크(400)를 선택적으로 제거하여 하드마스크 패턴(400a)을 형성한다.Subsequently, as shown in FIG. 6, the hard mask 400 is selectively removed by an etching process using the photoresist pattern 500 as a mask to form the hard mask pattern 400a.

상기 하드마스크 패턴(400a)을 형성하는 단계는 C/F를 주성분으로 하는 플라즈마 건식각 공정을 이용한다.The hard mask pattern 400a may be formed by using a plasma dry etching process based on C / F.

이어서, 도 7에 도시된 바와 같이, 상기 하드마스크 패턴(400a)을 일부 제거하여 하드마스크 미세 패턴(400b)을 형성한다.Subsequently, as shown in FIG. 7, the hard mask pattern 400a is partially removed to form the hard mask fine pattern 400b.

상기 하드마스크 미세 패턴(400b)을 형성하는 단계는 HF를 포함하는 용액을 이용한 등방성 습식 식각 공정을 이용한다. 이와 같은 방법은 습식 식각 공정의 등방성 식각 성질을 이용하는 것으로 선택비가 높은 습식 식각은 상기 감광막 패턴(500)과 도전막(300)은 식각하지 않고 하드마스크 패턴(400a)의 측면만을 식각하는 성질을 이용한 것이다.The forming of the hard mask fine pattern 400b uses an isotropic wet etching process using a solution containing HF. This method uses the isotropic etching property of the wet etching process, and the wet etching with a high selectivity uses only the side surface of the hard mask pattern 400a without etching the photoresist pattern 500 and the conductive layer 300. will be.

다음으로, 도 8에 도시된 바와 같이, 상기 감광막 패턴(500)을 제거하고 상기 하드마스크 미세 패턴(400b)을 마스크로 하는 식각으로 상기 도전막(300)을 선택적으로 제거하여 도전막 패턴(300a)과 하드마스크 미세 패턴(400b)으로 구성된 게이트 패턴(600)을 완성한다.Next, as shown in FIG. 8, the photoresist layer pattern 500 may be removed, and the conductive layer 300 may be selectively removed by etching using the hard mask fine pattern 400b as a mask. ) And the gate pattern 600 including the hard mask fine pattern 400b is completed.

본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 게이트 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the gate forming method of the semiconductor device according to the present invention has the following effects.

본 발명에 있어서는, 노광 공정에 의해 형성될 수 있는 패턴의 한계를 습식 식각의 등방성 식각성을 이용하여 하드마스크 패턴 측벽을 식각하여 극복하는 것으로, 고가의 장비를 필요치 않고 기존의 장비들을 이용하여 더욱 미세한 게이트 선폭을 얻을 수 있는 잇점이 있다. 따라서, 생산원가의 감소를 가져오게 되어 제품 경쟁력을 제고할 수 있는 효과가 있다.In the present invention, by overcoming the limitation of the pattern that can be formed by the exposure process by etching the hard mask pattern sidewall by using the isotropic etching of wet etching, it is possible to use the existing equipment without using expensive equipment. There is an advantage in that a fine gate line width can be obtained. Therefore, the production cost is reduced, thereby improving the product competitiveness.

Claims (4)

반도체 기판상에 게이트 산화막과 도전막과 하드마스크를 순차로 형성하는 단계;Sequentially forming a gate oxide film, a conductive film, and a hard mask on the semiconductor substrate; 상기 하드마스크를 선택적으로 제거하여 하드마스크 패턴을 형성하는 단계;Selectively removing the hard mask to form a hard mask pattern; 상기 하드마스크 패턴을 일부 제거하여 하드마스크 미세 패턴을 형성하는 단계; 및Removing a portion of the hard mask pattern to form a hard mask fine pattern; And 상기 하드마스크 미세 패턴을 마스크로 하는 식각으로 상기 도전막을 선택적으로 제거하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.And selectively removing the conductive layer by etching using the hard mask fine pattern as a mask. 제1항에 있어서,The method of claim 1, 상기 하드마스크는 SiO2계열 물질로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The hard mask is a gate forming method of a semiconductor device, characterized in that formed with a SiO 2 series material. 제1항에 있어서,The method of claim 1, 상기 하드마스크 패턴을 형성하는 단계는 C/F를 주성분으로 하는 플라즈마 건식각 공정을 이용하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The forming of the hard mask pattern is a method of forming a gate of a semiconductor device, characterized in that using a plasma dry etching process containing a C / F as a main component. 제1항에 있어서,The method of claim 1, 상기 하드마스크 미세 패턴을 형성하는 단계는 HF를 포함하는 용액을 이용한등방성 습식 식각 공정을 이용하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The forming of the hard mask fine pattern may include forming an isotropic wet etching process using a solution containing HF.
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US8513070B2 (en) 2011-06-13 2013-08-20 Samsung Display Co., Ltd. Methods of manufacturing wire, TFT, and flat panel display device

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KR19990075153A (en) * 1998-03-18 1999-10-15 윤종용 Method of forming fine pattern of semiconductor device
JP2000223476A (en) * 1999-02-02 2000-08-11 Fujitsu Quantum Device Kk Fabrication of semiconductor device
JP2001230233A (en) * 2000-02-16 2001-08-24 Mitsubishi Electric Corp Method for manufacturing semiconductor device

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Publication number Priority date Publication date Assignee Title
KR19990075153A (en) * 1998-03-18 1999-10-15 윤종용 Method of forming fine pattern of semiconductor device
JP2000223476A (en) * 1999-02-02 2000-08-11 Fujitsu Quantum Device Kk Fabrication of semiconductor device
JP2001230233A (en) * 2000-02-16 2001-08-24 Mitsubishi Electric Corp Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513070B2 (en) 2011-06-13 2013-08-20 Samsung Display Co., Ltd. Methods of manufacturing wire, TFT, and flat panel display device

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