KR20030002510A - Method of forming merged memory-logic device and merged memory-logic device thereof - Google Patents

Abstract

PURPOSE: A method for fabricating a merged memory logic(MML) device is provided to form a G-poly layer which has uniform thickness and depth and is bilateral, by forming an oxide layer mask on a memory cell area including the G-poly layer through an oxidation process. CONSTITUTION: The cell area and a logic device area are defined on a semiconductor substrate(20). A gate polysilicon layer is formed on the entire surface of the memory cell area and the logic device area. An anti-reflective coating(ARC) is formed on the entire surface of the gate polysilicon layer. A photoresist layer is formed on the entire surface of the ARC. A photoresist pattern exposing the ARC formed in the upper portion of a memory cell in the memory cell area is formed. The ARC is removed by using the photoresist pattern as an etch mask to expose the gate polysilicon layer. The photoresist pattern is eliminated. The gate polysilicon layer exposed to the upper portion of the memory cell is oxidized to form the oxide mask(34). The ARC remaining in the memory cell area is removed.

Description

Method for forming a memory-logic merged device and a device thereby {Method of forming merged memory-logic device and merged memory-logic device}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for forming a semiconductor device and a device therefrom, and more particularly to a method for forming a memory-logic merged device and a device therefrom.

In the recent semiconductor industry, DRAM-logic merged or flash memory-logic merged devices can be used to produce DRAM or Flash memory and logic devices for higher value-added and more versatile products. We are developing such chips.

In particular, in the case of a flash-logic integrated device, the process of forming a transistor is a key to product development. Hereinafter, a general flash-logic merger and its problems will be described with reference to the accompanying drawings.

1 through 3 are cross-sectional views illustrating a problem with a general memory-logic merger.

Referring to FIG. 1, a floating polysilicon layer 104 (F-poly film) and an insulator cell oxide layer 106 are sequentially formed on a semiconductor substrate 100 including an active region. The F-poly film 104 and the cell oxide film 106 are separated from the left and right from the common source electrode 108 to be formed in the memory cell region A. FIG. Here, the memory cell region A refers to a region where a memory cell is formed in the memory-logic merged device. In addition, the part except the memory cell part A is called a logic element part B. FIG. Subsequently, a gate polysilicon layer 102 (hereinafter, referred to as a G-poly layer) is formed on the memory cell region A and the logic element region B in front.

Fig. 2 is a cross sectional view showing a memory cell portion A including memory cells of a preferred memory-logic merger. Referring to FIG. 2, the gate polysilicon film 110 (hereinafter referred to as G-poly film) having a uniform thickness and height is symmetrically formed on the sidewalls of the cell oxide film 106 and the F-poly film 104. Here, reference numeral 102 ′ is a portion remaining on the top of the memory cell after the G-poly layer 102 is etched. Meanwhile, in order for the memory-logic merger to operate normally, the thickness and height of the symmetrically present G-poly film 110 must be constant.

Fig. 3 is a sectional view showing an actual memory-logic merging element. Referring to FIG. 3, the G-poly film 110 obtained by etching the G-poly layer 102 is not uniform in height and thickness due to intrusion during the etching process. In this case, there is a problem that the erase and program characteristics of the left and right cells of the symmetrically present G-poly film 110 are changed. Because, if the area of the symmetrical G-poly film 110 is different, the overlap capacitance between the G-poly film 110 and the F-poly film 104 is different. This results in a difference in voltage applied to the F-poly film 104. Another reason for the difference in erase characteristics is that when the overlap area is reduced, the coupling ratio and the efficiency of the erase are reduced.

In order to solve the asymmetry problem of the G-poly film 110, a process of adding a chemical-physical polishing (CMP) and a cell open photo process has been developed.

4 through 10 are process cross-sectional views illustrating a conventional memory-logic merger.

Referring to FIG. 4, a memory cell is formed using an F-poly film 104 sequentially formed in a memory cell portion A on a semiconductor substrate 100 including an active region and a cell oxide film 106 as an insulator. . At this time, the F-poly film 104 and the cell oxide film 106 are separated to the left and right by using the common source electrode 108 in common. Here, the memory cell region A refers to a region where a memory cell is formed in the memory-logic merged device. In addition, the part except memory cell part A is called logic element part B. As shown in FIG. Subsequently, the G-poly layer 102 is formed on the entire surface of the memory cell region A and the logic element region B. Next, an antireflection layer 202 and a middle oxide layer 204 to be used as masks when forming the gate electrode in the logic device are sequentially formed on the entire surface of the G-poly layer 102.

Referring to FIG. 5, the photoresist layer 206 covering the logic element region is formed, and the anti-reflection layer 202 and the mesophilic oxide film 204 on the cell portion are removed using a wet etching process.

Referring to FIG. 6, after removing the photoresist layer 206 by performing a strip process, a silicon nitride layer 208 may be formed on the entire surface of the memory cell region A and the logic element region B. SiN film) is formed.

Referring to FIG. 7, the SiN film 208 is planarized using a CMP process to expose the G-poly layer 102 on top of the memory cell.

Referring to FIG. 8, when the G-poly layer 102 of the memory cell is exposed, the exposed portion is oxidized to form an oxide mask 210. Here, the oxide mask 210 is used as a mask when forming a G-poly film (see 110 in FIG. 2) to be formed in a memory cell. At this time, the logic element portion does not undergo an oxidation process due to the SiN film 208. Next, the SiN film 208 is removed.

Referring to FIG. 9, in order to form a gate pattern in the logic element region B, the memory cell region A is covered using a photoresist, and the logic element region is a photoresist pattern 212 for forming a gate electrode. To form. Subsequently, the exposed MTO film 202 and the anti-reflection layer 202 are etched up to the G-poly layer 102 using the protoresist pattern 212 as a mask to form mask patterns 202 'and 204'. Next, the photoresist pattern 212 is removed.

Referring to FIG. 10, the G-poly layer 102 is etched using the mask patterns 202 ′ and 204 ′ to form a gate structure. In this way, the symmetric G-poly film 106 can be obtained.

By the way, the symmetrical G-poly film 106 can be obtained, but a problem arises in the process of forming the gate electrode in the logic element region B by using the CMP process. That is, during the CMP planarization process, the MTO film 204 and the anti-reflection layer 202 may be invaded to form a desired gate electrode. In addition, an end portion of the oxide mask mask 210 formed in the memory cell region A is sharpened, so that the end portion is separated in a subsequent etching process so that a uniform G-poly film is not formed.

Accordingly, an aspect of the present invention is to provide a method of forming a memory-logic merged device, which forms a G-poly film having a uniform symmetry with uniform thickness and height and does not perform a CMP process.

In addition, another technical problem to be achieved by the present invention is to provide a memory-logic integrated device having a G-poly film having a uniform symmetry of uniform thickness and height, and a gate electrode that is not invaded by CMP.

1 to 3 are cross-sectional views illustrating a general memory-logic merger.

4 through 10 are process cross-sectional views illustrating a conventional memory-logic merger.

11 through 15 are cross-sectional views illustrating the memory-logic merger according to the present invention.

* Explanation of symbols for the main parts of the drawings.

20; Semiconductor substrate 22; Gate polysilicon layer

24; Floating polysilicon film 26; Cell oxide

28; Common source electrode 30; Antireflection layer

32; Photoresist layer 34; Oxide mask

36; Photoresist pattern 38; Gate polysilicon film

According to an aspect of the present invention, there is provided a method of forming a memory-logic merged device, including forming a memory cell portion and a logic element portion on a semiconductor substrate, and forming a gate on the front surface of the memory cell portion and the logic element portion. Forming a polysilicon layer, forming an antireflection layer on the entire surface of the gate polysilicon layer, forming a photoresist layer on the entire surface of the antireflection layer, and forming a polysilicon layer on the top of the memory cell formed in the memory cell region Forming a photoresist pattern exposing the formed antireflection layer, exposing the gate polysilicon layer by removing the antireflection layer using the photoresist pattern as an etch mask, and removing the photoresist pattern; Oxidizing the gate polysilicon layer exposed on top of the memory cell On a step and a step of removing the anti-reflection layer that it remained in the memory cell region to form an oxide film mask.

According to the method of forming the memory-logic merged device according to the present invention, the oxide mask formed on the top of the memory cell is preferably the same thickness or thinner than the anti-reflection layer formed on the logic element portion, formed on the top of the memory cell The photoresist layer is preferably formed thinner than the photoresist layer in the logic element region.

According to the method of forming the memory-logic merger according to the present invention, the antireflection layer is preferably made of a SiN layer or a SiON layer.

According to the method of forming a memory-logic merged device according to the present invention, after removing the anti-reflection layer, forming a photoresist pattern on the logic element region to form a gate electrode on the logic element region and the photoresist pattern The method may further include forming a gate electrode on the logic element region by using.

In addition, the memory-logic merger according to the present invention in order to achieve the above technical problem, the active region while symmetrically separating the floating polysilicon film and the cell oxide film sequentially formed in the memory cell of the memory cell region on the semiconductor substrate A common source electrode in contact with the substrate, a gate polysilicon film formed on sidewalls of the floating polysilicon film and the cell oxide film, and having a thickness and a height, and an oxide mask that completely covers the common source electrode, the cell oxide film, and the gate polysilicon film. Equipped.

According to the memory-logic merging element according to the present invention, in the oxide mask, the thickness of the end portion of the oxide mask is preferably equal to or thicker than the thickness of the central portion of the oxide mask, and a predetermined distance between the logic element portions. A gate electrode may be further provided.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions have been emphasized for clarity, and when a layer is described as "on" another layer or substrate, the layer may exist in direct contact with another layer or substrate, or between There may be a third layer in the.

11 through 15 are cross-sectional views illustrating a memory-logic merger according to an embodiment of the present invention.

Referring to FIG. 11, a memory cell is formed using an F-poly film 24 sequentially formed in a memory cell region on a semiconductor substrate 20 including an active region and a cell oxide film 26 as an insulator. At this time, the F-poly film 24 and the cell oxide film 26 are separated left and right using the common source electrode 28 in common. Here, the memory cell part refers to a portion where a memory cell is formed in the memory-logic merged device. Next, the G-poly layer 22 is formed on the front surface of the memory cell portion and the logic element portion. Next, after the antireflection layer 30 is formed on the entire surface of the G-poly layer 22, the photoresist layer 32 is formed on the entire surface of the antireflection layer 30. Here, the antireflection layer 30 may be formed of an oxide film, a SiN layer or a SiON layer. In addition, the photoresist layer 32 formed on the top of the memory cell is preferably formed thinner than the photoresist layer 32 of the logic element region.

Referring to FIG. 12, a photoresist pattern (not shown) that exposes the anti-reflection layer 30 formed on the top of the memory cell is formed. Subsequently, the anti-reflective layer 30 is removed by using the photoresist pattern (not shown) as an etching mask to expose the G-poly layer 22. The photoresist pattern (not shown) is then removed using an ashing and strip process.

Referring to FIG. 13, an oxide mask 34 is formed by oxidizing the G-poly layer 22 exposed on the top of a memory cell. At this time, the thickness of the oxide mask 34 is determined in consideration of the etching selectivity with the gate. That is, the oxide mask 34 formed on the top of the memory cell is preferably the same thickness or thinner than the antireflection layer 30 of the logic element portion. In addition, in the oxide mask 34 formed on the G-poly film 38, the thickness of the end portion of the oxide mask 34 is formed to be the same as or thicker than that of the central portion.

Referring to FIG. 14, a photoresist pattern 36 is formed to remove the anti-reflection layer 30 remaining in the memory cell region. Subsequently, the anti-reflection layer 30 is removed using the photoresist pattern 36.

Referring to FIG. 15, after the anti-reflection layer 30 is removed, the photoresist pattern 36 is removed. Subsequently, a photoresist layer (not shown) is coated on the memory cell region and the logic element region, and a photoresist pattern 36 is formed on the logic element region to form a gate electrode. Next, the anti-reflection layer 30 is etched using the photoresist pattern 36 to form a pattern 30 ′ capable of forming a gate electrode. Further, using the pattern 30 ', the G-poly layer 22 is etched to a gate oxide film (not shown) on the semiconductor substrate 20 to form a gate electrode 22'.

Looking at the structure of the memory-logic merger according to an embodiment of the present invention, the common source electrode in contact with the active region while symmetrically separating the cell oxide film 26 formed sequentially in the memory cell of the memory cell region on the semiconductor substrate And (28). At the bottom of the cell oxide film 26, an F-poly film 24 is in contact with the semiconductor substrate 20. In general, a gate oxide film (not shown) exists between the semiconductor substrate 20 and the F-poly film 24. On the sidewall of the cell oxide film 26, a G-poly film 38 having the same thickness and height is formed symmetrically. An oxide film mask 34 is provided to completely cover the contact 28, the cell oxide film 26, and the G-poly film 38.

Further, the logic element portion further includes a gate electrode 22 'formed at a predetermined interval.

Although the present invention has been described in detail above, the present invention is not limited to the above embodiments, and many modifications and improvements can be made by those skilled in the art.

According to the above-described method of forming a memory-logic merger and merging thereof, an oxide mask is formed on an upper portion of a memory cell including a G-poly film using an oxidation process, whereby thickness and height are uniform and left and right. It is possible to form a G-poly film having symmetry and to form a memory-logic merger device in which the gate electrode is not impaired by not performing the CMP process.

Claims (8)

Forming a memory cell portion and a logic element portion on the semiconductor substrate; Forming a gate polysilicon layer on an entire surface of the memory cell region and the logic element region; Forming an anti-reflection layer on the entire surface of the gate polysilicon layer; Forming a photoresist layer on the entire surface of the anti-reflection layer; Forming a photoresist pattern exposing the anti-reflection layer formed on top of the memory cell formed at the memory cell region; Exposing the gate polysilicon layer by removing the anti-reflection layer using the photoresist pattern as an etch mask; Removing the photoresist pattern; Oxidizing the gate polysilicon layer exposed on top of the memory cell to form an oxide mask; And Removing the anti-reflective layer remaining in the memory cell region. The method of claim 1, And an oxide mask formed on top of the memory cell, the thickness of which is equal to or less than that of the anti-reflection layer formed on the logic element. The method of claim 1, And a photoresist layer formed on top of the memory cell to be thinner than the photoresist layer of the logic element region. The method of claim 1, And the anti-reflection layer is formed of a SiN layer or a SiON layer. The method of claim 1, After removing the antireflection layer, Forming a photoresist pattern on the logic element region to form a gate electrode on the logic element region; And And forming a gate electrode on the logic element region using the photoresist pattern. A contact in contact with the active region while symmetrically separating the floating polysilicon film and the cell oxide film sequentially formed in the memory cell of the memory cell region on the semiconductor substrate; A gate polysilicon film formed on sidewalls of the floating polysilicon film and the cell oxide film and having the same thickness and height; And an oxide mask that completely covers the contact, cell oxide, and gate polysilicon layers. The method of claim 6, In the oxide film mask, And a thickness of an end portion of the oxide mask is equal to or thicker than a thickness of a central portion of the oxide mask. The method of claim 6, And a gate electrode formed at a predetermined interval on the logic element portion.