KR20040004810A - Triple well in semiconductor device and method for forming the same - Google Patents

Abstract

PURPOSE: A triple well of a semiconductor device and a method for forming the same are provided to improve breakdown voltage between triple well and a P-well by forming a trench isolation layer between the triple well and the P-well. CONSTITUTION: A semiconductor substrate(102) is defined to a cell region including a triple P-well(108) and a triple N-well(106) and a peripheral region including a P-well(110). To isolate electrically between the triple N-well(106) of the cell region and the P-well(110) of the peripheral region, a trench isolation layer(104) is formed between the triple N-well(106) of the cell region and the P-well(110) of the peripheral region.

Description

Triple well in semiconductor device and method for forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triple well of a semiconductor device and a method of forming the same. In particular, a breakdown failure or leakage current due to breakdown between wells during an erase operation is increased by increasing the breakdown voltage of a NAND type flash memory device. The present invention relates to a triple well of a semiconductor device capable of preventing a phenomenon such as voltage drop and a method of forming the same.

In general, in the erase operation of a NAND type flash memory device, a well having a triple well structure is formed in a cell region because a relatively high bias voltage of about 20 V is applied to the well. do. In the case of forming a well of a triple well structure in a cell region, a P-well is formed in a ferry region to distinguish it from a peripheral region (hereinafter referred to as a “ferry region”). This P well acts as a ground during the erase operation. Therefore, triple N-wells in the cell region and P-wells in the ferry region must withstand a relatively high voltage bias voltage of at least 20V.

In general, it is reported that " Erase voltage drop and erase fail when the breakdown voltage (BV) between the triple N-well in the cell region and the P-well in the ferry region is less than 20V. (Erase fail), etc. "is reported. Therefore, the breakdown voltage between the triple N-well of the cell region and the P-well of the ferry region must be maintained at 20V or higher. For this, the amount of dose injected into the well (hereinafter referred to as 'dose amount') is determined. Should be lowered. In this case, however, as the dose of the well is decreased, the well resistance increases, which increases the well charging time, thereby lowering the device speed, and increasing the inter-well depletion region. As the margin on the layout (Layout) to give a lot of obstacles to the integration of the device.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and the breakdown failure or leakage current caused by breakdown between wells during an erase operation by increasing the breakdown voltage of the NAND type flash memory device is increased. The purpose of the present invention is to prevent phenomena such as voltage drop and to improve the erase characteristics of the flash memory device.

1 is a plan view illustrating a triple well of a semiconductor device according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of the triple well of the semiconductor device illustrated in FIG. 1 taken along the line 'A-A'.

3 to 5 are cross-sectional views illustrating a method of manufacturing a triple well of a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

102 semiconductor substrate 104 trench type isolation film

105: screen oxide film 106: triple N-well

108: triple P-well 110: P-well

In the present invention, it is divided into a triple P-well, a cell region in which a triple N-well is formed to surround the triple P-well, and a ferry region in which a P-well is formed, and the triple N-well of the cell region. In order to electrically isolate the P-wells of the ferry region from each other, a semiconductor substrate including a semiconductor substrate is formed between the triple N-well of the cell region and the P-well of the ferry region Provide triple wells.

In addition, in the present invention, forming a trench on a semiconductor substrate defined by a cell region and a ferri region, depositing an insulating film to fill the trench, and forming a trench type isolation layer, and opening the cell region. After forming a first photoresist pattern, performing an ion implantation process using the first photoresist pattern to form a triple N-well in the cell region bordering the trench-type isolation layer, the cell region After forming a portion of the triple N-well and the second photoresist pattern in which the ferry region is opened, an ion implantation process using the second photoresist pattern is performed to perform triple P in the triple N-well. -Forming a well, and forming a P-well in the ferry region at the boundary of the trench type isolation layer.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the same reference numerals refer to the same elements, and descriptions of overlapping elements will be omitted.

FIG. 1 is a plan view illustrating a triple well structure of a semiconductor device according to a preferred embodiment of the present invention, and FIG. 2 is a cutaway view of the triple well structure of the semiconductor device illustrated in FIG. 1 with 'A-A'. It is a cross section.

1 and 2, a triple well structure of a semiconductor device of the present invention includes a cell region including a triple P-well 108 and a triple N-well 106, and a P-well 110. The trench isolation device 104 is positioned between the ferry regions through a shallow trench isolation (STI) process.

Specifically, the triple well structure of the semiconductor device of the present invention defines the semiconductor substrate 102 as a cell region and a ferry region, wherein the triple P-well 108 and the triple P-well 108 are defined in the cell region. A triple N-well 106 is formed to surround and a P-well 110 is formed in the ferry region. In addition, a shallow trench isolation (STI) process is performed on the semiconductor substrate 102 in order to prevent a breakdown between the triple N-well 106 of the cell region and the P-well 110 of the ferry region. A trench type device isolation film 104 is formed therethrough.

In the above, the depth D of the trench type isolation layer 104 is to isolate the triple N-well 106 of the cell region and the P-well 110 of the ferry region from each other. It is desirable to form deeper than the depth of 106). In addition, the width W of the trench type isolation layer 104 is generally defined between the triple N-well 106 of the cell region and the P-well 110 of the ferry region when a bias voltage is applied during an erase operation. It is desirable to form larger than the width of the deprived area.

Hereinafter, a method of forming the triple well structure of the semiconductor device of the present invention described above will be described. In addition, the trench-type device isolation film forming process through the STI process applied in the present invention may be performed before or after the well formation, but before the well formation for convenience of description.

3 to 5 are cross-sectional views illustrating an example of a method of forming a triple well structure of a semiconductor device of the present invention.

Referring to FIG. 3, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 102 defined as a cell region and a ferry region. In this case, the pad oxide film is formed by performing an oxidation process by a dry or wet oxidation method for crystal defects or surface treatment of the upper surface of the semiconductor substrate 102. In addition, the pad nitride film is formed as high as possible by performing a deposition process using a low pressure chemical vapor deposition (LPCVD) method in order to increase the height of the trench type device isolation film 104 formed through a subsequent process to the maximum.

Subsequently, after the photoresist (not shown) is coated on the entire structure, an exposure process and a development process using a photomask are sequentially performed to have a profile of a subsequent trench type device isolation film 104. A photoresist pattern (not shown) is formed. Then, an etching process using the photoresist pattern as an etching mask is performed to form a trench (not shown) by etching a part of the pad nitride layer, the pad oxide layer, and the semiconductor substrate 102. At this time, the internal inclined surface of the trench is preferably formed in 65 to 85 ° in consideration of the subsequent process.

Subsequently, a high density plasma (HDP) oxide film is deposited on the entire structure by a gap fill method to prevent voids from occurring in the trench, and then a chemical mechanical polishing (CMP) process is performed. The trenches are buried, and the etching process and the cleaning process are performed to remove the pad nitride film and the pad oxide film to form the trench type isolation film 104. On the other hand, before forming the trench type isolation layer 104, the Wall SACrificial (SAC) oxidation process, the monthly oxidation process and the rounding treatment process on the inner surface of the trench may be performed by dry oxidation method or wet oxidation method. You can also carry out.

Subsequently, in order to perform a subsequent well ion implantation process, a VT screen oxide 105 is formed on a portion where the pad oxide film is removed by using a dry oxidation method or a wet oxidation method. The screen oxide film 105 may be formed using USG (Undoped Silicate Glass) or PSG (Phosphorous Silicate Glass).

Referring to FIG. 4, after the photoresist (not shown) is coated on the entire structure, an exposure process and a development process using a photo mask are sequentially performed to form the photoresist pattern PR1 to open the cell region. do. Next, an N-well ion implantation process using the photoresist pattern PR1 as an ion implantation mask is performed to form triple N-wells 106 in the cell region. Then, the photoresist pattern PR1 is removed by performing a strip process.

Referring to FIG. 5, after the photoresist (not shown) is coated on the entire structure, an exposure process and a development process using a photo mask are sequentially performed to form a region of the triple P-well 108 in the cell region; The photoresist pattern PR2 is formed to open the ferry region. Then, a P-well ion implantation process using the photoresist pattern PR2 as an ion implantation mask is performed to form a triple P-well 108 in the triple N-well 106 of the cell region, and the ferry region. Form a P-well 110. Then, the photoresist pattern PR2 is removed by performing a strip process.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In particular, as described above, the process of forming the trench may be applied after the well process, and the process of forming the trench type isolation layer by filling the trench may also be applied after the well process. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the present invention, a trench type isolation layer is formed between the triple N-well of the cell region and the P-well of the ferry region, and is isolated independently from each other, so that the triple N-well of the cell region and the P of the ferry region are isolated. The breakdown phenomenon can be prevented in this area by increasing the breakdown voltage between the wells.

In addition, the present invention prevents a breakdown phenomenon between a triple N-well in a cell region and a P-well in a ferry region, thereby preventing a phenomenon such as an erase fail due to breakdown between the wells or a voltage drop due to a leakage current during the erase operation. As a result, erase characteristics of the flash memory device may be improved.

Claims (6)

It is divided into a triple P-well, a cell region in which triple N-wells are formed to surround the triple P-well, and a ferry region in which P-wells are formed. To electrically isolate the triple N-well of the cell region and the P-well of the ferry region from each other, And a semiconductor substrate in which a trench type isolation layer is formed between the triple N-well of the cell region and the P-well of the ferry region. The method of claim 1, The depth of the trench type isolation layer is formed to be deeper than the triple N-well of the cell region. The method of claim 1, The width of the trench isolation layer is greater than the width of the depletion region between the triple N-well of the cell region and the P-well of the ferry region, which occurs when a bias voltage is applied during an erase operation of the semiconductor device. Triple well of a semiconductor device, characterized in that formed large. (a) forming a trench on a semiconductor substrate defined by a cell region and a ferry region; (b) depositing an insulating film to fill the trench to form a trench type isolation layer; (c) forming a first photoresist pattern in which the cell region is opened, and then performing an ion implantation process using the first photoresist pattern to triple N-well in the cell region bordering the trench type isolation layer; Forming a; And (d) forming a second photoresist pattern in which the ferrite region is open and a portion of the triple N-well in the cell region, and then performing an ion implantation process using the second photoresist pattern to perform the triplet Forming a triple P-well in an N-well, and forming a P-well in the ferry region at the boundary of the trench type isolation layer. The method of claim 4, wherein The depth of the trench type isolation layer is formed to be deeper than the triple N-well of the cell region. The method of claim 4, wherein The width of the trench type isolation layer is greater than a width of a deficiency region between the triple N-well of the cell region and the P-well of the ferry region, which occurs when a bias voltage is applied during an erase operation of the semiconductor device. The triple well forming method of a semiconductor device, characterized in that formed large.