KR20040003237A - Transistor in a semiconductor device and a method of manufacturing the same - Google Patents

Abstract

PURPOSE: A transistor of a semiconductor device and a method for manufacturing the same are provided to restrain hot carrier effect and to prevent attack of boron into a channel region by using a dual gate oxide layer including an oxynitride layer and an oxide layer. CONSTITUTION: Nitrogen is implanted into a semiconductor substrate(200). An oxide layer(205) is formed on the substrate while forming an oxynitride layer(206) at the lower portion of the oxide layer using implanted nitrogen. By annealing, the oxynitride layer(206) is grown and the thickness of the oxide layer(205) is thin. After forming a polysilicon layer, a gate electrode(208b) and a dual gate oxide layer(256) including the oxynitride layer and the oxide layer are formed by patterning the polysilicon layer, the oxide layer and the oxynitride layer.

Description

Transistor in a semiconductor device and a method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device capable of improving the hot carrier effect and the leakage current characteristics in the gate insulating film.

In general, a transistor of a semiconductor device includes a gate electrode and a source / drain formed on a semiconductor substrate at both edges of the gate electrode, and a gate oxide film is formed between the gate electrode and the semiconductor substrate.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the prior art.

Referring to FIG. 1A, an nMOS region is formed by an ion implantation process after forming an isolation layer 102 in an isolation region of a semiconductor substrate 101 in which an nMOS region in which an nMOS transistor is to be formed and a pMOS region in which a pMOS transistor is to be formed are defined, respectively. P wells 103a are formed in the semiconductor substrate 101, and n wells 103b are formed in the semiconductor substrate 101 in the pMOS region.

Referring to FIG. 1B, the gate oxide film 104 and the polysilicon layer 105 are sequentially formed on the entire structure including the nMOS region and the pMOS region.

Referring to FIG. 1C, the gate oxide film 104 and the polysilicon layer 105 in FIG. 1B are patterned through a patterning process to form the gate oxide film 104 and the gate electrodes 106a and 106b in the nMOS region and the pMOS region, respectively. ).

Thereafter, in order to form the source / drain of the LDD structure, a low concentration impurity region 107a and a low concentration ion implantation process are applied to the semiconductor substrate 101 at both edges of the gate electrodes 106a and 106b formed in a predetermined pattern in the nMOS region and the pMOS region. 107b), respectively. Here, n-type impurities are implanted into the nMOS region to form a low concentration impurity region 107a, and p-type impurities are implanted into the pMOS region to form a low concentration impurity region 107b.

Referring to FIG. 1D, the first insulating film 108 and the second insulating film 109 for sequentially forming the insulating film spacers on both side surfaces of the gate electrodes 106a and 106b are sequentially formed on the entire top. Subsequently, the first and second insulating layers 108 and 109 are left only on both sides of the gate electrodes 106a and 106b by the entire surface etching process, thereby forming the insulating layer spacer 110 including the first and second insulating layers 108 and 109. Form.

The first insulating layer 108 is formed of low pressure silicon oxide (LP-TEOS), and the second insulating layer 109 is formed of silicon nitride (Si ₃ N ₄ ). In this case, the first insulating film 108 serves as a buffer oxide film that prevents stress from occurring when the gate electrodes 106a and 106b made of the polysilicon layer and the second insulating film 109 made of silicon nitride directly contact each other. .

Thereafter, the high concentration impurity regions 111a and 111b are formed by the high concentration ion implantation process into the semiconductor substrate 101 at the edge of the insulating film spacer 110 formed on both sides of the gate electrodes 106a and 106b to form the source / drain. It is formed deeper than 107a and 107b. Here, n-type impurities are implanted into the nMOS region to form a high concentration impurity region 11a, and p-type impurities are implanted into the pMOS region to form a high concentration impurity region 111b. Thus, the source / drain 112a and 112b of the LDD structure including the low concentration impurity regions 107a and 107b and the high concentration impurity regions 111a and 111b are formed in the nMOS region and the pMOS region, respectively.

Referring to FIG. 1E, silicide layers 113 are formed on the top surfaces of the gate electrodes 106a and 106b and the source / drain 112a and 112b. In this way, a general transistor is manufactured.

In the transistor manufactured by the above method, the thickness of the gate oxide film should be reduced in order to increase the integration density and lower the operating voltage. However, when the thickness of the gate oxide film becomes thinner than 30 kV, direct tunneling of electrons occurs through the gate oxide film. There is a problem that the leakage current increases.

In addition, boron implanted into the pMOS region in order to impart conductivity to the gate electrode made of a polysilicon layer while forming a low concentration impurity region and a high concentration impurity region passes through the gate oxide film in a subsequent heat treatment process to form a semiconductor substrate under the gate electrode as a channel region. Diffuses to the surface. When boron is diffused to the channel region, the threshold voltage of the transistor is changed, thereby reducing the reliability of the device.

Therefore, it is difficult to carry out the subsequent heat treatment at a high temperature, and subsequent heat treatment at a low temperature lowers the junction depth and increases leakage current, and it is impossible to sufficiently activate impurities injected into the gate electrode. An impurity concentration may be reduced to generate an insulation region. As a result, an unwanted electrical gate oxide film thickness is increased, resulting in a problem of higher threshold voltage.

On the other hand, in the case of nMOS transistors, electrons / holes moving from the source to the drain obtain a higher energy than the energy barrier between the semiconductor substrate and the gate oxide layer by a high electric field applied to the gate rather than the kinetic energy obtained by the ambient temperature. The threshold voltage may decrease due to the hot carrier effect introduced into the oxide layer.

Therefore, in order to solve the above problems, the present invention injects nitrogen into the surface of a semiconductor substrate, forms an oxide film, forms a lower portion of the oxide film as a nitride oxide film, and then grows the nitride oxide film by heat treatment to form a gate oxide film as a nitride oxide film and an oxide film. By forming a stacked structure, a method of manufacturing a transistor of a semiconductor device capable of improving resistance to hot carrier effects and preventing boron injected into a gate electrode from penetrating a channel region can improve process reliability and device electrical characteristics. The purpose is to provide.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views of devices for explaining a method of manufacturing a transistor of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 200: semiconductor substrate 102, 201: device isolation film

103a, 202a: p well 103b, 202a: n well

203: sacrificial oxide film 204: nitrogen

205: oxide film 206: nitride oxide film

104, 256: gate oxide film 105, 207: polysilicon layer

106a, 106b, 208a, 208b: gate electrode

107a, 107b, 209a, 209b: low concentration impurity regions

108, 210: buffer oxide film 109, 211: nitride film

110, 212: insulating film spacer

111a, 111b, 213a, and 213b: high concentration impurity regions

112a, 112b, 214a, 214b: source / drain

113,215: silicide layer

A transistor of a semiconductor device according to the present invention is formed between a gate electrode formed in a predetermined pattern on a semiconductor substrate, a source / drain formed on a semiconductor substrate at both edges of the gate electrode, and formed between the gate electrode and the semiconductor substrate, and a nitride oxide film and an oxide film. It characterized in that it comprises a gate oxide film made of a laminated structure of.

In the above, the nitride oxide film has a thickness of 10 to 35 kPa.

In the method of manufacturing a transistor of a semiconductor device according to the present invention, nitrogen is injected into a surface of a semiconductor substrate in an element formation region, and an oxide film is formed on an upper portion of the semiconductor substrate, and the lower portion of the oxide film is formed using nitrogen injected into the surface of the semiconductor substrate. Forming a nitride oxide film, lowering the thickness of the oxide film remaining while the nitride oxide film is grown by a heat treatment process, forming a polysilicon layer on the oxide film, and etching the polysilicon layer, the oxide film, and the nitride oxide film by an etching process. Patterning to form a gate electrode made of a polysilicon layer, a gate oxide film made of a laminated structure of an oxide film of nitride and an oxide film, and forming a source / drain on the semiconductor substrate at both edges of the gate electrode; .

In the above description, the method may further include forming a sacrificial oxide film on the semiconductor substrate before injecting nitrogen, wherein the sacrificial oxide film is removed before forming the oxide film.

After that, the nitrogen is characterized in that the injection of energy of 5 to 30keV, the injection amount of nitrogen is 7E13 to 1E15ions / cm ² It is characterized by that.

On the other hand, it is characterized in that it further comprises the step of performing a rapid heat treatment after the injection of nitrogen, before forming the oxide film. At this time, the rapid heat treatment is characterized in that carried out for 10 to 30 seconds at a temperature of 900 to 1050 ℃ in a nitrogen gas atmosphere.

The oxide film is formed to a thickness of 5 to 30 kPa, and characterized in that formed by supplying O ₂ gas or NO gas at a temperature of 500 to 900 ℃.

Heat treatment is carried out in a nitrogen oxide atmosphere at a temperature of 750 to 950 ℃ for 15 to 45 minutes, characterized in that the nitride oxide film is grown to 10 to 35 kPa.

The etching process may be performed by a dry etching method using an etching gas containing HBr gas.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the present invention.

Referring to FIG. 2A, an nMOS region is formed by forming an isolation layer 201 in an isolation region of a semiconductor substrate 200 in which an nMOS region in which an nMOS transistor is to be formed and a pMOS region in which a pMOS transistor is to be formed are defined. P wells 202a are formed in the semiconductor substrate 200 of the semiconductor substrate 200, and n wells 202b are formed in the semiconductor substrate 200 of the pMOS region. Thereafter, heat treatment is performed to activate the implanted impurities.

Referring to FIG. 2B, the sacrificial oxide film 203 is formed on the entire structure including the nMOS region and the pMOS region after removing a natural oxide film (not shown) formed on the surface of the semiconductor substrate 200 by a cleaning process. Thereafter, nitrogen 204 is injected into the surface of the semiconductor substrate 200 by an ion implantation process, and rapid heat treatment for activation is performed.

In the above, the cleaning process for removing the natural oxide film is a first cleaning process using a mixed solution of NH ₄ OH, H ₂ O ₂ and H ₂ O in a ratio of about 1: 1: 5 and a second using a hydrofluoric acid solution Proceed to the cleaning process. Thereafter, the sacrificial oxide film 204 is formed to a thickness of 30 to 60 kPa.

Meanwhile, the amount of nitrogen 204 injected in the ion implantation process is 7E13 to 1E15ions / cm ² It is injected to the surface of the semiconductor substrate 200 with an energy of 5 to 30 keV. The rapid heat treatment performed thereafter is performed at a temperature of 900 to 1050 ° C. for 10 to 30 seconds in a nitrogen gas atmosphere.

Referring to FIG. 2C, after the sacrificial oxide film 204 of FIG. 2B is removed, the oxide film 205 is formed on the surface of the semiconductor substrate into which nitrogen (204 of FIG. 2B) is injected. At this time, the oxide film 205 is formed to a thickness of 5 ~ 30Å, the nitrogen (204 in Fig. 2b) injected into the surface of the semiconductor substrate 200 while the oxide film 205 is formed is introduced into the oxide film 205, the oxide film A lower portion of 205 is formed of the first nitride oxide film 206.

In the above, the cleaning process for removing the sacrificial oxide film (204 in Fig. 2b) is a first cleaning process using a mixed solution of NH ₄ OH, H ₂ O ₂ and H ₂ O mixed in a ratio of about 1: 1: 5 and Proceed to the secondary cleaning process with hydrofluoric acid solution.

On the other hand, the oxide film 205 is formed to a thickness of 5 to 30 kPa by supplying O ₂ gas or NO gas at a temperature of 500 to 900 ℃.

Referring to FIG. 2D, heat treatment is performed to grow the nitride oxide film 206 to increase its thickness. The thickness of the oxide film 205 remaining as the nitride oxide film 206 is grown becomes thin.

In the above, heat treatment for growing the nitride oxide film 206 to increase its thickness is performed for 15 to 45 minutes in a nitrogen oxide (NO gas) atmosphere at a temperature of 750 to 950 ° C. As a result, the nitride oxide film 206 grows to a thickness of 10 to 35 kPa. At this time, since the atomic spacing of the nitride oxide film 206 is wider than the atomic spacing of the oxide film 205, the nitride oxide film 206 can be grown to a thickness of 10 to 35 GPa even when the oxide film 205 is formed to a thickness of 5 to 30 GPa. In this case, the oxide film 205 remains on the nitride oxide film 206 by a predetermined thickness.

Referring to FIG. 2E, a polysilicon layer 207 is formed over the entire structure including the nMOS region and the pMOS region.

Referring to FIG. 2F, the polysilicon layer (207 of FIG. 2E), the oxide film 205, and the nitride oxide film 206 are patterned through a patterning process using a gate mask, and the oxide film 205 and the nitride oxide film 206 are stacked. A gate oxide film 256 having a structured structure and gate electrodes 208a and 208b made of a polysilicon layer (207 in Fig. 2E) are formed in the nMOS region and the pMOS region, respectively.

At this time, the polysilicon layer (207 in FIG. 2E) is patterned to form gate electrodes 208a and 208b by a dry etching method using an etching gas containing HBr gas, and oxygen is formed after the gate electrodes 208a and 208b are formed. The heat treatment process is performed in an atmosphere to remove plasma damage and the like generated during the patterning process.

Thereafter, in order to form the source / drain of the LDD structure, a low concentration impurity region 209a and a low concentration ion implantation process are applied to the semiconductor substrate 200 at both edges of the gate electrodes 208a and 208b formed in a predetermined pattern in the nMOS region and the pMOS region. 209b) are formed respectively. Here, a low concentration impurity region 209a is formed by injecting n-type impurities into the nMOS region, and a low concentration impurity region 209b is formed by implanting p-type impurities into the pMOS region.

Referring to FIG. 2G, the first insulating film 210 and the second insulating film 211 for sequentially forming the insulating film spacers on both side surfaces of the gate electrodes 208a and 208b are sequentially formed on the entire top. Subsequently, the first and second insulating layers 210 and 211 are left only at both sides of the gate electrodes 208a and 208b by the entire surface etching process, thereby forming the insulating layer spacer 212 including the first and second insulating layers 210 and 211. Form.

In the above description, the first insulating layer 210 is formed of low pressure silicon oxide (LP-TEOS), and the second insulating layer 211 is formed of silicon nitride (Si ₃ N ₄ ). In this case, the first insulating film 210 serves as a buffer oxide film that prevents stress from occurring when the gate electrodes 208a and 208b made of the polysilicon layer and the second insulating film 211 made of silicon nitride directly contact each other. .

Thereafter, the high concentration impurity regions 213a and 213b are formed by the high concentration ion implantation process into the semiconductor substrate 200 at the edge of the insulating film spacer 212 formed on both sides of the gate electrodes 208a and 208b to form the source / drain. It is formed deeper than 209a and 209b. Here, n-type impurities are implanted into the nMOS region to form a high concentration impurity region 213a, and p-type impurities are implanted into the pMOS region to form a high concentration impurity region 213b, respectively. As a result, the source / drain 214a and 214b of the LDD structure including the low concentration impurity regions 209a and 209b and the high concentration impurity regions 213a and 213b are formed in the nMOS region and the pMOS region, respectively.

On the other hand, in order to lower the contact resistance of the gate electrodes 208a and 208b and the source / drains 214a and 214b and the contact plug to be formed in a subsequent process, the upper portions of the gate electrodes 208a and 208b and the source / drain 214a and 214b. The silicide layer 215 is formed on the surface.

A method of forming the silicide layer 215 is described below. First, the remaining oxide films on the surfaces of the gate electrodes 208a and 208b and the source / drain 214a and 214b are removed, and a metal layer (not shown) and a capping layer (not shown) are sequentially formed on the entire top, and then the primary The silicide layer 215 is formed by reacting the silicon component of the gate electrodes 208a and 208b and the source / drain 214a and 214b with the metal component of the metal layer by a heat treatment process. Thereafter, after removing the capping layer and the unreacted metal layer, a second heat treatment process is performed to improve the quality of the silicide layer 215.

As described above, the present invention can obtain the following effects by forming the gate oxide film in a laminated structure of a nitride oxide film and an oxide film.

First, since the dielectric constant of the gate oxide film can be increased, the thickness of the electrical gate oxide film can be reduced, thereby increasing the physical thickness of the gate insulating film, thereby reducing the leakage current through the gate oxide film. .

Second, by increasing the hot carrier immunity characteristics of the nMOS transistor to prevent the change of the threshold voltage of the device can improve the reliability of the device.

Third, it is possible to prevent boron from penetrating into the channel region in the pMOS transistor, thereby reducing the threshold voltage, thereby improving the reliability of the device.

Fourth, since the gate oxide film is formed in a stacked structure of nitride oxide film and silicon nitride film, the thermal burden on subsequent thermal processes can be reduced to secure a process margin. Therefore, the subsequent thermal process is performed at a high temperature to be injected into the gate electrode or the source / drain. By activating the impurities sufficiently, it is possible to prevent the thickness of the gate oxide film from increasing due to the activated ion decrease.

Fifth, damage to the surface of the substrate is conventionally generated in the process of patterning the polysilicon layer by the dry etching method using halogens, but in the present invention, the polysilicon layer is patterned by the dry etching method using HBr in the state of leaving the nitride oxide film. As a result, the plasma damage generated on the substrate can be minimized to improve the reliability of the device.

Claims (12)

Injecting nitrogen into the surface of the semiconductor substrate in the device formation region; Forming a lower portion of the oxide layer as a nitride oxide layer using the nitrogen injected into the surface of the semiconductor substrate while forming an oxide layer on the semiconductor substrate; Lowering the thickness of the oxide film remaining while growing the nitride oxide film by a heat treatment process; Forming a polysilicon layer on the oxide film; Patterning the polysilicon layer, the oxide film, and the nitride oxide film by an etching process to form a gate electrode formed of the polysilicon layer, and a gate oxide film having a stacked structure of the nitride oxide film and the oxide film; And Forming a source / drain on the semiconductor substrate at both edges of the gate electrode. The method of claim 1, Forming a sacrificial oxide film on the semiconductor substrate prior to implanting the nitrogen, wherein the sacrificial oxide film is removed before forming the oxide film. The method of claim 1, The nitrogen is a transistor manufacturing method of a semiconductor device, characterized in that the injection of energy of 5 to 30keV. The method of claim 2 or 3, The injection amount of the nitrogen is 7E13 to 1E15ions / cm ² The transistor manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 1, wherein after injecting the nitrogen and before forming the oxide film, The method of manufacturing a transistor of a semiconductor device, further comprising the step of performing a rapid heat treatment. The method of claim 5, wherein The rapid heat treatment is a transistor manufacturing method of a semiconductor device, characterized in that performed for 10 to 30 seconds at a temperature of 900 to 1050 ℃ in a nitrogen gas atmosphere. The method of claim 1, The oxide film is a transistor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 5 to 30Å. The method according to claim 1 or 7, The oxide film is a transistor manufacturing method of a semiconductor device, characterized in that formed by supplying O ₂ gas or NO gas at a temperature of 500 to 900 ℃. The method of claim 1, The heat treatment is carried out in a nitrogen oxide atmosphere at a temperature of 750 to 950 ℃ for 15 to 45 minutes, the method of manufacturing a transistor of a semiconductor device, characterized in that to grow the nitride oxide film to 10 to 35 kHz. The method of claim 1, The etching process is a transistor manufacturing method of a semiconductor device, characterized in that performed by a dry etching method using an etching gas containing HBr gas. A gate electrode formed in a predetermined pattern on the semiconductor substrate; Source / drain formed on the semiconductor substrate at both edges of the gate electrode; And And a gate oxide film formed between the gate electrode and the semiconductor substrate, the gate oxide film having a stacked structure of a nitride oxide film and an oxide film. The method of claim 11, The thickness of the nitride oxide film is a transistor of the semiconductor element, characterized in that 10 to 35 kHz.