KR20040002238A - Method for manufacturing a transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor is provided to improve the characteristic, yield and reliability of the transistor by preventing a gate oxide layer and a semiconductor substrate from being damaged in a process for a metal gate electrode pattern and by avoiding stress applied to the substrate in a subsequent heat treatment process. CONSTITUTION: The gate oxide layer(33), a polycrystalline silicon layer(35), a metal layer(37) and a hard mask layer(39) are sequentially formed on the substrate(31) of the first conductivity type. The hard mask layer and the metal layer are etched. The upper portion of the polycrystalline silicon layer is etched to form a pattern structure. A nitride layer spacer(41) is formed on the sidewall of the pattern structure. The exposed polycrystalline silicon layer and the polycrystalline silicon layer under the nitride layer spacer are etched while the metal gate electrode is formed. An oxide layer is grown on the exposed polycrystalline silicon layer and the gate oxide layer of the metal gate electrode through a re-oxidation process. The oxide layer and the gate oxide layer are etched. Low density impurity ions of the second conductivity type are implanted into the front surface of the resultant structure by using the metal gate electrode as a mask. An oxide layer spacer is formed on the sidewall of the metal gate electrode including the nitride layer spacer. A source/drain region of a lightly-doped-drain(LDD) structure is formed in the substrate at both sides of the metal gate electrode including the oxide layer spacer.

Description

Method for manufacturing a transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and in particular, during a metal gate electrode pattern process, an upper portion of a polycrystalline silicon layer, which is a lower component of the metal gate electrode, is etched, and a nitride spacer is formed on a sidewall of the pattern structure. After forming a, and the etching of the polycrystalline silicon layer under the nitride film spacer by a wet etching process, and then proceeds to the reoxidation process relates to a transistor manufacturing method for improving the characteristics, yield and reliability of the device.

Currently, a polycrystalline silicon layer is mainly used as a gate electrode material of a MOS transistor in a semiconductor chip, but the use of a metal gate electrode using a metal layer as a gate electrode material is increasing due to high integration and high speed.

1A to 1C are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

Referring to FIG. 1A, a gate oxide film 13 is grown on a semiconductor substrate 11 by a thermal oxidation process.

The polycrystalline silicon layer 15, the tungsten (W) layer 17, and the hard mask layer 19 of the nitride layer are sequentially formed on the gate oxide layer 13.

Referring to FIG. 1B, a photoresist film is coated on the hard mask layer 19, and the photoresist film is selectively exposed and developed so as to remain only at a portion where a gate electrode is to be formed.

The hard mask layer 19 is etched using the selectively exposed and developed photoresist film, and the tungsten layer 17 and the polycrystalline silicon layer 15 are etched to form a metal gate electrode, and then the gate After the oxide film 13 is etched, the photosensitive film is removed.

Subsequently, an oxide film 21 is grown on the side surface of the polycrystalline silicon layer 15 and the semiconductor substrate 11 by a reoxidation process. At this time, the re-oxidation process is performed to improve the characteristics and reliability of the transistor. By adjusting the partial pressure of H ₂ O and H ₂ , the tungsten layer 17 is not oxidized, but only the polycrystalline silicon layer 15 is oxidized. It is a process to make it.

Referring to FIG. 1C, the oxide layer 21 is etched using the metal gate electrode as a mask, and low concentration n-type impurity ions are implanted into the entire surface.

A nitride film and an oxide film are sequentially formed on the entire surface including the metal gate electrode, and then etched back to form a spacer 23 having a nitride film and an oxide film stacked structure on sidewalls of the metal gate electrode.

Subsequently, a high concentration of n-type impurity ions are implanted using the metal gate electrode and the spacer 23 as a mask, and drive-in diffusion is used to lightly doped the surface of the semiconductor substrate 11 on both sides of the metal gate electrode. A source / drain region 25 having a drain structure is formed.

However, the conventional method of manufacturing a transistor has the following problems because a reoxidation process is performed in a transistor having a metal gate electrode in a state where the metal layer of the metal gate electrode is exposed.

First, a reoxidation process in which the metal layer is not oxidized is required, so that a high temperature process or a process time is lengthened, and thus there is a limit in the thickness of an oxide film grown.

Second, during the high temperature reoxidation process, the metal layer, which is a constituent of the metal gate electrode, and the polycrystalline silicon layer react to change device characteristics.

Third, the nitride film protecting the metal layer of the metal gate electrode is brought into contact with the semiconductor substrate, and stress is applied to the semiconductor substrate in a subsequent thermal process due to a difference in thermal expansion coefficient between the two layers, thereby degrading the characteristics of the transistor. In the DRAM, the refresh characteristic is degraded.

The present invention has been made to solve the above problems, and during the metal gate electrode pattern process, the upper portion of the polycrystalline silicon layer, which is a lower component of the metal gate electrode, is etched, and a nitride spacer is formed on the sidewall of the pattern structure. By etching the polycrystalline silicon layer under the nitride spacer by a wet etching process, and then reoxidation process, the reoxidation process is easy, and to prevent damage to the gate oxide film and the semiconductor substrate generated during the metal gate electrode pattern process It is an object of the present invention to provide a method for manufacturing a transistor.

1A to 1C are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11,31 semiconductor substrate 13,33 gate oxide film

15,35 polycrystalline silicon layer 17,37 tungsten layer

19,39: hard mask layer 21,43: oxide film

23 spacer 25,47 source / drain region

41 nitride film spacer 45 oxide film spacer

The present invention for achieving the above object,

Sequentially forming a gate oxide film, a polycrystalline silicon layer, a metal layer, and a hard mask layer on the first conductivity type semiconductor substrate;

Etching the hard mask layer and the metal layer by a photolithography process using a mask for a gate electrode, and forming a pattern structure by etching the upper portion of the polycrystalline silicon layer;

Forming a nitride film spacer on sidewalls of the pattern structure;

Etching the exposed polycrystalline silicon layer and the polycrystalline silicon layer under the nitride film spacer, and forming a metal gate electrode by the etching process;

Growing an oxide film on the exposed polycrystalline silicon layer and the gate oxide film of the metal gate electrode by a re-oxidation process;

Etching the oxide layer and the gate oxide layer using the hard mask layer and the nitride spacer as a mask;

Implanting low concentration of the second conductivity type impurity ions onto the metal gate electrode as a mask;

Forming an oxide spacer on sidewalls of the metal gate electrode including the nitride spacer;

And forming a source / drain region of an LDD structure in a semiconductor substrate on both sides of the metal gate electrode including the oxide spacer.

According to the present invention, a polycrystalline silicon layer, which is a lower component of the metal gate electrode, is etched only at an upper portion thereof, a nitride layer spacer is formed on sidewalls of the pattern structure, and a wet etching process is performed on the lower portion of the nitride layer spacer. The polycrystalline silicon layer of the invention is etched, followed by a reoxidation process.

As described above, the metal gate electrode pattern process may be performed by etching the upper portion of the polycrystalline silicon layer, which is a lower component of the metal gate electrode, and wet etching the remaining polycrystalline silicon layer in a subsequent process. This is to prevent damage to the gate oxide film and the semiconductor substrate generated at the time.

In addition, since the metal layer of the metal gate electrode is protected from oxidation by the nitride film spacer during the reoxidation process, the reoxidation process is facilitated.

Since the nitride layer protecting the metal layer of the metal gate electrode does not contact the semiconductor substrate, the two layers contact each other to prevent stress on the semiconductor substrate generated in a subsequent thermal process, thereby degrading transistor characteristics and refreshing characteristics in DRAM. This is to prevent degradation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

Referring to FIG. 2A, the gate oxide film 33 is grown on the semiconductor substrate 31 by a thermal oxidation process.

The polycrystalline silicon layer 35, the tungsten layer 37, and the hard mask layer 39 are sequentially formed on the gate oxide layer 33.

Referring to FIG. 2B, a photosensitive film (not shown) is coated on the hard mask layer 39.

After selectively exposing and developing the photoresist film so as to remain only at a portion where a gate electrode is to be formed, the hard mask layer 39 is etched using the selectively exposed and developed photoresist mask, and the tungsten layer 37 is removed. After etching, the upper portion of the polycrystalline silicon layer 35 is etched, and then the photosensitive film is removed.

Referring to FIG. 2C, a nitride film is formed on the entire surface including the hard mask layer 39 and etched back to form upper portions of the etched hard mask layer 39, tungsten layer 37, and polycrystalline silicon layer 35. The nitride film spacer 41 is formed on the sidewalls of the pattern structure.

Referring to FIG. 2D, the polycrystalline silicon layer 35 is wet etched. In this case, the polycrystalline silicon layer 35 under the nitride film spacer 41 is etched by the wet etching process.

Here, the polycrystalline silicon layer 35 is etched using the hard mask layer 39 and the nitride film spacer 41 as a mask, followed by a wet etching process of the polycrystalline silicon layer 35 to perform the wet etching process. The polycrystalline silicon layer 35 at the bottom may be etched.

Referring to FIG. 2E, an oxide film 43 is grown on the exposed polycrystalline silicon layer 35 and the gate oxide film 33 by a reoxidation process.

The oxide layer 43 and the gate oxide layer 33 are etched using the hard mask layer 39 and the nitride layer spacer 41 as a mask.

Referring to FIG. 2F, low concentration n-type impurity ions are ion-implanted to the entire surface using the metal gate electrode as a mask.

An oxide film is formed on the entire surface including the nitride spacer 41 and etched back to form an oxide spacer 45 on the sidewall of the metal gate electrode including the nitride spacer 41.

Subsequently, a high concentration of n-type impurity ions are implanted using the metal gate electrode, the nitride film spacer 41, and the oxide film spacer 45 as a mask, and then drive-in diffusion to form an LDD structure in the surface of the semiconductor substrate 31 on both sides of the metal gate electrode. Source / drain regions 47 are formed.

In the method of manufacturing a transistor of the present invention, a polycrystalline silicon layer, which is a lower component of the metal gate electrode, is etched only at an upper portion thereof, a nitride spacer is formed on sidewalls of the pattern structure, and the wet etching process is performed. By etching the polycrystalline silicon layer under the nitride film spacer and then performing a re-oxidation process, there is an effect of improving the characteristics, yield and reliability of the device for the following reasons.

First, in the metal gate electrode pattern process, the polycrystalline silicon layer, which is a lower component of the metal gate electrode, is etched only at an upper portion thereof, and the remaining polycrystalline silicon layer is wet etched in a subsequent process, which occurs during the metal gate electrode pattern process. To prevent damage to the gate oxide film and the semiconductor substrate.

Second, since the metal layer of the metal gate electrode is protected from oxidation by the nitride film spacer, there is no restriction on the process and thus the reoxidation process is easy.

Third, the nitride film protecting the metal layer of the metal gate electrode does not come into contact with the semiconductor substrate so that the two layers contact each other to prevent the stress applied to the semiconductor substrate generated in a subsequent thermal process, thereby deteriorating the characteristics of the transistor and in the DRAM. Prevents deterioration of refresh characteristics.

Claims (1)

Sequentially forming a gate oxide film, a polycrystalline silicon layer, a metal layer, and a hard mask layer on the first conductivity type semiconductor substrate; Etching the hard mask layer and the metal layer by a photolithography process using a mask for a gate electrode, and forming a pattern structure by etching the upper portion of the polycrystalline silicon layer; Forming a nitride film spacer on sidewalls of the pattern structure; Etching the exposed polycrystalline silicon layer and the polycrystalline silicon layer under the nitride film spacer, and forming a metal gate electrode by the etching process; Growing an oxide film on the exposed polycrystalline silicon layer and the gate oxide film of the metal gate electrode by a re-oxidation process; Etching the oxide layer and the gate oxide layer using the hard mask layer and the nitride spacer as a mask; Implanting low concentration of the second conductivity type impurity ions onto the metal gate electrode as a mask; Forming an oxide spacer on sidewalls of the metal gate electrode including the nitride spacer; Forming a source / drain region of an LDD structure on a semiconductor substrate on both sides of the metal gate electrode including the oxide spacer.