KR20040001939A - Method for forming self align contact in semiconductor device - Google Patents
Method for forming self align contact in semiconductor device Download PDFInfo
- Publication number
- KR20040001939A KR20040001939A KR1020020037273A KR20020037273A KR20040001939A KR 20040001939 A KR20040001939 A KR 20040001939A KR 1020020037273 A KR1020020037273 A KR 1020020037273A KR 20020037273 A KR20020037273 A KR 20020037273A KR 20040001939 A KR20040001939 A KR 20040001939A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- hard mask
- semiconductor device
- contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로 특히, 자기정렬콘택 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact.
소자의 집적도 향상을 통하여 포토레지스트를 이용한 패턴 형성 공정 자체의 마진과 오버래이의 정확도(Overlay accuracy)를 안정적으로 확보하기가 어렵게 됨에 따라 SAC 공정이 도입되었는 바, SAC 공정은 콘택홀 등의 패턴을 형성함에 있어서 별도의 마스크를 사용하지 않고 이미 증착된 물질을 이용하여 식각을 하는 방식으로 비용 감소에 큰 역할을 하는 것으로, SAC 공정 자체는 여러가지 방법을 사용하고 있으나 대표적인 방법으로는 질화막을 식각방지막으로 사용한다.The SAC process was introduced as it was difficult to stably secure the margin and overlay accuracy of the pattern forming process itself using photoresist by improving the integration degree of the device. In forming, it plays a big role in reducing the cost by etching using the material already deposited without using a separate mask. The SAC process itself uses various methods, but a representative method is using a nitride film as an anti-etching film. use.
또한, 집적도 증가에 따라 층간 콘택 공정이 적용되었고, 이러한 층간 콘택을 이용한 플러그가 도입되었다. 예컨대, 0.15㎛급 반도체소자에서는 비트라인콘택(Bitline contact)과 스토리지노드콘택(Storagenode contact)을 형성할 때 원형(Hole type) 콘택마스크를 사용하는데, 이는 사진식각공정의 오정렬(Mis-alignment)로 인하여 콘택영역 확보에 어려움이 있다. 이를 개선하기 위하여 이종의 절연막질간 예컨대, 산화막과 질화막의 식각선택비 차이를 이용하는 전술한 바와 같은 SAC 공정을 도입하였다.In addition, as the degree of integration increases, an interlayer contact process is applied, and a plug using the interlayer contact is introduced. For example, in the 0.15㎛ class semiconductor device, a circular type contact mask is used to form a bitline contact and a storage node contact, which is a misalignment of the photolithography process. There is a difficulty in securing the contact area. In order to improve this, a SAC process as described above using a difference in etching selectivity between different types of insulating films, for example, an oxide film and a nitride film, has been introduced.
SAC에 의한 플러그 식각시 T형 플러그 마스크 또는 I형 플러그 마스크를 이용하는데, 이는 플러그간을 절연시키기 위한 산화막을 식각하여 플러그 콘택홀을 형성한 후, 플러그 콘택홀에 예컨대, 폴리실리콘을 증착하고 이를 화학기계적연마(Chemical Mechanical Polishing; 이하 CMP라 함) 공정으로 평탄화시켜 콘택홀에 플러그를 매립시키는 기술인 바, 층간절연막(Inter Layer Dielectric; ILD)에 의해 절연된 하부전도층과 상부전도층간의 콘택을 실시함에 있어서, 콘택홀 형성후 이 콘택홀 내부에만 폴리실리콘 등의 플러그 물질을 매립하여 플러그를 형성하는 이러한 방법이 널리 사용되고 있다.In the plug etching by SAC, a T-type plug mask or an I-type plug mask is used, which forms a plug contact hole by etching an oxide film to insulate the plugs, and then deposits polysilicon in the plug contact hole, for example. It is a technology to planarize the plug in the contact hole by flattening by Chemical Mechanical Polishing (CMP) process. The contact between the lower conductive layer and the upper conductive layer insulated by Inter Layer Dielectric (ILD) is formed. In practice, a method of forming a plug by embedding a plug material such as polysilicon only in the contact hole after forming the contact hole is widely used.
그러나, T형 마스크를 이용한 SAC 플러그 공정은 비트라인콘택의 오정렬 여유는 충분하나, 스토리지코드콘택의 오정렬과 산화막 식각시 발생하는 경사 단면으로 인하여 충분한 콘택영역 확보에 문제가 있어, 0.13㎛급 반도체소자에서는 그 적용이 어렵다. 한편, I형 마스크를 이용한 SAC 고정은 소자분리마스크(ISOlation mask; 이하 ISO라 함)를 필드산화막(Field OXide; 이하 FOX이라 함) 위로 이동시켜 산화막을 식각하는 방법으로서, 최근에 주로 적용되는 기술이다.However, the SAC plug process using the T-type mask has sufficient margin of misalignment of the bit line contacts, but there is a problem in securing a sufficient contact area due to the misalignment of the storage code contacts and the inclined cross section generated during the etching of the oxide film. It is difficult to apply. On the other hand, SAC fixing using an I-type mask is a method of etching an oxide film by moving an isolation mask (hereinafter referred to as ISO) over a field oxide film (hereinafter referred to as FOX). to be.
도 1은 질화막을 식각방지막으로 사용하는 I형 마스크를 이용한 SAC 형성 공정을 도시한 단면도로서, 기판(10) 상에 이웃하는 게이트전극(11)이 형성되어 있으며, 그 측벽에는 스페이서(13)가 형성되어 있으며, 그 상부에는 SAC 공정시 게이트전극의 손실을 방지하기 위한 질화막 계열의 식각방지막 즉, 하드마스크(12)가 형성되어 있다.FIG. 1 is a cross-sectional view illustrating a SAC forming process using an I-type mask using a nitride film as an etch stop layer. A neighboring gate electrode 11 is formed on a substrate 10, and a spacer 13 is formed on a sidewall thereof. A nitride mask-based etch stop layer, that is, a hard mask 12, is formed on the upper portion thereof to prevent loss of the gate electrode during the SAC process.
한편, 전술한 바와 종래의 SAC에 의한 플러그 형성 공정은 다음과 같은 문제점이 있는 바, 도 1은 이러한 구조 상부에 층간절연막(14)을 증착한 후, 스토리지노드 또는 비트라인 등의 콘택 플러그 형성을 위한 SAC 공정시 'A'와 같이 하드마스크(12)와 게이트전극(11)의 손실을 나타내고 있다. 이러한 SAC 공정 진행시 기판(10) 하부의 불순물 접합영역까지 식각 타겟을 하고 식각 진행시 전술한 'A'와 같은 손실을 피할 수 없다.On the other hand, the plug forming process according to the conventional SAC as described above has the following problems, Figure 1 is after depositing the interlayer insulating film 14 on the structure, and forming a contact plug, such as a storage node or bit line In the SAC process, the loss of the hard mask 12 and the gate electrode 11 is shown as 'A'. During the SAC process, an etching target is performed to the impurity junction region under the substrate 10, and the loss as described above is inevitable during the etching process.
즉, 식각 공정시 하지층과의 통전을 위해 과도식각(Over etch)을 진행하여야하는데 이 때, 상부의 게이트전극(11) 등의 전도층은 계속적으로 오픈된 상태에서 어택(Attack)을 받게 되는 바, 이는 후속 플러그 등의 전도성 물질과의 단락을 유발하여 소자의 전기적 특성 열화 및 수율을 떨어뜨리는 요인이 된다. 이러한 문제점은 주로 I형 마스크를 이용한 SAC 공정시 주로 이슈(Issue)화 되고 있는 바, 특히 I형 마스크를 이용한 SAC 식각 공정시 게이트 하드마스크의 손실을 최소화할 수 있는 SAC 식각 방법이 요구되어 진다.That is, during the etching process, the over etch must be performed to conduct electricity with the underlying layer. At this time, the conductive layer such as the gate electrode 11 on the upper side is subjected to an attack while being continuously opened. Bars cause short-circuits with conductive materials such as subsequent plugs, resulting in deterioration of electrical characteristics and yield of devices. This problem is mainly an issue in the SAC process using an I-type mask. In particular, a SAC etching method capable of minimizing the loss of a gate hard mask during the SAC etching process using an I-type mask is required.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 자기정렬콘택 공정에서 하드마스크의 손실에 의해 초래되는 반도체소자의 결함을 방지하기 위한 반도체소자의 자기정렬콘택 형성방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, provides a method for forming a self-aligned contact of the semiconductor device for preventing the defect of the semiconductor device caused by the loss of the hard mask in the self-aligned contact process. There is a purpose.
도 1은 질화막을 식각방지막으로 사용하는 SAC 형성 공정을 도시한 단면도.1 is a cross-sectional view showing a SAC forming process using a nitride film as an etch stop layer.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체소자의 자기정렬콘택 형성 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a process of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 기판 21 : 활성영역20: substrate 21: active area
22' : 도전막 23' : 제1하드마스크22 ': conductive film 23': first hard mask
24' : 제2하드마스크 26: 식각정지막24 ': second hard mask 26: etch stop
27 : 절연막 28 : 콘택홀27: insulating film 28: contact hole
상기와 같은 문제점을 해결하기 위해 본 발명은, 기판 상에 도전막과 제1하드마스크용 탄화실리콘막 및 제2하드마스크용 질화막이 적층된 다수의 도전패턴을 형성하는 단계; 상기 도전패턴이 형성된 프로파일을 따라 식각정지막을 형성하는 단계; 상기 식각정지막 상이 형성된 기판 전면에 절연막을 형성하는 단계; 상기 절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 기판을 노출시키는 콘택홀을 형성하는 단계; 및 상기 콘택홀을 매립하여 상기 노출된 기판과 도통되는 플러그를 형성하는 단계를 포함하는 반도체소자의 자기정렬콘택 형성방법을 제공한다.In order to solve the above problems, the present invention comprises the steps of forming a plurality of conductive patterns in which a conductive film, a silicon carbide film for the first hard mask and a nitride film for the second hard mask are stacked; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an insulating film on an entire surface of the substrate on which the etch stop film is formed; Selectively etching the insulating layer to form a contact hole exposing the substrate between the conductive patterns; And forming a plug that fills the contact hole and is electrically connected to the exposed substrate.
본 발명은, 게이트전극 등 도전패턴의 하드마스크를 탄화실리콘막과 질화막의 이중 구조로 형성함으로써, 이종막 구조의 하드마스크에 의한 SAC 식각 공정 마진을 향상시키며, 질화막과 거의 무한대의 식각선택비를 갖는 탄화실리콘막에 의해 하드마스크의 손실을 방지하고자 한다.According to the present invention, a hard mask of a conductive pattern such as a gate electrode is formed in a double structure of a silicon carbide film and a nitride film, thereby improving the SAC etching process margin by the hard mask having a heterogeneous film structure, and reducing the etching selectivity of the nitride film and the almost infinite etching selectivity. It is intended to prevent loss of the hard mask by the silicon carbide film having.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도 2a 내지 도 2d를 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체소자의 자기정렬콘택 형성 공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a process of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.
먼저 도 2a에 도시된 바와 같이, 반도체소자를 이루기 위한 여러 요소가 형성된 기판(20) 상에 도전막(22)과 제1하드마스크용 탄화실리콘막(23)과 제2하드마스크용 질화막(24)을 차례로 적층한 다음, 게이트전극 패턴 등의 도전패턴 형성을 위한 포토레지스트 패턴(25)을 형성한다.First, as shown in FIG. 2A, the conductive film 22, the silicon carbide film 23 for the first hard mask, and the nitride film 24 for the second hard mask are formed on the substrate 20 on which various elements for forming a semiconductor device are formed. ) Are sequentially stacked, and then a photoresist pattern 25 for forming a conductive pattern such as a gate electrode pattern is formed.
여기서, 도면부호 '21'은 활성영역을 도시하며, 도전막은 폴리실리콘, 텅스텐 등의 금속, 텅스텐 실리사이드 등의 금속 실리사이드 또는 텅스텐질화막 등의 금속질화막을 단독 또는 다층 구조로 형성한 것이다.Here, reference numeral 21 denotes an active region, and the conductive film is formed of a metal nitride film such as a metal silicide such as polysilicon or tungsten, a metal silicide such as tungsten silicide or a tungsten nitride film in a single or multi-layered structure.
또한, 하드마스크 물질로 실리콘질화막 또는 실리콘산화질화막 등의 제2하드마스크용 질화막(24)과 제1하드마스크용 탄화실리콘막(23)의 이종 구조로 형성함으로써 단일 층 또는 동일 물질의 형성에 따른 후속 SAC 공정시의 손실을 방지할 수있음은 물론, 탄화실리콘은 저체의 강한 결합력에 의해 화학적 반응에 의해서는 식각이 이루어지지 않고 스퍼터링 등의 물리적 식각에 의해서만 식각이 이루어지는데 반해, 질화막은 화학적 반응에 의해 식각이 이루어진다는 특징이 있어, 두 물질간의 거의 무한대에 가까운 식각선택비를 확보할 수 있다.In addition, the hard mask material may be formed of a heterogeneous structure of the second hard mask nitride film 24 such as the silicon nitride film or the silicon oxynitride film and the first hard mask silicon carbide film 23 to form a single layer or the same material. In addition to preventing loss during the subsequent SAC process, silicon carbide is not etched by a chemical reaction due to the strong binding force of the bottom, but is etched only by physical etching such as sputtering. It is characterized by the etching is performed, it is possible to secure an almost infinity etching selectivity between the two materials.
도 2b에 도시된 바와 같이, 포토레지스트 패턴(25)을 식각마스크로 제2하드마스크용 질화막(24)과 제1하드마스크용 탄화실리콘막(23) 및 도전막(22)을 선택적으로 식각함으로써, 도전막(22')과 제1하드마스크(23') 및 제2하드마스크(24')가 적층된 구조의 게이트전극 패턴을 형성한다.As shown in FIG. 2B, the second hard mask nitride film 24, the first hard mask silicon carbide film 23 and the conductive film 22 are selectively etched using the photoresist pattern 25 as an etching mask. A gate electrode pattern having a structure in which the conductive film 22 ', the first hard mask 23', and the second hard mask 24 'are stacked is formed.
이 때, 탄화실리콘막(23)의 식각은 전술한 바와 같이 스퍼터링 등이 물리적 식각을 이용한다.At this time, the etching of the silicon carbide film 23 uses sputtering or the like as described above.
이어서, 게이트전극 패턴이 형성된 프로파일을 따라 SAC 공정에 따른 게이트전극 패턴의 측벽 손실을 방지함과 동시에 산화막계열인 절연막(27)과의 식각선택비를 확보할 수 있는 질화막을 이용하여 식각정지막(26)을 형성한다.Subsequently, the sidewall loss of the gate electrode pattern according to the SAC process is prevented along the profile in which the gate electrode pattern is formed, and at the same time, the etch stop layer is formed by using a nitride film which can secure an etching selectivity with the insulating film 27, which is an oxide film series. 26).
이어서, 식각정지막(26) 상에 BPSG(Boro Phospho Silicate Glass), HDP(High Density Plasma)산화막 등의 산화막 계열의 절연막(27)을 증착한 다음, CMP 또는 전면식각을 통해 그 상부를 평탄화시킨다.Subsequently, an oxide-based insulating film 27 such as BPSG (Boro Phospho Silicate Glass) or HDP (High Density Plasma) oxide film is deposited on the etch stop layer 26, and then the top thereof is planarized through CMP or full surface etching. .
이어서, 절연막(27) 상에 SAC 식각을 실시하기 위한 포토레지스트 패턴(도시하지 않음)을 형성한 다음, 이를 식각마스크로 절연막(27)과 식각정지막(26)을 식각하여 기판(20)의 활성영역(21)을 노출시키는 콘택홀(28)을 형성하는 바, 콘택홀(28)이 형성되는 부위의 식각정지막(26)은 게이트전극 패턴 측벽부분에서만남는 스페이서 형태를 이룬다.Subsequently, a photoresist pattern (not shown) for SAC etching is formed on the insulating layer 27, and then the insulating layer 27 and the etch stop layer 26 are etched using an etching mask. As the contact hole 28 exposing the active region 21 is formed, the etch stop layer 26 at the portion where the contact hole 28 is formed has a spacer shape remaining only at the sidewall portion of the gate electrode pattern.
한편, 전술한 절연막(27)과 식각정지막(26) 식각시에는 통상의 SAC 공정시 사용하는 불소계플라즈마 예컨대, C2F4, C2F6, C3F8, C4F6, C5F8또는 C6F6등의 CxFy(x,y는 1 ∼ 10)를 주식각가스로 하며, 여기에 SAC 공정시 폴리머를 발생시키기 위한 가스 즉, CH2F2, C3HF5, CH3F, CH2, CH4, C2H4, H2또는 CHF3등의 가스를 첨가하며, 이 때 식가선택비 향상과 플라즈마 안정 및 스퍼터링 효과를 증가시켜 식각멈춤 개선을 위해 He, Ne, Ar 또는 Xe 등의 비활성 가스를 사용한다.On the other hand, when etching the insulating film 27 and the etch stop film 26 described above, for example, C 2 F 4 , C 2 F 6 , C 3 F 8 , C 4 F 6 , C used in a normal SAC process. CxFy (x, y is 1 to 10), such as 5 F 8 or C 6 F 6 , is used as a stock angle gas, and a gas for generating a polymer in the SAC process, that is, CH 2 F 2 , C 3 HF 5 , Adds gases such as CH 3 F, CH 2 , CH 4 , C 2 H 4 , H 2, or CHF 3 , at this time He, Ne for improved etch selectivity, plasma stabilization and sputtering effect Inert gas, such as Ar or Xe, is used.
이 때, 질화막으로 이루어진 제2하드마스크(24')는 어택을 받아 손실이 발생하나, 탄화실리콘막으로 이루어진 제1하드마스크(23')는 손실이 발생하지 않는다.At this time, the second hard mask 24 'made of a nitride film receives an attack, but a loss occurs, but the first hard mask 23' made of a silicon carbide film does not cause a loss.
이어서, 콘택홀(28)이 형성된 기판(20) 전면에 플러그 물질을 증착하여 노출된 기판(20)의 활성영역(21)과 도통시킨 다음, 제1하드마스크(23')가 노출될때까지 플러그 물질과 절연막(27)과 식각정지막(26) 및 제2하드마스크(24')을 CMP 공정을 통해 연마하여 제거함으로써 플러그(29)간을 분리시킴으로써, 도 2d와 같은 공정 단면이 완성된다.Subsequently, a plug material is deposited on the entire surface of the substrate 20 on which the contact hole 28 is formed to be in contact with the active region 21 of the exposed substrate 20, and then the plug is exposed until the first hard mask 23 ′ is exposed. The material, the insulating film 27, the etch stop film 26, and the second hard mask 24 'are removed by grinding through the CMP process to separate the plugs 29, thereby completing the process cross section shown in FIG. 2D.
이렇듯 손실된 제2하드마스크(24')를 제거함으로써 CMP 공정시 단차 발생을 억제하고 하드마스크의 비균일성에 따른 플러그의 심(Seam) 발생 등 결함 발생을 억제할 수 있다.By removing the lost second hard mask 24 'as described above, it is possible to suppress the generation of steps in the CMP process and to prevent the occurrence of defects such as the generation of plug seams due to the non-uniformity of the hard mask.
전술한 바와 같이, 본 발명에서 일예로 제시된 콘택홀 패턴은 후속 공정에서이를 통해 기판과 도통되는 전도성 물질에 의해 기판의 활성영역과 비트라인 또는 스토리지노드와 연결되는 반도체소자에서 중요한 역할을 담당하게 되며, 하드마스크의 손실을 방지하여 게이트전극의 노출에 따른 전기적 단락을 방지하며, 플러그 형성 후 분리 공정에서의 결함 발생을 최소화할 수 있음을 실시예를 통해 알아 보았다.As described above, the contact hole pattern presented as an example in the present invention plays an important role in the semiconductor device connected to the active region and the bit line or the storage node of the substrate by a conductive material which is connected to the substrate through subsequent processes. In order to prevent the loss of the hard mask to prevent an electrical short circuit caused by the exposure of the gate electrode, it was found through the embodiment that the occurrence of defects in the separation process after plug formation can be minimized.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은, 자기정렬콘택 공정시 콘택오픈결함과 콘택저항을 감소시킬 수 있어, 궁극적으로 반도체 소자의 수율을 크게 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above can reduce contact open defects and contact resistance during the self-aligned contact process, and ultimately, it can be expected to have an excellent effect of greatly improving the yield of semiconductor devices.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020037273A KR100856058B1 (en) | 2002-06-29 | 2002-06-29 | Method for forming self align contact in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020037273A KR100856058B1 (en) | 2002-06-29 | 2002-06-29 | Method for forming self align contact in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040001939A true KR20040001939A (en) | 2004-01-07 |
| KR100856058B1 KR100856058B1 (en) | 2008-09-02 |
Family
ID=37313670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020037273A KR100856058B1 (en) | 2002-06-29 | 2002-06-29 | Method for forming self align contact in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100856058B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10818495B2 (en) | 2018-07-12 | 2020-10-27 | Alpha Power Solutions Limited | Semiconductor devices and methods of making the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100307556B1 (en) * | 1998-10-14 | 2001-10-19 | 박종섭 | Manufacturing method of semiconductor device |
| KR20000052110A (en) * | 1999-01-29 | 2000-08-16 | 윤종용 | Method for etching etch stopping layer of self-aligned contact |
| KR20020039096A (en) * | 2000-11-20 | 2002-05-25 | 윤종용 | Method for forming self aligned contact |
| KR20020048618A (en) * | 2000-12-18 | 2002-06-24 | 윤종용 | Semiconductor device with self aligned silicide layer and method for forming the same |
-
2002
- 2002-06-29 KR KR1020020037273A patent/KR100856058B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10818495B2 (en) | 2018-07-12 | 2020-10-27 | Alpha Power Solutions Limited | Semiconductor devices and methods of making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100856058B1 (en) | 2008-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7094672B2 (en) | Method for forming self-aligned contact in semiconductor device | |
| US6268252B1 (en) | Method of forming self-aligned contact pads on electrically conductive lines | |
| KR100492898B1 (en) | Method for fabricating semiconductor device | |
| US7384823B2 (en) | Method for manufacturing a semiconductor device having a stabilized contact resistance | |
| KR100505450B1 (en) | Method for fabricating semiconductor device using damascene process | |
| KR20030049132A (en) | Method for fabricating semiconductor device | |
| KR100856058B1 (en) | Method for forming self align contact in semiconductor device | |
| KR20030096660A (en) | Method for fabricating semiconductor device | |
| KR20040001938A (en) | Forming method of self align contact in semiconductor device | |
| KR100945225B1 (en) | Method for fabrication of semiconductor device | |
| KR100919675B1 (en) | Method for fabrication of semiconductor device | |
| KR100553517B1 (en) | Method for forming contact plug of semiconductor device | |
| KR20020091891A (en) | A forming method of contact | |
| KR100869358B1 (en) | Method for fabricating semiconductor device | |
| KR100744001B1 (en) | A forming method of landing plug contact | |
| KR100471411B1 (en) | Method for fabricating semiconductor device with improved reduction of seam | |
| KR100649971B1 (en) | Method for forming contact plug of semiconductor device | |
| KR100411026B1 (en) | Method of manufacturing a semiconductor device | |
| KR100869357B1 (en) | Method for fabricating semiconductor device with improved protection of void | |
| KR20040057490A (en) | Method for fabricating semiconductor device | |
| KR100744681B1 (en) | A fabricating method of semiconductor device | |
| KR100843869B1 (en) | Method for manufacturing a semiconductor device | |
| KR20040001945A (en) | Fabricating method of semiconductor device with improved protection capability of contact not open | |
| KR20040001888A (en) | Method for fabricating semiconductor device | |
| KR20040001847A (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |