KR20040001741A - Method for manufacturing small contact in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a fine contact of a semiconductor device is provided to be capable of effectively removing a hard mask after forming a contact hole by forming the hard mask using tungsten or nitride titanium. CONSTITUTION: After forming an insulating layer(300) at the upper portion of a semiconductor substrate(100), a metal hard mask(450) is formed at the upper portion of the insulating layer. A contact hole(350) is formed through the insulating layer for exposing the upper surface of the semiconductor substrate by selectively patterning the insulating layer using the metal hard mask as an etching mask. Then, the metal hard mask is selectively removed from the resultant structure. Preferably, the metal hard mask is made of a tungsten layer or a nitride titanium layer.

Description

Method for manufacturing micro contact of semiconductor device {Method for manufacturing small contact in semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing small contacts.

As semiconductor devices become more integrated and design rules become more sophisticated, many problems are involved in the process of patterning a material layer to form a device. In particular, in order to realize a pattern having a smaller size in the photolithography process, the layer thickness of the photoresist is becoming thinner. Accordingly, in some cases, the photoresist layer may not properly serve as an etch mask during dry etching for pattern formation. In addition, a so-called striation phenomenon in which the pattern is scrambled may be caused during the patterning process. Such patterning defects eventually act as an important factor inducing defects in semiconductor devices.

As one of methods for overcoming the defects caused by the limitation of the photoresist in the patterning process, the concept of a hard mask has been introduced or evaluated. That is, a method of performing patterning using such a polysilicon hard mask by introducing another hard film, for example, a polysilicon hard mask under the photoresist layer at the time of forming a contact hole for fine contact It is evaluated.

Specifically, in order to effectively electrically connect a bit line or a capacitor with an active region of a semiconductor substrate in a semiconductor memory device manufacturing process of 256M DRAM or more, intermediates such as pad contacts may be used. The connectors are being introduced. The process of forming the pad contacts involves a process of forming a contact hole for contact by photo etching the insulating layer.

However, as the design rule becomes very low to 0.14 μm or less, when the photoresist mask is used, the thickness of the photoresist layer becomes low, making it difficult to maintain the role of the etch mask until the micro contact hole is completely penetrated. have. Therefore, a hard mask of a hard material such as polysilicon is introduced before coating the photoresist layer.

However, in the case of forming a micro contact hole using a hard mask made of polysilicon, it is difficult to measure the critical dimension (CD) using ILS (In-line SEM) or to check whether the bottom of the contact hole is normally opened. it's difficult. In-line SEM (ILS) scans electrons and detects secondary electrons reflected by the detector to shape an image.

However, when the hard mask of the polysilicon is present over the entire surface of the contact hole, especially when the polysilicon is doped, the hard mask of the polysilicon serves as a ground and is reflected from the inside of the contact hole. Coming out will absorb the secondary electrons. Therefore, the number of reflected secondary electrons is absolutely insufficient, so that the image of the inside of the fine contact hole is difficult to be clearly obtained. Nevertheless, the process of removing the hard mask of polysilicon is not easy. Therefore, the phenomenon in which the image of the micro contact hole is not clearly obtained by the ILS may act as an element that makes it difficult to employ the polysilicon hard mask in the manufacture of semiconductor devices.

The technical problem to be achieved by the present invention can be introduced as an etch mask in the process of patterning a contact hole for a fine contact, and prevents a bad influence from occurring on a critical line width (CD) or a pattern formed before the bottom check inspection of the contact hole. The present invention provides a method for manufacturing a micro contact of a semiconductor device that introduces a new hard mask that can be effectively removed.

1 to 6 are cross-sectional views schematically illustrating a method of manufacturing a small contact of a semiconductor device according to an embodiment of the present invention.

7 is a scanning electron micrograph of a contact hole for a fine contact formed according to an embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem provides a method of manufacturing a fine contact of a semiconductor device using a metal hard mask. The manufacturing method includes forming a metal hard mask on an insulating layer on a semiconductor substrate, and forming a contact hole for patterning the insulating layer using the metal hard mask as an etch mask to penetrate the insulating layer to expose a surface of the semiconductor substrate. Forming and selectively removing the metal hard mask.

Here, the metal hard mask is formed including a tungsten layer or a titanium nitride layer.

In addition, the removing of the metal hard mask may be performed by performing wet etching using an oxidizing agent or a solution containing an oxidizing agent as an etching medium.

In this case, the etching medium may include a mixture of sulfuric acid and hydrogen peroxide, may include hydrogen peroxide or a mixture of hydrogen peroxide and water, or may include ozone or ozone water.

According to the present invention, it can be introduced as an etch mask in the process of patterning a contact hole for a fine contact, and can be effectively removed to prevent the bad influence of the pattern formed before the critical line width (CD) or the bottom check inspection of the contact hole. The present invention provides a method of manufacturing a fine contact of a semiconductor device that can introduce a new hard mask.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, the layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. May be interposed.

In an embodiment of the present invention, a metal hard mask is introduced as an etching mask in a patterning process of forming a contact hole for a fine contact. Such a metal hard mask may function as an etching mask sufficiently effectively in the patterning process, and may also be selectively removed sufficiently without substantially affecting the patterns after the patterning process.

1 to 6 are cross-sectional views schematically illustrating a method of manufacturing a small contact of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a hard mask layer 400 is formed on an insulating layer 300. In detail, the semiconductor substrate 100 includes a gate 210, a gate capping layer 220, and a gate spacer 220 on an active region set by the device isolation 150 of the semiconductor substrate 100. A gate stack 200 is formed. After the transistor structure including the gate stack 200 is formed on the semiconductor substrate 100, an insulating layer 300 covering the gate stack 200 is formed. The insulating layer 300 may be formed of various insulating materials, for example, silicon oxide.

In order to form a fine pattern, the surface of the deposited insulating layer 300 is planarized by chemical mechanical polishing (CMP) or etch back. Thereafter, the hard mask layer 400 is formed on the insulating layer 300 having a flat surface. For example, a tungsten (W) layer is deposited on the insulating layer 300 or a metal layer such as a titanium nitride layer is deposited as the hard mask layer 400.

When the etching mask is formed using only the photoresist layer, the design rule is reduced, for example, the design rule is reduced to 0.14 μm or less, and the thickness of the photoresist layer is inevitably reduced until the photoresist layer completely penetrates the fine contact hole. The phenomenon of not playing a role as an etching mask is occurring. In addition, a scratching phenomenon in which the pattern is scrambled occurs. The introduction of the hard mask layer 400 in the embodiment of the present invention is for forming a hard mask for preventing such a phenomenon or defect.

Referring to FIG. 2, a photoresist pattern 500 is formed on the hard mask layer 400 to pattern the hard mask layer 400 into a hard mask. Specifically, in order to pattern the hard mask layer 400 as a hard mask to be used as an etch mask in the patterning process for the fine contact hole, a photoresist layer is coated on the hard mask layer 400 and a photo process, that is, exposure is performed. And developing to form the photoresist pattern 500.

Referring to FIG. 3, the hard mask layer 400 is patterned using the photoresist pattern 500 as an etch mask to form a hard mask 450. Patterning of the hard mask layer 400 may be performed by dry etching. After the hard mask 450 is patterned, the photoresist pattern 500 is removed.

Referring to FIG. 4, the contact hole 350 is completely opened by etching the exposed portion of the insulating layer 300 using the hard mask 450 as an etching mask. In this case, since the insulating layer 300 is preferably formed of silicon oxide, the etching of the insulating layer 300 may be performed by dry etching of the oxide. The contact hole 350 is patterned to completely expose the lower surface of the semiconductor substrate 100, that is, the surface of the active region. The contact hole 350 is for fine contact. The micro contact serves to effectively electrically connect a bit line or capacitor to be formed later with the active region of the semiconductor substrate 100. Such fine contacts can illustrate intermediate connectors such as pad contacts.

Referring to FIG. 5, the hard mask 450 is selectively removed. After the contact hole 350 is completed, the hard mask 450 used as the etching mask 450 is removed. In this case, since the hard mask 450 is formed of a metallic material, for example, is formed of a tungsten layer or a titanium nitride layer, the hard mask 450 is removed by using an etchant for the metallic material.

For example, the silicon oxide preferably forming the insulating layer 300, the silicon nitride Si ₃ N ₄ and the semiconductor substrate 100 preferably forming the gate capping layer 220 or the gate spacer 230 are preferable. The hard mask 450 is stripped by wet etching using SPM (sulfuric acid and hydrogen peroxide mixed solution), hydrogen peroxide, a mixture of hydrogen peroxide and water, or a high concentration of ozone water, which has substantially no etching ability.

Etching media as described above have the ability to remove the metal layer constituting the hard mask 450 with an oxidant or a solution containing an oxidant. On the other hand, the etching medium, the portion that should not be preferably affected in the process of removing the hard mask 450, for example, the insulating layer 300, the semiconductor substrate 100, the gate capping layer 220 and the gate The silicon oxide, silicon, or silicon nitride constituting the spacer 230 may not exhibit substantial etching ability. Thus, by using the above etching media, selective removal of the hard mask 450 can be effectively performed. That is, only the hard mask 450 of the tungsten layer used as the etching mask may be selectively removed without invading the peripheral layers.

Referring to FIG. 6, the conductive contact 600 filling the contact hole 350 is formed after the hard mask 450 is removed. The conductive contact 600 effectively connects a bit line or a capacitor to be subsequently formed with the active region of the semiconductor substrate 100.

In the present invention, the hard mask including the metal as in the embodiment, for example, tungsten or titanium nitride, can be easily and effectively removed by wet etching after the process of patterning the contact hole for the fine contact. Accordingly, by observing the resultant surface on which the contact hole is formed after removal of the hard mask with an in-line scanning electron microscope, it is easy to determine the critical line width (CD) of the contact hole or whether the bottom of the contact hole is completely opened. It can be confirmed effectively. At this time, since the obstacles caused by the hard mask are effectively removed in the process of obtaining the scanning electron micrograph, the scanning electron micrograph of the contact hole or the like can be obtained at a higher resolution.

7 is a scanning electron micrograph (SEM) of a contact hole for a micro contact formed according to an embodiment of the present invention. FIG. 7 is a SEM photograph of a target result after forming a contact hole using a tungsten hard mask and removing the hard mask by wet etching as described above. As shown in FIG. 7, the inside of the contact hole may be effectively managed by an in-line SEM (ILS).

In the conventional case of using a polysilicon hard mask, the inside of the contact hole was not observed by SEM after the formation of the contact hole. However, when the contact hole is formed by using a tungsten hard mask as in the embodiment of the present invention, the contact hole is removed. As shown in FIG. 7, the inside of the contact hole is clearly visible, and thus, the contact hole may be more effectively processed than the critical line width (CD) measurement or inspection.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, after forming a contact hole by introducing a hard mask of tungsten or titanium nitride, the hard mask can be effectively removed by stripping such as wet etching. Thereafter, by observing the contact hole formed by obtaining the SEM picture, the CD measurement of the contact hole and the internal inspection of the contact hole can be performed more precisely and reliably.

Claims (6)

Forming a metal hard mask on an insulating layer on the semiconductor substrate; Patterning the insulating layer using the metal hard mask as an etch mask to form a contact hole penetrating the insulating layer to expose a surface of the semiconductor substrate; And And selectively removing the metal hard mask. The method of claim 1, wherein the metal hard mask Method for producing a fine contact of a semiconductor device comprising a tungsten layer or a titanium nitride layer. The method of claim 1, wherein removing the metal hard mask comprises: A method of manufacturing a micro contact of a semiconductor device, comprising performing wet etching using an oxidizing agent or a solution containing an oxidizing agent as an etching medium. The method of claim 3, wherein the etching medium is A fine contact manufacturing method for a semiconductor device comprising a mixture of sulfuric acid and hydrogen peroxide. The method of claim 3, wherein the etching medium is A method for manufacturing a micro contact of a semiconductor device comprising hydrogen peroxide or a mixture of hydrogen peroxide and water. The method of claim 3, wherein the etching medium is A fine contact manufacturing method for a semiconductor device comprising ozone or ozone water.