KR20040001482A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing a plate electrode of a cell region from being punched. CONSTITUTION: A plurality of word lines(22) and bit lines(24) are formed at a cell region and a peripheral region of a semiconductor substrate(21), respectively. After forming the first interlayer dielectric on the entire surface of the resultant structure for enclosing the word and bit lines, the first and second trench are formed by selectively etching the first interlayer dielectric. A storage node(27a) and a buffer storage pattern(27b) are formed at the first and second trench, respectively. A capacitor is completed by sequentially forming a dielectric layer(28) and a plate electrode(29) at the upper portion of the cell region. After forming the second interlayer dielectric at the upper portion of the resultant structure, the first and second contact hole are formed by selectively etching the first and second interlayer dielectric. A plurality of metal lines(32,33) are formed at the first and second contact hole.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing a plate electrode of a cell region from being punched during formation of a metal wiring due to a step between a cell region and a peripheral circuit region. will be.

As the integration of semiconductor devices proceeds, the device size is also getting smaller, and accordingly, the capacitor area is also getting smaller. The capacitor has a structure in which a dielectric film is interposed between the storage electrode and the plate electrode, and the capacitance of the capacitor having such a structure (hereinafter referred to as capacitance) is proportional to the electrode surface area and the dielectric constant of the dielectric film, whereas the spacing between electrodes Inversely proportional to the thickness of the dielectric film.

Therefore, recent technical developments for increasing capacitance have been inclined to increase electrode surface area or to apply high dielectric constant dielectric films such as tantalum oxynitride (TaON) or tantalum oxide (Ta2O5).

In this case, a method of increasing the surface area of the electrode is a method of forming a storage electrode into a three-dimensional structure of a cylinder or a pin structure, and in addition, hemispherical silicon grains on the electrode surface The method of forming a grain) and the method of increasing the height of a capacitor are used a lot.

In particular, the method of increasing the height of the capacitor is a method of compensating for the reduced capacitance according to the narrowed capacitor area by increasing the height of the capacitor, and is widely applied because it is relatively easy.

However, when the height of the capacitor is increased, the height of the metal 1 contact (hereinafter referred to as M1C) is also increased at the same time. Accordingly, due to the step difference between the cell region and the peripheral circuit region, the plate electrode formed in the cell region when the M1C is formed is formed. Punch occurs and device defects are caused.

In detail, the M1C refers to a connection path of a metal wire connected to a semiconductor substrate, a word line, a bit line, a plate electrode, and the like, and corresponds to an increase in the height of the capacitor, that is, the height of the storage electrode or the plug for the storage electrode. The height can not but be increased.

However, as shown in FIG. 1, the metal wires 12 and 13 are formed not only in the cell region but also in the peripheral circuit region, where M1C is formed simultaneously in the cell region and the peripheral circuit region, and has a relatively higher peripheral circuit. Since it is common to form a height considering the region as a target, the punch of the plate electrode 9 is generated by M1C of the cell region formed with a relatively low height, and in this case, the metal wiring ( The contact area between 12) and the plate electrode 9 becomes small, which causes an increase in resistance, which adversely affects device operation and causes device failure.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 a word line, 3 a first interlayer insulating film, 4 a bit line, 5 a second interlayer insulating film, 6 a third interlayer insulating film, 7 a storage electrode, 8 is a dielectric film, 10 is a capacitor, 11 is a fourth interlayer insulating film, and 12 and 13 are metal wirings, respectively.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing punching of a plate electrode in a cell region when M1C is formed.

1 is a cross-sectional view for explaining the problem of the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 word line

23: first interlayer insulating film 24: bit line

25: second interlayer insulating film 26: third interlayer insulating film

27a: storage electrode 27b: buffer storage pattern

28 dielectric film 29 plate electrode

30 capacitor 31 fourth interlayer insulating film

32: metal wiring

In order to achieve the above object, the present invention provides a semiconductor substrate having a cell region and a peripheral circuit region, the word line and a bit line formed on each region; Forming a first interlayer insulating film over the entire area of the substrate to cover the word line and the bit line; Etching the first interlayer insulating film to form a first trench in the substrate cell region and defining a storage electrode formation region of the capacitor, and forming a second trench in the plate electrode formation region of the capacitor to be in contact with the metal wiring; Forming a storage electrode in contact with the substrate on the first trench surface, and forming a floating buffer storage pattern on the second trench surface; Forming a capacitor by sequentially forming a dielectric film and a plate electrode on the substrate cell region including the storage electrode and the buffer storage pattern; Forming a second interlayer insulating film to cover the capacitor; Etching the second and first interlayer insulating layers to form first contact holes exposing a portion of a plate electrode disposed in the second trench and second contact holes exposing word lines and bit lines of a substrate peripheral circuit area, respectively. step; And forming a metal wiring on the second interlayer insulating layer and contacting the word line and the bit line of the plate electrode and the substrate peripheral circuit region through the first and second contact holes. to provide.

The storage electrode and the buffer storage pattern may be simultaneously formed through deposition of a conductive layer and patterning of the conductive layer, or after the buffer storage pattern is formed, the storage electrode may be formed.

According to the present invention, by forming a trench in the metal wiring formation region to be in contact with the plate electrode, it is possible to prevent the plate electrode of the cell region from being punched due to the step between the cell region and the peripheral circuit region when forming the metal wiring. have.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a transistor including a word line 22 is formed on a semiconductor substrate 21 having a cell region and a peripheral circuit region according to a known process, and then covers the first interlayer insulating layer 23 to cover the transistor. To form. Then, a bit line 24 is formed on the first interlayer insulating film 23, for example, to contact the drain region (not shown) of the transistor, and to cover the bit line 24. 23, a second interlayer insulating film 25 is formed.

Subsequently, after the third interlayer insulating layer 26 is formed on the second interlayer insulating layer 25, portions of the third interlayer insulating layer 26 are selectively etched to form first trenches T1 defining a capacitor formation region. In this case, when the first trenches T1 are formed, the second trenches T2 having the same depth as the first trenches T2 are formed by etching the M1C formation regions to be contacted with the plate electrodes.

Then, after depositing a conductive film for the capacitor electrode on the third interlayer insulating film 26 including the surfaces of the first and second trenches T1 and T2, it is etched and formed on the surface of the first trench T1. A storage electrode 27a is formed, and at the same time, a buffer storage pattern 27b is formed on the surface of the second trench T2 to prevent punching of the plate electrode in subsequent M1C formation.

Here, although not described in detail, the storage electrode 27a may be understood to include a contact plug for the storage electrode formed in the previous process steps. Thus, the storage electrode 27a is in contact with the substrate 1, more precisely, the source region of the substrate, while the buffer storage pattern 27b is in a floating state.

The storage electrode 27a and the buffer storage pattern 27b may be formed through separate processes. In this case, the storage electrode 27a is formed after the storage pattern 27b is formed. When the storage electrode 27a is formed, the conductive electrode for the storage electrode on the buffer storage pattern 27b is removed by a wet or dry etching process.

Referring to FIG. 2B, a dielectric film 28 is deposited on the storage electrode 27a, the buffer storage pattern 27b, and the third interlayer insulating layer 26. Then, after depositing a capacitor electrode conductive film in the form of filling the first trench on the dielectric film 28, the conductive film and the dielectric film is patterned to form a plate electrode 29, through which the capacitor ( 30). In this case, the plate electrode 29 is formed to be disposed on the buffer storage pattern 27b on the surface of the second trench T2.

Referring to FIG. 2C, a fourth interlayer insulating layer 31 is formed on the third interlayer insulating layer 26 to cover the capacitor 30. Then, the predetermined portions of the fourth interlayer insulating layer 31 are selectively etched, so that the plate electrode 29 of the cell region, the word line 22, the bit line 24, and the semiconductor substrate 21 of the peripheral circuit region, respectively. First contact holes C1 and second contact holes C2 exposing the first and second contact holes C2 are formed.

In this case, the height difference between the first contact hole C1 formed in the cell region and the second contact hole C2 formed in the peripheral circuit region is not large, particularly, the cell region in which the first contact hole C1 is formed. In connection with the formation of the buffer storage pattern on the surface of the second trench, the punch in the plate electrode 29 is not generated when the first and second contact holes C1 and C2 are formed.

Referring to FIG. 2D, a wiring metal film, for example, an aluminum film is deposited on the fourth interlayer insulating film to fill the first and second contact holes, and is patterned to contact the plate electrode 29 of the cell region. M1Cs 32 and 33 are formed in contact with the word line 22, the bit line 24 and the substrate 21 in the circuit area, respectively.

Here, the M1C 32 formed in the cell region has a relatively large contact area with the plate electrode 29 since the punch of the plate electrode 29 is not induced in the previous process, thus preventing an increase in resistance. The reliability can be ensured.

As described above, the present invention forms a trench in the M1C formation region of the cell region to be contacted with the plate electrode to make the height of the M1C to be similar to the heights of M1C to be formed in the peripheral circuit region, thereby making the cell region and the surroundings It is possible to prevent the plate electrode of the cell region from being punched out when M1C is formed in the circuit region, thereby increasing the contact area between the M1C and the plate electrode, thereby reducing the contact resistance therebetween, so that the reliability and manufacturing of the device Yield can be improved.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

Providing a semiconductor substrate having a cell region and a peripheral circuit region, wherein a word line and a bit line are formed on each region; Forming a first interlayer insulating film over the entire area of the substrate to cover the word line and the bit line; Etching the first interlayer insulating film to form a first trench in the substrate cell region and defining a storage electrode formation region of the capacitor, and forming a second trench in the plate electrode formation region of the capacitor to be in contact with the metal wiring; Forming a storage electrode in contact with the substrate on the first trench surface, and forming a floating buffer storage pattern on the second trench surface; Forming a capacitor by sequentially forming a dielectric film and a plate electrode on the substrate cell region including the storage electrode and the buffer storage pattern; Forming a second interlayer insulating film to cover the capacitor; Etching the second and first interlayer insulating layers to form first contact holes exposing a portion of a plate electrode disposed in the second trench and second contact holes exposing word lines and bit lines of a substrate peripheral circuit area, respectively. step; And Forming a metal wiring on the second interlayer insulating layer, the metal wiring being in contact with the word line and the bit line of the plate electrode and the substrate peripheral circuit region through the first and second contact holes. Manufacturing method. The method of claim 1, wherein the storage electrode and the buffer storage pattern is A method of manufacturing a semiconductor device, characterized in that formed simultaneously through the deposition of a conductive film and the patterning of the conductive film. The method of claim 1, wherein the storage electrode and the buffer storage pattern is A method of manufacturing a semiconductor device, characterized in that each forming through a separate process. The method of claim 3, wherein the storage electrode and the buffer storage pattern is And forming the storage electrode after the buffer storage pattern is formed.