KR200349229Y1 - Equalization Circuit of Semiconductor Memory - Google Patents

Abstract

The present invention relates to an equalization circuit of a semiconductor memory, and according to the prior art, when the voltage difference between the bit line and the bit line bar is greater than or equal to a predetermined level as the column address is changed, current consumption in bit line equalization is large. When the voltage difference between the line and the bit line bar is less than a predetermined level, the amount of current decreases, which takes a long time for equalization. Accordingly, when the width of the NMOS transistor is widened, a peak current and an operating current increase during equalization. Accordingly, the present invention has been devised to solve the above-mentioned conventional problems. When the voltage is applied to the bit line and the bit line bar, the present invention detects a voltage below the reference voltage level. When the required period is reduced and the high speed operation is performed, and the voltage applied to the bit line and the bit line bar is equal to or higher than the reference voltage level, the predetermined NMOS transistor in the equalization circuit unit is turned off to suppress current consumption.

Description

Equalization Circuit of Semiconductor Memory

The present invention relates to an equalization circuit of a semiconductor memory, and more particularly, to detect a voltage difference between a bit line and a bit line bar, and to control a predetermined transistor in the equalization circuit part to be suitable for low voltage and high speed operation, and to improve reliability of a sense amplifier. Relates to an equalization circuit.

In a general equalization circuit, a local I / O line is precharged and equalized to a predetermined level suitable for sensing by a sense amplifier each time a column address is changed, and the predetermined pre-operation is performed when sensing. A high potential or a low potential is amplified by the sense amplifier based on the charge level to determine the result.

Here, since the column address is changed when new read data is loaded on the local input / output line, the equalization circuit operates for a predetermined time since the local input / output line must be made electrically at the same level as the precharge level. The read data is loaded after performing equalization of the local input / output line.

1 is a schematic view showing a configuration of a general semiconductor memory, as shown therein; first and second memory array units 10 and 20 composed of a plurality of unit cells; A sense amplifier unit 30 for amplifying data, which are weak signals output from the first and second memory array units 10 and 20 to bit lines and bit line bars, to a predetermined level; An equalization circuit section 40 for equalizing the bit line and the bit line bar at a predetermined level; A first access transistor section (50) for controlling data transfer between the first memory array section (10) and the sense amplifier section (30); The second access transistor unit 51 is configured to transfer and control data between the second memory array unit 20 and the equalization circuit unit 40.

2 is an equalization circuit diagram of a conventional semiconductor memory, and as shown therein, a bit line BL and a bit line bar ( ), Each source is connected, and each drain has a ½ supply voltage ( A first and a second NMOS transistors NM1 and NM2 which are electrically controlled according to a precharge control signal PCT applied to each gate; The source and drain are connected to the bit line BL and the bit line bar. ) And a third NMOS transistor NM3 connected to the gate according to the equalization signal EQ1 applied to the gate. The operation of a conventional embodiment configured as described above will be described in detail as follows.

First, in the timing diagram of FIG. 3, when the rasva signal RASB is at high potential, that is, when the bit line pair is disabled, the precharge control signal PCT and the equalization signal EQ1 are applied at high potential. To turn on the first, second, and third NMOS transistors NM1, NM2, and NM3 to turn on the bit line BL and the bit line bar ( Precharge and equalize.

Thereafter, in the timing diagram of FIG. 3, when the rasva signal RASB has a low potential, the equalization signal EQ1 and the precharge control signal PCT are applied at a low potential to generate the first, second, and third signals. The NMOS transistors NM1, NM2, and NM3 are all turned off and the bit line BL is electrically floating in a state necessary for the read operation.

Therefore, when the data of the cell is loaded on the bit line BL by the read operation in the floating state as described above, the sense amplifier unit 30 is driven by the amplification enable signal so that the bit line BL is a memory array. It becomes high potential or low potential according to the data value of the part 10,20.

In addition, when the rasva signal RASB is in the high potential state again in the timing diagram of FIG. 3, the precharge control signal PCT and the equalization signal EQ1 are applied at a high potential to generate the first, second, and second powers. 3 NMOS transistors NM1, NM2, and NM3 are turned on so that the bit line BL and the bit line bar ( Precharge and equalize.

As described above, in the conventional technology, when the voltage difference between the bit line and the bit line bar is higher than a predetermined level as the column address is changed, current consumption is high when the bit line is equalized, while the voltage difference between the bit line and the bit line bar is predetermined. If it is below the level, the amount of current decreases, so much time is required for equalization. Accordingly, if the width of the NMOS transistor is widened, there is a problem in that the peak current and the operating current increase during equalization.

Accordingly, the present invention has been made to solve the above-described problems, and compares the voltage difference between the bit line and the bit line bar to be suitable for low voltage and high speed operation, and turns on or turns on a predetermined NMOS transistor according to the comparison value. An object of the present invention is to provide an equalization circuit of a semiconductor memory that controls turn-off to equalize the bit line and the bit line bar.

1 is a schematic diagram showing a configuration of a general semiconductor memory.

2 is an equalization circuit diagram of a conventional semiconductor memory.

3 is a timing diagram of a conventional semiconductor memory.

4 is an equalization circuit diagram of a semiconductor memory of the present invention.

Figure 5 is a block diagram showing the configuration of the subject innovation equalization control unit.

6 is a timing diagram of a semiconductor memory to which the present invention is applied.

*** Description of the symbols for the main parts of the drawings ***

10, 20: memory array unit 30: sense amplifier unit

40: light circuit section 50,51: access transistor section

70 comparison unit 80 detection unit

90: control part NM1-NM4: NMOS transistor

The configuration of the equalization circuit of the inventive semiconductor memory for achieving the above object comprises an equalization control unit for comparing the potential of the data applied to the bit line and the bit line bar and outputs an equalization signal and a precharge control signal according to the comparison value; ; And an equalization circuit section configured to equalize the bit line and the bit line bar to the same potential by receiving the equalization signal and the precharge control signal.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

4 is an equalization circuit diagram of a semiconductor memory of the present invention. As shown in FIG. 4, a bit line BL and a bit line bar ( ), Each source is connected, and each drain has a ½ supply voltage ( A first and a second NMOS transistors NM1 and NM2 which are electrically controlled according to a precharge control signal PCT applied to each gate; The source and the drain are the bit line BL and the bit line bar, respectively. ) And third and fourth NMOS transistors NM3 and NM4 that are connected and controlled according to the first and second equalization signals EQ1 and EQ2 applied to the respective gates.

FIG. 5 is a block diagram showing the configuration of an equalization control unit of the present invention. As shown therein, a bit line BL and a bit line bar ( A comparator 70 for comparing the voltage levels of and outputting a comparison value accordingly; A detector 80 for comparing and outputting the voltage level of the comparison value output from the comparison unit 70 with the level of the reference voltage VREF; The control unit 90 receives the output signal of the detection unit 80 and outputs the precharge control signal PCT and the first and second equalized signals EQ1 and EQ2. If described in detail the operation and operation of the embodiment according to the following.

First, in the timing diagram of FIG. 6, when the rasva signal RASB is at high potential, that is, when the bit line pair is disabled, the bit line BL and the bit line bar (in the comparison unit 70) are disabled. ) And compares the voltages of the voltages) and outputs the comparison value. The detection unit 80 receives the comparison value and outputs the comparison value to the control unit 90 in comparison with the level of the reference voltage VREF.

In this case, when the comparison value of the comparison unit 70 is equal to or greater than a predetermined level of the reference voltage VREF, the controller 90 outputs the precharge control signal P CT at high potential and reduces the amount of current consumption. Only one of the first and second equalization signals EQ1 and EQ2 is output at high potential to output the first and second NMOS transistors NM1 and NM2 and the third NMOS transistor NM3 or the fourth. The NMOS transistor NM4 is turned on so that the bit line BL and the bit line bar ( Precharge and equalize.

On the other hand, if the comparison value of the comparator 70 is less than or equal to a predetermined level of the reference voltage VREF, the controller 90 may control the first and second equalized signals EQ1 and EQ2 and the precharge control signal. ( P CT) is output at high potential to turn on all of the first to fourth NMOS transistors NM1 to NM4 so that the bit line BL and the bit line bar Precharge and equalize.

In addition, when the rasva signal RASB becomes low potential in the timing diagram of FIG. 6, the controller 90 applies equalization signals EQ1, EQ2 and the precharge control signal PCT to low potential to generate the low potential. The first, second, third, and fourth NMOS transistors NM1 to NM4 are turned off and the bit line BL is electrically floating in a state required for read.

Therefore, when the data of the cell is loaded on the bit line BL in the floating state as described above, the sense amplifier unit 30 is driven by the amplification enable signal, so that the bit line BL is the memory array unit. It becomes high potential or low potential according to the data value of (10) and (20).

Subsequently, when the rasva signal RASB is in the high potential state again in the timing diagram of FIG. 6, the bit line BL and the bit line bar ( By comparing the voltage levels of the circuits, the equalization signals EQ1, EQ2 and the precharge control signal PCT are applied to the equalizing circuit unit, so that the bit line BL and the bit line bar ( Precharge and equalize.

As described in detail above, the present invention detects the voltage applied to the bit line and the bit line bar to turn on a plurality of NMOS transistors in the equalization circuit unit when the voltage is below the reference voltage level, thereby reducing the time required for equalization and performing high speed operation. When the voltage applied to the bit line and the bit line bar is equal to or higher than the reference voltage level, the predetermined NMOS transistor in the equalization circuit unit is turned off to suppress current consumption.

Claims (1)

A comparator for comparing the voltage levels of the bit line and the bit line bar and outputting a comparison value according to the bit line, a detector for comparing and outputting the voltage level and the reference voltage level of the output comparison value of the comparator; An equalization control unit comprising a control unit configured to receive a precharge control signal and output first and second equalization signals; First and second NMOS transistors each having a source connected to the bit line and the bit line bar, a ½ power voltage applied to each drain, and a conduction control applied to the gate by the precharge control signal; Each of the third and fourth NMOS transistors connected to the bit lines and the bit line bars and electrically connected to the gates by applying the first and second equalization signals to the gates, respectively, has the bit lines and the bit line bars at the same potential. An equalization circuit of a semiconductor memory, characterized by comprising an equalizing circuit section for equalizing.