KR100244427B1 - Wide voltage operating pull-up circuit in memory device - Google Patents

Abstract

According to the present invention, in the wide voltage operation memory device, the voltage difference between the bit and bit bar lines is increased to operate in a wide voltage range so that the sense amplifier operates stably. Relates to a pullup circuit.

According to the present invention, the precharge transistors are divided into a plurality of transistors to have different precharge capacities in the low and high voltage regions.

Therefore, since the present invention operates stably in two high and low power supply voltage regions, there is an effect of eliminating the need to install two pull-up circuits that operate at high and low power supplies, respectively.

Description

Pullup Circuit in Wide Voltage Operating Memory Devices

1 is a block diagram of a conventional pull-up circuit.

2 is an embodiment configuration diagram of a pull-up circuit of a wide voltage operating memory device according to the present invention.

* Explanation of symbols for main parts of the name

1: Cell 12: Precharger

13 equalization unit 14 voltage control unit

15: precharging controller M1, M2, M3, M11 to M23: PMOS transistor

The present invention is connected between a positive bit line (BIT) and a sub bit line (/ BIT) in response to a power supply voltage in a wide voltage operation memory device having a wide range of power supply voltages, and is free to the gate end. A pull-up circuit in a wide voltage operating memory device that ensures stable data sensing operation by appropriately performing a charge operation.

1 is a configuration diagram of a conventional pull-up circuit.

As shown in the figure, the conventional pull-up circuit precharges the positive bit line (BIT) and the sub bit line (/ BIT) of the memory cell 1, respectively, in response to the precharge and equalization signals / WYMI. Two PMOS transistors M1 and M2 and another PMOS transistor M3 that equalizes the positive bit line BIT and the sub bit line / BIT. Here, the PMOS transistor M1 is connected between the power supply voltage terminal and the positive bit line BIT, and receives the precharge and equalization signal / WYMI through the gate terminal. The PMOS transistor M3 is connected between the positive bit line BIT and the sub bit line / BIT and receives a precharge and equalization signal / WYMI through a gate terminal.

The operation of the conventional pull-up circuit made as described above will be described next.

During the write cycle of writing data to the memory cell 1, the precharge and equalize signals (/ WYMI) are at the "high" level, so that the PMOS transistors M1, M2, and M3 are all turned off. )do.

In addition, when a read cycle for reading data stored in the memory cell 1 and another column are selected, the precharge and equalization signals / WYMI are at the "low" level, and the PMOS transistors M1, M2, and M3 are selected. ) Are all turned on. Therefore, the positive bit line BIT and the sub bit line / BIT are precharged to the power supply voltage level by the PMOS transistors M1 and M2, and the positive bit line and the bit bit by the PMOS transistor M3. The voltage levels of the lines (/ BIT) are equalized to each other.

Here, the PMOS transistors M1 and M2 are turned on at the time of reading to serve as a voltage source to generate a voltage difference between the positive bit line and the sub bit line / BIT, and a sense amplifier. Senses the voltage difference and reads the data stored in the memory cell (1).

At this time, when the size of the PMOS transistors M1 and M2 is increased, the driving capability of the transistor is improved, so that the positive bit line (BIT) and the sub bit line (/ BIT) can be reliably precharged. Since the voltage difference between the and the bit line (/ BIT) is reduced, the sensing operation during reading becomes difficult.

On the other hand, when the memory device is only for a power supply voltage of a specific size, that is, a memory device using only 5V as the power supply voltage or a memory device using only 3.3V as the power supply voltage, the memory device is only 5V or 3.3V supply voltage. Because it only works, it was possible to construct the circuit by determining the appropriate transistor size through simulation.

However, in recent years, a memory device is required to cover a wide voltage range of 2.7V to 5.7V or more. When using a conventional pull-up circuit, a positive bit line ( The voltage difference between BIT) and sub-bit line (/ BIT) is widened so that the sense amplifier can sense data without any problem.However, in the low power supply area where the supply voltage is 3.3V or less, the size of the pull-up transistor is higher than in the high power supply area. The relatively large voltage difference between the positive bit line (BIT) and the sub bit line (/ BIT) decreases, making it difficult to sense data in the sense amplifier, which may cause the memory device to malfunction.

The present invention is to solve the problems of the prior art as described above, respectively, in the wide voltage operating memory device in response to the power supply voltage in each of the positive bit line (BIT) and the sub bit line (BIT) with different precharge capabilities It is an object of the present invention to provide a pull-up circuit capable of performing a stable data sensing operation by precharging.

In order to achieve the above object, the present invention provides a positive bit line differently at high power voltages having a relatively high power supply voltage and a low power supply voltage having a relatively low power supply voltage in a wide voltage operating memory device having a wide range of power supply voltages. And a pull-up circuit for precharging a sub bit line, the pull-up circuit being connected between a supply terminal for supplying the power voltage and the positive and sub bit lines, the precharge and equalize signals at both the high power supply voltage and the low power supply voltage. First precharge means for precharging the positive bit line and the sub bit line in response to the first and second precharge means; Second precharge means for precharging the positive bit line and the sub bit line only at the high power voltage in response to the precharge and equalize signals; Voltage sensing means connected to a supply terminal for supplying the power supply voltage to sense a voltage level of the power supply voltage and output a voltage sensing signal; And the positive bit line and the sub bit line connected to the positive and sub bit lines by the second precharge means in response to the voltage sensing signal output from the voltage sensing means. A precharge control means for controlling a precharge operation of the precharge control means, wherein the precharge control means is configured to be configured by the second precharge means in response to the voltage sensing signal output from the voltage sensing means during the high power supply voltage. The precharge operation of the positive bit line and the sub bit line is controlled to be possible.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a diagram illustrating an embodiment of a pull-up circuit of a wide voltage operation memory device according to the present invention.

As shown in the figure, the pull-up circuit of the wide voltage operation memory device according to the present invention includes a precharging unit 12, an equalizing unit 13, a voltage control unit 14, and a precharging control unit 15.

The precharging unit 12 is for precharging the positive bit line (BIT) and the sub bit line (/ BIT) of the memory cell 1 in response to the precharge and equalization signal (/ WYMI). PMOS transistors M11, M12, M13, and M14 of any size having capability. Here, one side of the PMOS transistor M11 is connected to the power supply voltage terminal, and a precharge and equalization signal (/ WYMI) is input to the gate terminal, and the PMOS transistor M12 is connected between the power supply voltage terminal and the positive bit line (BIT). Is connected to the gate terminal and receives the precharge and equalization signal (/ WYMI), and the PMOS transistor (M2) is connected between the power supply voltage terminal and the sub bit line (/ BIT), and the gate terminal is precharged and equalized. It receives the signal / WYM1. One side of the PMOS transistor M13 is connected to a power supply voltage terminal, and a precharge and equalization signal (/ WYMI) is input to the gate terminal, and the PMOS transistor M14 is a power supply voltage terminal and a sub bit line (/ BIT). It is connected between and receives a precharge and equalization signal (/ WYMI) at the gate end. Here, in order to precharge the bit line (BIT) and the bit line () / BIT) differently according to the high power supply voltage and the low power supply voltage, the PMOS transistors M1 and M2 of FIG. The sizes of the transistors M11 and M12 and the PMOS transistors M13 and M14 are determined, but, for example, the PMOS transistors M11 and M12 are each composed of 1/2 the size of the PMOS transistor M1 of FIG. The PMOS transistors M13 and M14 are each composed of 1/2 the size of the PMOS transistor M2 of FIG.

Next, the equalizing unit 13 equalizes the positive bit line (BIT) and the sub bit line (/ BIT), and is connected between the other sides of the PMOS transistors M11 and M13 and precharges and equalizes to the gate end. A PMOS transistor M15 that receives a signal WYMI is provided.

Next, the voltage controller 14 outputs a voltage control signal so that the memory device can operate in a desired power supply voltage region in response to a chip selection (/ CS) applied from the outside. A plurality of PMOS diodes M19, M20, M21, M22, and M23 connected in series in the forward direction between the PMOS transistor M18 and the other side of the PMOS transistor M18 and the ground power supply terminal for receiving the selection signal / CS as a gate terminal. And an inverter G11 connected to an anode of the last PMOS diode M23 among the PMOS diodes and outputting a voltage control signal to the precharging controller 14.

Here, the plurality of PMOS diodes M19, M20, M21, M22, and M23 are sized by a designer to select a desired voltage range, and are implemented as a PMOS transistor having a gate and a drain connected to one terminal.

The precharging control unit 15 generates the positive bit line (BIT) and the sub bit line (/ BIT) with different precharging driving capabilities, respectively, in response to the voltage control signal output from the voltage control unit 14. PMOS transistor M16 and PMOS connected between the positive bit line BIT and the other side of the PMOS transistor M11 and receiving a voltage control signal output from the voltage controller 14 to a gate terminal. The PMOS transistor M17 is connected between the other side of the transistor M13 and the sub bit line / BIT and receives a voltage control signal output from the voltage controller 14 to the gate terminal.

On the other hand, the precharge and equalization signals / WYMI are input at the "high" level at the time of writing so that the PMOS transistors M11, M12, M13, and M14 of the precharging unit 12 and the PMOS transistors of the equalizing unit 13 are provided. All of the M15 is turned off and is input at the "low" level when it is not selected and when another column is selected and equalized with the PMOS transistors M11, M12, M13, and M14 of the precharging unit 12. All of the PMOS transistors M15 of the unit 13 are turned on.

The operation of the pull-up circuit of the wide voltage operation memory device according to the present invention configured as described above will be described below.

When the chip select signal / CS is input to select the chip and the precharge and equalize signal / WYMI is input to the "low" level to perform a read operation, the pull-up circuit according to the present invention starts to operate. do.

First, the operation of the pull-up circuit according to the present invention in the high power supply voltage range of the power supply voltage is 5V or more.

The voltage region desired by the designer is selected by the size of each of the PMOS transistors M18, M19, M20, M21, M22, and M23 constituting the voltage controller 14. In the high power voltage region, the inverter of the voltage controller 14 is selected. A voltage control signal of "low" level is output from G11.

Accordingly, the PMOS transistors M16 and M17 of the precharging control section 15 are each turned on by the low voltage control signal of the "low" level, i.e., the same size as the pmos transistors M1 and M2 in the conventional pull-up circuit. The same voltage source capability is used to precharge the positive bit line (BIT) and the sub bit line (/ BIT) with the same capability. That is, since the PMOS transistors M11, M12, M13, and M14 of the precharging unit 12 all precharge the positive bit line BIT and the sub bit line / BIT, the PMOS transistors in the conventional pull-up circuit ( Precharge the positive bit line (BIT) and the sub bit line (/ BIT) with the same precharge capability as M1, M2).

Next, the operation of the pull-up circuit according to the present invention in the low power supply voltage region of the power supply voltage is 3.3V or less.

The voltage region desired by the designer is selected by the size of each PMOS transistor (18.M19, M20, M21, M22, M23) constituting the voltage controller 14. In the low power supply voltage region, the inverter of the voltage controller 14 is selected. A voltage control signal of "high" level is output from G11.

The PMOS transistors M16 and M17 of the precharging control unit 15 are turned off by the "high" level voltage control signal, so that the PMOS transistors M11 and M13 and the equalizing unit 13 of the precharging unit 12 are turned off. PMOS transistor (M15) is turned on but can not affect the precharge of the positive bit line (BIT) and the sub bit line (/ BIT). Therefore, only PMOS transistors M12 and M14 designed to one-half or any size of the conventional PMOS transistors M1 and M2 are turned on to precharge the positive bit line and the bit bit line / BIT. Done.

At this time, if the PMOS transistors M12 and M14 have a size corresponding to 1/2 of the PMOS transistors M1 and M2 of the conventional pull-up circuit, the PMOS transistors M12 and M14 precharge the bit line and the bit line. The effect is reduced by half, and the voltage difference between the positive bit line (BIT) and the sub bit line (/ BIT) is doubled.

Therefore, the precharge capability in the low power supply voltage range is reduced by 1/2, and the voltage difference between the positive bit line (BIT) and the sub bit line (/ BIT) is increased, thereby preventing malfunction of the data detected by the detection amplifier. You can prevent it.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described implementation is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present disclosure, the pull-up circuit according to the present invention precharges the positive bit line and the sub bit line differently for each of the high power supply voltage region and the low power supply voltage region according to the power supply voltage in a wide voltage operating memory device having a wide range of power supply voltage. This provides an excellent effect to perform stable data sensing operation, and also eliminates the need to have two pull-up circuits that precharge the low-input and sub-bit lines for each of the high power and low power supply voltage regions. Can be simplified.

Claims (7)

In a wide voltage operating memory device having a wide range of power supply voltages, a pull-up for precharging the positive bit line and the sub bit line is different from each other at a high power voltage having a relatively high power supply voltage and a low power supply voltage having a relatively low power supply voltage. A circuit, comprising: a supply terminal for supplying the power supply voltage and the positive and negative bit lines, the positive bit line and the negative device in response to a precharge and equalize signal at both the high power supply voltage and the low power supply voltage. First precharge means for precharging the bit lines; Second precharge means for precharging the positive bit line and the sub bit line only at the high power voltage in response to the precharge and equalize signals; Voltage sensing means connected to a supply terminal for supplying the power supply voltage to sense a voltage level of the power supply voltage and output a voltage interception signal; And the positive bit line and the sub bit line connected to the positive and sub bit lines by the second precharge means in response to the voltage sensing signal output from the voltage sensing means. A precharge control means for controlling a precharge operation of the precharge control means, wherein the precharge control means is further configured by the second precharge means in response to the voltage sensing signal output from the voltage sensing means during the high power supply voltage. A pull-up circuit in a wide voltage operating memory device, characterized in that for controlling the precharge operation of the positive bit line and the sub bit line. 2. The display device of claim 1, wherein the first precharge means comprises: a first PMOS transistor connected between a supply terminal for supplying the power voltage and the positive bit line, and receiving the precharge and equalization signals to a gate terminal; And a second PMOS transistor connected between the supply terminal and the sub bit line and receiving the precharge and equalization signals through a gate terminal. 2. The precharge and equalization signal of claim 1, wherein the second precharge means is connected to a supply terminal to which a source terminal supplies the power voltage and a drain terminal is connected to the precharge control means. A first PMOS transistor configured to receive the first PMOS transistor; And a second PMOS transistor having a source terminal connected to the supply terminal, a drain terminal connected to the precharge control means, and receiving the precharge and equalization signals through a gate terminal. Circuit. The third PMOS transistor of claim 3, wherein the precharge control unit is connected between the positive bit line and the drain terminal of the first PMOS transistor, and receives the voltage sensing signal output from the voltage sensing unit to a gate terminal. ; And a fourth PMOS transistor connected between the drain terminal of the second PMOS transistor and the sub bit line and receiving the voltage sensing signal output from the voltage sensing means to a gate terminal. The third and fourth PMOS transistors include: Each of the maintenance units is turned on in response to the voltage sensing signal having a "low" level output from the voltage sensing unit when the high power supply voltage is supplied, and is applied to the drain terminals of the first and second PMOS transistors. And a pre-charge of the sub-bit line. 5. The first and fourth PMOS transistors of claim 4, wherein the third and fourth PMOS transistors are turned off in response to the "high" level voltage sensing signal output from the voltage sensing means when the low power supply voltage is supplied. A pull-up circuit in a wide voltage operating memory device, characterized in that the voltage applied from the drain terminal of the second PMOS transistor is blocked from being transferred to the positive bit line and the sub bit line. 6. The apparatus of claim 4 or 5, further comprising equalizing means for equalizing the positive bit line and the sub bit line precharged through the first and second precharge means at the high power voltage. And the equalizing means includes a fifth PMOS transistor connected between the drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor and receiving the precharge and equalization signals to a gate terminal. Pullup circuit in memory device. The semiconductor device of claim 1, wherein the voltage sensing unit comprises: a first PMOS transistor connected to a supply terminal at which one side supplies a false power supply voltage, and receiving a chip select signal at a gate terminal; And a plurality of second PMOS transistors connected in series diodes in a forward direction between the other side of the first PMOS transistor and a ground power supply terminal, wherein the voltage sensing signal is output from a drain terminal of the second PMOS transistor connected to the ground power supply terminal. A pull-up circuit in a wide voltage operation memory device.