Claims (8)
A first precharge transistor for precharging bits and bit barriers (BIT, / BIT) to different precharging capacities in accordance with a write enable signal / WYMI input in a low voltage region, A second precharge transistor for precharging the bit and bit bar lines BIT and / BIT to different precharging capacitances according to the enable signal / WYMI, and for equalizing the bit and bit bar lines BIT and / A voltage control unit 14 for operating the equalizing unit 13 and a chip selection signal / CS to be input to output a predetermined voltage control signal when the power supply voltage reaches a desired voltage level, And a precharging control unit (15) for controlling the precharging unit (12) to have different precharging capacities according to a voltage control signal output from the precharging unit A pull-up circuit.
The semiconductor memory device according to claim 1, wherein the precharging unit includes a first PMOS transistor having a gate input connected to a source of a power supply and a write enable signal / WYMI input thereto and a drain connected to the precharging control unit, A second PMOS transistor M12 having a source connected to the power supply and having the write enable signal / WYMI as a gate input and a drain connected to the bit line BIT, a second PMOS transistor M12 having a source connected to the power source, A third PMOS transistor M13 having an enable signal / WYMI as a gate input and a drain connected to the precharging control unit 14 and a third PMOS transistor M13 having a source connected to the power source and the write enable signal / , And a fourth PMOS transistor (M14) having a drain connected to the bit line (/ BIT).
3. The method of claim 2, wherein the first and second PMOS transistors (M11, M12) and the third and fourth PMOS transistors (M13, M14) Up circuit of a memory device.
4. The wide-voltage operation memory device according to claim 3, wherein the first and second PMOS transistors M11 and M12 and the third and fourth PMOS transistors M13 and M14 have the same size. .
3. The semiconductor memory according to claim 2, wherein the equalizing unit (13) comprises a fifth PMOS transistor (M15) having drains and sources connected to the drains of the first and third PMOS transistors (M11, M13) Up circuit of the device.
2. The semiconductor memory device according to claim 1, wherein the voltage controller comprises: a first PMOS transistor having a source connected to a power source and having the chip select signal / CS as a gate input; And a plurality of PMOS diodes M19, M20, M21, M22 and M23 connected in series in a forward direction to the ground, and an end of the last PMOS diode M23 among the plurality of PMOS diodes, And an inverter (G11) for outputting the voltage to the charging control unit (14).
7. The pull-up circuit of a wide voltage operation memory according to claim 6, wherein the plurality of PMOS diodes (M19, M20, M21, M22, M23) are sized to select a desired voltage region.
The precharge controller (15) according to claim 2, wherein the precharging controller (15) uses a voltage control signal output from the voltage controller (14) as a gate input and drains and drains the drains of the first and second PMOS transistors A fifth PMOS transistor M16 having a source connected thereto and a voltage control signal output from the voltage control unit 14 as a gate input and a drain and a source connected to the drains of the third and fourth PMOS transistors M13 and M14 And a connected sixth PMOS transistor (M17).
※ Note: It is disclosed by the contents of the first application.