KR100403318B1 - Power supply control circuit for a sense amplifier - Google Patents

Abstract

Compares the voltage difference between dummy bit line pair and senses it when it is over a certain voltage, and outputs sense amplifier power supply control signal so that when the external voltage rises rapidly due to noise or uses high external voltage, rto node In order to provide a sense amplifier power supply control circuit capable of stably operating the sense amplifier even when the voltage of the non-ideally rises, the sensing unit for sensing the point of time to switch the power supply voltage of the sense amplifier from the external voltage to the internal voltage. And a first current mirror circuit for sensing a voltage difference of a bit line pair as a comparison input when a predetermined voltage difference is generated or a voltage input opposite to the comparison input as a comparison input. A second current mirror circuit and an output of the first current mirror circuit or the second current mirror circuit. Provided with a voltage difference detection unit detecting an output from the sensing results that constitute a sense.

Description

Sense amplifier power supply control circuit {POWER SUPPLY CONTROL CIRCUIT FOR A SENSE AMPLIFIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier power supply control circuit of a semiconductor memory device. In particular, the present invention relates to a switching point of a power supply voltage (RTO voltage signal) supplied to a sense amplifier by using a voltage difference of a dummy bit line pair. It relates to a circuit that can be controlled.

Hereinafter, the operation of the conventional sense amplifier will be described using a shared bit line type cross coupled sense amplifier of FIG. 1.

First, during the precharge period, the bit line equalizer signal blpz is applied to turn on the NMOSs N1 and N2 so that the bit line pair is precharged with the precharge voltage Vblp and the half Vcc precharge type. Precharged.

Next, after the bit line is selected, the data voltage stored in the cell is charged and shared through the bit line BIT_LINE according to the bootstrapping of the word line, and the voltage of the bit line is predetermined by the charge sharing. When changed by the level of, the bit line sense amplifier senses and operates to amplify the voltage of the predetermined level to the Vcc level.

Then, the column select signal Yi is input to enable the NMOSs N6 and N7, so that the amplified data is output through the output lines lbdx and lbdz.

The rto and sx terminals for supplying power to the sense amplifier are connected to the sans amplifier driver circuit shown in FIG. Referring to FIG. 2, the sx terminal is connected to the voltage Vss by the sense amplifier enable signal sxez. The rto terminal is connected to an external voltage Vext or an internal voltage Vdd_core by an external voltage application signal RTOext_b and an internal voltage application signal RTOint_b, respectively, to supply power to the sense amplifier. The RTO voltage is high during the bit line pair, considering the efficient high-speed operation of the sense amplifier and the tRCD (minimum time required from the time the low active command is input to the read / write command). Initially, the external voltage application signal RTOext_b is enabled and supplied to the external voltage Vext so that the voltage is quickly increased to the Vcc level. When the voltage is higher than a predetermined level, the internal voltage application signal RTOint_b is internally applied. It is supplied with the voltage Vdd_core.

Providing the strobe signals RTOext_b, RTOint_b, and sxez for supplying the internal voltage Vdd_core or the external voltage Vext according to this detection level is by the sense amplifier power supply control circuit of FIG.

As shown in FIG. 3, the conventional sense amplifier power supply control circuit compares the internal voltage Vdd_core connected to the NMOS N31 and the voltage of the rto node applied to the NMOS N30 so that the two values have a predetermined difference. A sensing unit 10 configured to sense a time when the sensor is opened, a sense amplifier enable signal sxez outputting a sense amplifier enable signal sxez based on a sense amplifier enable control signal sgz and a bit line equalizer signal blpz Based on the sensing result output from the signal signal generation unit 30 and the sensing unit 10, the external voltage application signal output unit 20 and the sensing unit 10 output the external voltage application signal RTOext_b. An internal voltage application signal output unit 40 for outputting the internal voltage application signal RTOint_b based on the result and the sense amplifier enable signal output from the sense amplifier enable signal generator 30, and a sense amplifier enable signal ( sxez) delayed output Includes an enable signal output portion 50, a sense amplifier.

The sense amplifier enable signal generator 30 bootstraps the word line so that the bit line equalizer signal blpz is " low ", and the sense amplifier enable control signal sgz is " high ". In this case, since the voltage of the rto node is initially lower than the internal voltage Vdd_core, the external voltage application signal RTOext_b is "low", and the internal voltage application signal RTOint_b and the sense amplifier enable signal sxez are "high". ", And outputs to the sense amplifier driver circuit, whereby the sense amplifier driver circuit of FIG. 2 supplies the voltage of the rto node to the external voltage Vext. Thereafter, when the voltage of the rto node rises to reach the detection level of FIG. 6, the internal voltage application signal RTOint_b becomes "low", the external voltage application signal RTOext_b becomes "high", and the power supply is supplied with an external voltage. Allow Vext to switch to the internal voltage Vdd_core.

Fig. 6A shows the timing of switching the power supply voltage by such a voltage level detection. As shown in FIG. 6A, the internal voltage Vdd_core is provided as a comparison voltage of the sensing unit 10, and amplifies the bit line pair voltage difference to the Vcc level, thereby maintaining it.

However, when the external voltage Vcc rises sharply due to noise or the like or when a high external voltage is used, the voltage of the rto node may rise to the detection level before the appropriate switching point as shown in FIG.

In this case, without sufficient amplification, the sense amplifier power supply voltage is switched from the external voltage Vext to the internal voltage Vdd_core, so that the amplification of the bit line pair voltage to a high voltage of Vcc level is not the external voltage Vext_core. As a result, the sense amplifier amplification operation is delayed or does not rise to the Vcc level reliably, and a defect may occur when the insufficient value is read next, resulting in poor tRCD performance.

An object of the present invention for solving the above problems is to sense the voltage difference of the dummy bit line pair, and when the voltage difference is more than a certain voltage by switching the sense amplifier power supply from the external voltage to the internal voltage, the external voltage is noise It is possible to provide a sense amplifier power supply control circuit that operates stably at a high voltage level without causing an error even if the voltage of the rto node rises abnormally.

1 is a circuit diagram showing an embodiment of a conventional sense amplifier.

FIG. 2 is a circuit diagram illustrating a driver circuit of the sense amplifier of FIG. 1. FIG.

3 is a circuit diagram of a conventional sense amplifier power supply control circuit for outputting a signal for controlling the sense amplifier driver circuit of FIG.

4 is a circuit diagram illustrating a sensing unit of a sense amplifier power supply control circuit according to an embodiment of the present invention.

5 is a circuit diagram illustrating a sensing unit of a sense amplifier power supply control circuit according to an embodiment of the present invention.

6 is a sense amplifier power supply voltage operation waveform diagram comparing the switching time of the power supply of the sense amplifier power supply control circuit according to the prior art and the present invention.

The sense amplifier power supply control circuit according to the present invention is a dummy bit line in a sense amplifier power supply control circuit of a semiconductor memory device for outputting a signal for supplying an external voltage to a sense amplifier and a signal for supplying an internal voltage. A first voltage comparing unit configured to change the first logic value by outputting the first bit line voltage of the pair and a predetermined reference voltage as a comparison input and sensing when the compared voltage difference is greater than a desired level; A second voltage comparison unit configured to change the second logic value by outputting the second bit line voltage of the dummy bit line pair and a predetermined reference voltage as a comparison input, and to sense when the compared voltage difference is greater than or equal to a desired level; And a voltage difference outputting a signal indicating that a voltage difference of the dummy bit line pair reaches a level at which a power supply of a sense amplifier is switched from the external voltage to the internal voltage based on the first logic value or the second logic value. The detection unit is provided.

The first voltage comparator may include one or more diodes for reducing the first bit line voltage.

The second voltage comparator may include one or more diodes for reducing the second bit line voltage.

The predetermined reference voltage of the first voltage comparator may be a voltage of the second bit line.

The predetermined reference voltage of the second voltage comparator may be a voltage of the first bit line.

The predetermined reference voltage of the first voltage comparator may be a bit line precharge voltage.

The predetermined reference voltage of the second voltage comparator may be a bit line precharge voltage.

That is, the present invention configures the sensing unit 10 to sense the voltage of the dummy bit line pair in the conventional sense amplifier power supply control circuit of FIG. 3 so that the voltage difference between the sensed bit line pair becomes a predetermined level or more. The power supply voltage of the sense amplifier is configured to be converted from the external voltage to the internal voltage.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 and 5.

<First Embodiment>

4 illustrates a sensing unit 10 of a sense amplifier power supply control circuit according to an embodiment of the present invention. As illustrated, the sensing unit 10 according to the present invention includes a first current mirror circuit 12, a second current mirror circuit 14, and a voltage difference detector 16. The / BIT_LINE voltage of the dummy bit line is input to the NMOS N50 as the input of the first current mirror circuit 12, and the BIT_LINE voltage is input to the NMOS N51 (hereinafter, the BIT_LINE voltage and the / BIT_LINE voltage are referred to as dummy bit line voltages). ). The BIT_LINE voltage input to the NMOS N51 is reduced in voltage by the MOS diodes N52 and N53 and input to the first current mirror circuit 12. This is to detect a certain voltage difference as much as the diodes N52 and N53 occurs.

Here, the diode may be added or removed depending on how many V the detection level is, and the detection level may be determined depending on the elapsed time tRCD when the voltage difference of the bit line pair becomes more than V.

For example, suppose that the voltage drop by one MOS diode is 0.7 V and the elapsed time of tRCD is when the voltage difference of the bit line pair is 1.4 V or more. As shown in FIG. 4, two diodes may be included.

That is, during the precharge, the voltages of the bit line pairs BIT_LINE and / BIT_LINE are kept the same, and the output of the first current mirror circuit is reduced because the input of the NMOS N51 is reduced by the diodes N52 and N53. The output of the current mirror circuit 12 is " low ". The voltage on the bit line is then raised or decreased in accordance with the data of the cell after the word line is bootstrapping. If the data of "1" is stored in the cell on the bit line (BIT_LINE) side, the bit line (/ BIT_LINE) voltage maintains the precharge voltage and the bit line (BIT_LINE) voltage is charge-shared to have a slightly higher voltage. will be. However, since the voltage is reduced by the diodes N52 and N53 and input to the first current mirror circuit 12, the voltage of the NMOS N51 becomes higher than the voltage of the NMOS N50 and still remains "low".

On the other hand, in the lower second current mirror circuit 14, the bit line voltage BIT_LINE is applied to the NMOS N55 and the bit line voltage / BIT_LINE is connected to the NMOS N56 as opposed to the first current mirror circuit 12. The voltage is reduced by (N58, N59) and input, respectively, and the output of the bit line (BIT_LINE) is always higher than the voltage of the bit line (/ BIT_LINE) so that the output is kept " low ".

When the charge sharing is performed, a slight voltage difference occurs between the bit line pairs, and the sense amplifier operates to gradually amplify the voltage difference between the bit line pairs to a Vcc level, and when the voltage difference spreads above a predetermined voltage indicated by the diodes N58 and N59. The gate voltage of the NMOS N51 of the first current mirror circuit 12 becomes larger than the gate voltage of the NMOS N50, so that the output of the first current mirror circuit 12 becomes "high".

On the contrary, when there is data of "0" in the cell, the bit line / BIT_LINE rises and the output of the second current mirror circuit 14 below becomes "high".

When a signal of "high" is output from any current mirror circuit, the voltage difference detection unit 16 outputs a signal indicating this to the external voltage application signal output unit 20 and the internal voltage application signal output unit 40, thereby By outputting the voltage application signal RTOext_b to "high" and the internal voltage application signal RTOint_b to "low", the RTO voltage of the sense amplifier is switched from the external voltage Vext to the internal voltage Vdd_core.

Application of the bit line equalizer signal blpz to the NMOS N54 and N60 connects the gate nodes of the NMOS N54 and N60 to ground voltages when the bit line is precharged by the bit line equalizer signal blpz. This is to perform correct operation during the next operation by discharging.

Second Embodiment

FIG. 5 illustrates a sensing unit according to still another embodiment of the present invention, in which a comparison target of each of the first and second current mirror circuits is not a dual voltage of a dummy bit line pair, but the first current mirror circuit 12 '. Denotes the voltage of the precharge voltage Vblp and the dummy bit line BIT_LINE, and the second current mirror circuit 14 'denotes the voltage of the precharge voltage Vplp and the dummy bit line / BIT_LINE. Characterized in that each of the comparison input.

By using the precharge voltage Vblp as the predetermined reference voltage in this way, the number of diodes representing a constant voltage can be adjusted.

Third Embodiment

The reference voltage may be a constant voltage different from the precharge voltage. By doing so, the constant voltage level for determining the RTO voltage switching point can be adjusted to the reference voltages applied to the two current mirror circuits instead of the diodes, so that the voltage adjustment can be made more accurate.

The detailed configuration of applying such a constant reference voltage is not shown because it is obvious to those skilled in the art.

Alternatively, the first current mirror circuit 12 or the second current mirror circuit 14 may be configured by mixing the first to third embodiments. Therefore, the detection level may be set differently for the bit line BIT_LINE and the bit line / BIT_LINE.

According to the present invention, when the voltage of the conventional rto node is detected and a sense amplifier power supply control signal is generated, the power supply switching time of the sense amplifier can be controlled more stably, thereby preventing malfunction of the sense amplifier. It can operate stably even at high Vcc.

Claims (7)

In the sense amplifier power supply control circuit of a semiconductor memory device for outputting a signal for supplying an external voltage to the sense amplifier and a signal for supplying an internal voltage, A first voltage comparing unit configured to change the first logic value by outputting the first bit line voltage of the dummy bit line pair and the predetermined reference voltage as a comparison input, and to sense when the compared voltage difference is greater than or equal to a desired level; A second voltage comparison unit configured to change the second logic value by outputting the second bit line voltage of the dummy bit line pair and a predetermined reference voltage as a comparison input, and to sense when the compared voltage difference is greater than or equal to a desired level; And A voltage difference detector configured to output a signal indicating that a voltage difference of the dummy bit line pair reaches a level at which a power supply of a sense amplifier is switched from the external voltage to the internal voltage based on the first logic value or the second logic value Sense amplifier power supply control circuit comprising: a. The method of claim 1, And the first voltage comparator comprises one or more diodes for reducing the first bit line voltage. The method of claim 1, And the second voltage comparator includes at least one diode for reducing the voltage of the second bit line. The method of claim 1, And the predetermined reference voltage of the first voltage comparator is a voltage of the second bit line. The method of claim 1, And the predetermined reference voltage of the second voltage comparator is a voltage of the first bit line. The method of claim 1, And the predetermined reference voltage of the first voltage comparator is a bit line precharge voltage. The method of claim 1, And the predetermined reference voltage of the second voltage comparator is a bit line precharge voltage.