KR100192586B1 - Current sense amplifier of semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a sense amplifier of a semiconductor memory device.

2. The technical problem the invention is trying to solve:

The present invention compares the level of the precharge signal VBL with the level of the reference voltage Vrefa according to the node level change of the driven drive control signal? Lapg to gradually reduce the peak value (level difference) to enable stable sensing operation. A sense amplifier control circuit of a semiconductor memory device is provided.

3. Summary of the Solution of the Invention:

A semiconductor memory device having a sense amplifier which is operated by a predetermined control signal to apply a predetermined voltage to a memory cell, comprising: sense amplifier driving means driven by input of a control voltage to drive the sense amplifier; A level for selectively generating first and second trigger signals by comparing the sense amplifier driving signal with a preset reference voltage in response to an input of a signal, and outputting a bias control signal corresponding to the first and second trigger signals; An output is connected to a control means, a power supply voltage sensing means for detecting a level of an external power supply voltage by comparing the external power supply voltage with a voltage of a predetermined defect level, and an output is connected to a control voltage terminal of the sense amplifier driving means. The control voltage is kept constant in response to the input of the first and second trigger signals and the bias control signal. In response to the detection signal, a sense amplifier driving control means for amplifying the control voltage to charge up the voltage supplied to the memory cell at a high speed, and an input terminal and an input terminal of the power supply voltage sensing means are commonly connected to respond to the activation signal. A delay circuit for outputting a signal delayed by a predetermined time and one input terminal are connected to an output terminal of the delay circuit, and a type force terminal is commonly connected to an output terminal of the level control means and an input terminal of the sense amplifier driving control means to temporarily store a predetermined signal. And a latch unit for outputting.

4. Important uses of the invention:

The present invention is suitably used for a sense amplifier of a semiconductor memory device.

Description

Current Sense Amplifiers in Semiconductor Memory Devices

1 is a block diagram illustrating a sense amplifier and a memory cell array of a semiconductor memory device according to an embodiment of the prior art.

2 is a view showing a relationship between the reference voltage Vrefa and the external power supply voltage EVCC of FIG.

3 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to an embodiment of the prior art.

4 is an operation timing diagram of FIG. 1, assuming cell data connected to B / L is in a logic high state.

5 is a detailed circuit diagram of an internal power supply voltage generator according to an embodiment of the prior art.

6 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to an embodiment of the present invention.

7 is an operation timing diagram of FIG.

8 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to another embodiment of the present invention.

9 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to another embodiment of the present invention.

FIG. 10 is a block diagram showing a connection between a P-S / A control circuit and a sub memory array when using an internal power supply voltage (VCCA) for an array according to another embodiment of the present invention.

11 is a detailed circuit diagram of an internal power supply voltage generator according to an embodiment of the present invention.

The present invention relates to a semiconductor memory device, and more particularly to a sense amplifier control circuit of a semiconductor memory device.

In general, as semiconductor devices are highly integrated, the area occupied by one transistor is reduced by that amount, and the size of the transistor is becoming smaller and smaller, and the thickness of the oxide is becoming thinner. Of course, a sense amplifier composed of transistors (hereinafter referred to as S / A) also becomes small. Therefore, when the external power supply voltage is applied to the reduced S / A and the memory cell as it is, the peak current increases during the sensing operation, and the transistor malfunctions due to power noise. In addition, it is well known in the art that a high power supply voltage level shortens the life of a memory cell, thereby making it impossible to perform a stable operation as a memory device. Therefore, in the highly integrated semiconductor memory device, a method of applying a voltage lower than the external power supply voltage applied to the outside of the chip to the memory cell has become common. This technique uses an internal power supply voltage generator which inputs an external power supply voltage and clamps it to a predetermined level lower than the external power supply voltage. 1 is a block diagram illustrating a sense amplifier and a memory cell array of a semiconductor memory device according to an embodiment of the prior art. Referring to FIG. 1, the configuration includes a P-Type Sense Amplifier (hereinafter referred to as PS / A) control circuit 100, a PS / A Driver 108, and an N-Type Sense Amplifier. It is composed of a driver 110, a precharge circuit 109, a memory cell array and an S / A circuit 107. The P-S / A control circuit 100 includes a comparator 101, a trigger circuit 102, a P-S / A driver control circuit 103, a bias circuit 104, a comparator enable circuit 105, and a level shifter circuit 106. Here, the voltage level (logical high level) charged in the memory cell is represented by the reference voltage Vrefa. In addition, the sensing enable signal? S is enabled in a logic high state after a predetermined time when the row address strobe signal RASB is activated in a logic low state. The comparator 101 outputs a comparison output signal? Com by comparing the reference voltage Vrefa and the voltage level of the control signal LA when the sensing enable signal? S is activated to a logic high. When the level of the control signal LA is higher than the reference voltage Vrefa level, the level of the comparison output signal øcom is at a logic high state. When the level of the control signal LA is lower than the reference voltage Vrefa level, the level of the comparison output signal øcom is at a logic low state. Becomes The level shift circuit 106 inputs the sensing enable signal? S as an input and outputs the level shifted signal? SS. This circuit uses the power of the sensing enable signal øS generator (not shown) using an internal power supply voltage (hereinafter referred to as IVCC), and the power of the PS / A control circuit 100 is referred to as an external power supply voltage (hereinafter referred to as EVCC). It is used to convert the level (IVCC) of the sensing enable signal? S to the EVCC level. The comparator enable circuit 105 is a circuit for precharging the comparison output signal? S to a logic high level when the sensing enable signal? S is in a logic low state. This circuit inputs the level shifted signal? SS, and its output terminal is connected to the node of the comparison output signal? S. Although the internal structure of the trigger circuit 102 is not shown, the configuration is composed of an inverter, and the comparison output signal? S is input and outputs the trigger signal? Tri. The bias circuit 104 outputs the bias signal? Bi with the trigger signal? Tri as an input, which is used to reduce the sensing peak current.When the trigger signal? Tri is in a logic low state, the bias signal? Bi is at the IVCC level, and the trigger signal? Tri is logic. If the state is high, the bias signal? Bi has a voltage level of | Vtn | + α. The P-S / A driver control circuit 103 inputs the trigger signal? Tri and the bias signal? Bi to output the driven driver enable signal? Lapg. If trigger signal øtri is logic low, then the enable driver enable signal ølapg is at EVCC level. If trigger signal øtri is logic high, then the enable driver enable signal ølapg is EVCC-| Vtp | has a level of α. Referring to the sense amplifier control circuit 100 as a whole, if the sensing enable signal? S is enabled in a logic high state and the voltage level of the control signal LA is lower than the level of the reference voltage Vrefa, the driver driver enable signal? Lapg is the EVCC level. Becomes The PS / A driver 108 consists of a PMOS transistor Q1 so that the source, gate and drain are connected to EVCC, ølapg, and LA nodes, respectively, and the driver enable signal ølapg is EVCC. At the level, PMOS transistor Q1 is turned off and the level of the driver enable signal ølapg is set to EVCC-| Vtp | At α, the PMOS transistor Q1 is turned on to supply charge to the LA node. N-S / A driver 110 is composed of NMOS transistor Q2. The source, gate, and drain of the NMOS transistor Q2 are connected to ground voltages VSS,? Lapg, and LAB, respectively. Therefore, the NMOS transistor Q2 discharges the LAB to the ground voltage level when the level of the N-type driver enable signal? Lang is logic high after the activation of the row address strobe signal RASB. The precharge circuit 109 precharges LA and LAB. The precharge circuit 109 turns on the NMOS transistors Q3, Q4, and Q5 when the low address strobe signal RASB is in the precharge state, that is, the logic high state. When pre-charged LAB to VBL level (1 / 2Vrefa level) and low address strobe signal RASB is activated in a logic low state, equalization control signal øEQ transitions to logic low, turning on the EnMOS transistors Q3, Q4, and Q5. Turn it off. In the memory cell array and the sense amplifier 107, a plurality of bit lines (hereinafter referred to as B / L) and complementary bit lines (hereinafter referred to as B / LB) are present in one memory cell array. Although / L is a plurality of memory cell arrays are connected, only a pair of B / L and B / LB and two word lines (hereinafter referred to as W / L) is shown. The memory cell transistor Q6 composed of the NMOS transistor and the cell capacitor C1 show one memory cell, and the memory cell transistor Q7 composed of the ENMOS transistor and the cell capacitor C2 represent another memory connected to another word line. The cell is shown. The B / L equalization transistors Q8, Q9, and Q10 perform the equalization of the B / L and B / LB to the VBL level by making the equalization control signal øEQ become the logic high state when the low address strobe signal RASB is precharged. The equalization stops when the signal RASB is activated. P-S / A consists of the PMOS transistors Q11 and Q12, and N-S / A consists of the NMOS transistors Q13 and Q14. The B / L, B / LB and the input / output lines I / O and I / OB are electrically connected by the column select gates Q15 and Q16, and the column select line CSL is connected to the gates of the column select gates Q15 and Q16. Since such a memory cell array is a conventionally known configuration, the detailed description of the PA is omitted.

FIG. 2 is a diagram illustrating a relationship between the reference voltage Vrefa and the external power supply voltage EVCC of FIG. 1. Referring to FIG. 2, the reference voltage Vrefa is clamped to a substantially constant level when the external power supply voltage EVCC has a value equal to or greater than a predetermined voltage level. The reason why the reference voltage Vrefa supplied to the memory cell is affected by the external power supply voltage EVCC is that the output of the internal power supply voltage generator (not shown) that generates the internal power supply voltage IVCC by the input of the external power supply voltage EVCC is not shown. Because it uses.

3 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to an embodiment of the prior art. The same reference numerals are used in FIG. 1 for clarity. In addition, the components having the same function in the drawings to be described later use the same reference numerals. Referring to FIG. 3, comparator 101 is composed of PMOS transistors Q17, Q18 and enMOS transistors Q19, Q20, Q21. When the sensing enable signal? S is enabled in a logic high state, the voltage levels of LA and Vrefa are reduced. Compare and output the comparison output signal øcom. The level shift circuit 106 outputs the signal? SS level-shifted to the EVCC level when the sensing enable signal? S is enabled in the logic high state (IVCC level state). The comparator enable circuit 105 precharges the node carrying the level shifted signal? Com to the EVCC level when the sensing enable signal? S is in a logic low state. The trigger circuit 102 is an inverter composed of a PMOS transistor Q23 and an NMOS transistor Q24, and an input terminal and an output terminal are connected to a node of øcom and a node of øtri, respectively. The bias circuit 104 consists of a PMOS transistor Q25 and an enMOS transistors Q26 and Q27. When the trigger signal øtri is enabled from a logic low state to a logic high state, the bias signal øbi, which is an output, is set at | Vtn | It serves to level down to a level of + α. Thus, this is to reduce the peak value of the sensing current. The P-S / A driver control circuit 103 is composed of PMOS transistors Q28, Q31, and Q32 and enMOS transistors Q29 and Q30, and outputs a signal? Lapg by inputting a trigger signal? Tri and a bias signal? Bi. As described above, the signal? Lapg is an EVCC level when the trigger signal? Tri is in a logic low state, and the ground voltage VSS level at the EVCC level through the transistors Q31, Q32, Q29, and Q30 sequentially when the trigger signal? Tri is in a logic high state. Current path is formed and the EVCC-| Vtp | has a level of α. The P-S / A driver 108 is composed of a PMOS transistor 108. The operation is as described in FIG.

FIG. 4 is an operation timing diagram of FIG. 1 assuming that cell data connected to B / L is in a logic high state. Referring to FIG. 4, when the low address strobe signal RASB is in a logic high state, each of the lines B / L, B / LB, LA, and LAB is all at 1 / 2.Vrefa level, which is a precharge signal VBL level. The signal? Lapg is precharged to the EVCC level, the equalization control signal? EQ to the IVCC level, and the signals? Lang and W / L are precharged to OV. Subsequently, when the low address strobe signal RASB is activated to logic low, the equalization control signal øEQ is disabled to logic low, and when W / L is enabled to a voltage level of IVCC + α, charge sharing is performed. By this, B / L increases to a level of 1/2 · Vrefa + α. Therefore, when the signal? Lang is enabled at the logic high level after charge sharing, the node of the LAB, which has been precharged to 1/2 · Vrefa level, transitions to OV when the EnMOS transistor Q2 in FIG. 1 is turned on. Therefore, N-S / A of FIG. 1 operates to transition B / LB to OV. If the sensing enable signal øS transitions to a logic high state after the signal ølang is enabled, the signal ølapg goes to EVCC-| Vtp | -The PMOS transistor Q1 of FIG. 1 is turned on to supply charge to the node of LA, thereby gradually increasing the voltage level of LA. As the voltage level of LA gradually increases, the P-S / A PMOS transistors Q11 and Q12 of FIG. 1 operate to gradually increase the voltage level of B / L. When the level of LA rises to the Vrefa level, the comparison output signal? Com transitions to the logic high level,? Lapg transitions to the EVCC level, and the PMOS transistor Q1 is turned off. Even after the PMOS transistor Q1 is turned off, the charge on the node of the LA is transferred to the B / L, so the voltage level of the LA is lowered by a predetermined level. At this time, when the voltage level of LA becomes lower than the Vrefa level, the comparison output signal øcom, which is the output of the comparator, becomes a logic low state, and ølapg becomes EVCC-| Vtp | It is lowered by the level of -α to operate the PMOS transistor Q1. Therefore, as PMOS transistor Q1 operates, the node and B / L of LA become high by Vrefa + DELTA V, which is higher than the desired level. If the voltage level of B / L is high, it takes much time to invert the voltages of B / L and B / LB by I / O and I / OB lines during write. ) Means that the characteristics of the deterioration. In addition, when the B / L level is high, more time is required to precharge the low address strobe signal RASB to precharge the B / L to the level of the precharge signal VBL (1/2 · Vrefa level). Done. This means that the low address strobe signal RASB precharge time tRP is long. Therefore, as the signal? Lapg changes, the level of the precharge signal VBL becomes larger than the level of Vrefa, and the voltage level peak portion on the node of LA becomes higher than a predetermined predetermined level, resulting in unstable write operation. There is a problem that the precharge time of / L becomes long.

5 is a detailed circuit diagram of an internal power supply voltage generator according to an embodiment of the prior art. Referring to FIG. 5, the configuration includes an active internal power supply voltage generator 402, an active internal power supply voltage driver Q401, a standby internal power supply voltage generator 401, and a standby internal power supply voltage driver Q400. The configuration and operation of the active internal power supply voltage generator 402 is the same as the configuration and operation of FIG. 3 described above, except that the internal power supply voltage VCCA is applied instead of the signal LA of FIG. The standby internal power supply voltage generator 401 is configured as a differential amplifier including PMOS transistors Q500 and Q501 and enMOS transistors Q502 and Q503, and outputs a signal lang_s using the reference voltage Vrefa and the internal power supply voltage VCCA as inputs. The standby internal power supply voltage driver Q400 is a PMOS transistor, and a source, a gate, and a drain are connected to terminals of EVCC, lapg_s, and VCCA, respectively. If the reference voltage Vrefa is higher than the internal power supply voltage VCCA, the signal lapg_s becomes a logic low level, thereby turning on the standby internal power supply voltage driver Q400 to supply charge to the internal power supply voltage VCCA at the EVCC, and the reference voltage Vrefa supplies the internal power supply. If the level is lower than the voltage VCCA, the signal lapg_s goes to a logic high level to turn off the standby internal power supply voltage driver Q400. In other words, the standby internal power supply voltage generator 401 and the standby internal power supply voltage driver Q400 maintain a voltage level of the internal power supply voltage VCCA at a level of a predetermined reference voltage Vrefa. In general, the standby internal power supply voltage generator 401 and the standby internal power supply voltage driver Q400 operate while the low address strobe signal RASB is precharged, increasing the standby current. Therefore, in order to reduce the standby current, the standby internal power supply voltage generator 401 and the standby internal power supply voltage driver Q400 are designed to be very small. When the low address strobe signal RASB is activated, a large amount of charge is consumed by the internal power supply voltage VCCA, so that the small standby internal power supply voltage generator 401 and the standby internal power supply voltage driver Q400 maintain stable voltage levels of the internal power supply voltage VCCA. Therefore, the large active internal power supply voltage generator 402 and the active internal power supply voltage driver Q401 are operated to supply a large amount of charge to the internal power supply voltage VCCA when the low address strobe signal RASB is activated. When the active internal power supply voltage generator 402 and the active internal power supply voltage driver Q401 are operated when the low address strobe signal RASB is activated, overshooting occurs in the internal power supply voltage VCCA as shown in FIG. have.

Accordingly, an object of the present invention is to compare the level of the precharge signal VBL with the level of the reference voltage Vrefa and gradually reduce the peak value (level difference) according to the node level change of the driven drive control signal? Lapg, thereby achieving stable sensing operation. The present invention provides a sense amplifier control circuit of a semiconductor memory device.

Another object of the present invention is to provide a sense amplifier control circuit of a semiconductor memory device which ensures stable sensing characteristics of the semiconductor memory device by preventing overshooting of the sensing node LA by a predetermined voltage difference or more during sensing. .

According to the technical idea of the present invention for achieving the above object, in the semiconductor memory device having a sense amplifier which is operated by a predetermined control signal to apply a predetermined voltage to the memory cell, is driven to the input of the control voltage A sense amplifier driving means for driving a sense amplifier, and in response to an input of an activation signal, comparing the sense amplifier driving signal with a preset reference voltage to selectively generate first and second trigger signals, and generating the first and second trigger signals. Level control means for outputting a bias control signal corresponding to a trigger signal, power supply voltage sensing means for detecting a level of an external power supply voltage by comparing the external power supply voltage with a voltage of a predetermined defect level, and the sense amplifier driving means. An output is connected to the control voltage terminal, and is selectively input to the first and second trigger signals and the input of the bias control signal. In response to the control voltage being kept constant and amplifying the control voltage in response to the level detection signal to sense up the voltage supplied to the memory cell at high speed; and an input terminal of the power supply voltage sensing means. And an input terminal are commonly connected to output a delayed signal for a predetermined time in response to the activation signal, and an input terminal is connected to an output terminal of the delay circuit, and is connected to an output terminal of the level control means and an input terminal of the sense amplifier driving control means. The type force stage is connected in common and has a latch portion for temporarily storing and outputting a predetermined signal.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

6 is a detailed circuit diagram of a P-S / 4 control circuit and a P-S / A driver according to an embodiment of the present invention. Referring to FIG. 6, the PS / A control circuit includes a comparator 101, a trigger circuit 102, a pS / A driver control circuit 103, a bias circuit 104, a comparator enable circuit 105, a level shift circuit 106, and a delay. (Delay) A circuit 201 and a latch unit 202 are provided. In contrast to the prior art, the novel arrangement is parallel to the delay circuit 201 connected to the comparator 101, the output terminal of the delay circuit 201, the output terminal of the trigger circuit 102, the input terminal of the bias circuit 104, and the input terminal of the PS / A driver control circuit 103. A connected latch portion 202 is added. In the P-S / A driver control circuit 103, a PMOS transistor Q41 connected in parallel to the NMOS transistor Q40 is added. In more detail, the PS / A driver control circuit 103 includes two NMOS transistors Q40 and Q41 connected in parallel between the NMOS transistor Q29 and the NMOS transistor Q30 in comparison with the third diagram, and the gate of the NMOS transistor Q40 is connected to the NMOS transistor Q29. The IVCC terminal is connected, and the output terminal of the latch unit 202 is connected to the gate of the NMOS transistor Q41. The delay circuit 201 receives the sensing enable signal? S as an input, and its output terminal is connected to the output node of the signal? SD. The delay circuit 201 may be designed or commonly used for each sub memory block in a semiconductor device including a plurality of sub memory blocks. The latch unit 202 inputs the trigger signal? Tri and the signal? SD, and outputs the latch signal? Latch. The operation of the latch unit 202 causes the latch signal ølatch to transition from logic high to logic low after the signal øSD is enabled from the logic low state to the logic high state and then the trigger signal øtri transitions from the logic high state to the logic low state. The latch signal ølatch remains logic low as long as the logic remains high. The characteristic of the latch unit 202 is that when the sensing enable signal øS is enabled, the first transistors of the signal ølapg enable all of the enMOS transistors Q40 and Q41 in the PS / A driver control circuit 103 to be turned on. When enabled, the NMOS transistor Q40 is turned on and the NMOS transistor Q41 is turned off. Thus, the second enable slope is greater than the first enable slope of signal ølapg, and the level of the second signal ølapg is higher than the level of the first signal ølapg, resulting in overshooting of LA by the second sensing. This can greatly reduce the effect. Here, it will be apparent to those skilled in the art that the latch unit 202 can be configured as a latch circuit other than a flip-flop.

7 is an operation timing diagram of FIG. Referring to FIG. 7, it can be seen that when the signal? Lapg is first enabled, the slope of the signal? Lapg is large and the level is high, thus reducing overshooting of the LA.

8 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to another embodiment of the present invention. Referring to FIG. 8, the PS / A control circuit includes a comparator 101, a trigger circuit 102, a first PS / A driver control circuit 103, a bias circuit 104, a comparator enable circuit 105, a level shift circuit 106, And a delay circuit 201, a latch unit 202, and a second PS / A driver control circuit 301, the PS / A driver being controlled by the first PS / A driver control circuit 103; And a second PS / A driver 302 under the control of the second PS / A driver control circuit 301. The configuration and operation of circuits corresponding to the reference numerals 101, 102, 104, 105, 106, 108, 201 and 202 of the configuration are the same as the configuration and operation of FIG. 7 described above. Therefore, a description will be given focusing on the second P-S / A driver control circuit 301 and the second P-S / A driver 302 which are additional circuits other than those shown in FIG. The first P-S / A driver control circuit 103 is connected to the NMOS transistor Q41 in series between the NMOS transistors Q29 and Q30, and a latch signal? Latch is applied to the gate of the NMOS transistor Q41. In such a configuration, when the latch signal? Latch transitions to a logic low after the first order sensing (that is, the enable of the signal? Lapg), the signal? Lapg continues to maintain a logic high level, and the PMOS transistor in the first P-S / A driver 108 is maintained. Turn off Q1. 8 is a diagram in which a second P-S / A driver control circuit 301 and a second P-S / A driver 302 are added in addition to the configuration of FIG. 7. The second P-S / A driver control circuit 301 is composed of an inverter in which a PMOS transistor Q45 and an NMOS transistor Q46 are connected in series, and an input terminal and an output terminal are respectively connected to an output node of the trigger signal? Tri and a signal? Lapg1. The second P-S / A driver 302 is composed of a PMOS transistor Q44, and EVCC,? Lapg1, and LA are connected to the source, gate, and drain, respectively. In the above-described configuration, the low address strobe signal RASB is activated in a logic low state so that the first P-S / A driver 108, for example, the PMOS transistor Q1 and the like, is activated during the first sensing (primary sensing) operation of the PS / A. For example, the second P-S / A driver 302 supplies charge to the LA by the PMOS transistor Q44, and the PMOS transistor Q1 is turned off after the second sensing (second sensing), so that only the PMOS transistor Q44 senses the sense. do. Since secondary charge has very little charge to be supplied to LA, if the size of the PMOS transistor Q44 is much smaller than that of the PMOS transistor Q1, the overshooting of LA, which is a problem in FIG. 4, can be greatly reduced. It works. In laying out the PS / A driver, the first P-S / 4 driver Q1 is divided into a plurality of transistors in the area occupied by the sense amplifier, and the second P-S / A driver Q44 can be easily laid out by laying out relatively small transistors around. Can be implemented. Here, it is apparent to those skilled in the art that the latch unit 202 may be configured as a latch circuit other than a flip-flop.

9 is a detailed circuit diagram of a P-S / A control circuit and a P-S / A driver according to another embodiment of the present invention. Referring to FIG. 9, the configuration and operation are the same as those in FIG. 8 except for the internal configuration of the 2P-S / A driver control circuit 301. FIG. Accordingly, the 2P-S / A driver control circuit 301 is the same as the PS / A driver control circuit 103 in FIG. 3, so that the voltage level of ølapg is increased when the 2P-S / A driver, for example, the PMOS transistor Q44 is operated. EVCC not at ground voltage level-| Vtn | It is a circuit for making the level of (alpha). Thus, in the first sensing operation of the P-S / A, both PMOS transistors Q1 and Q44 operate, and in the second sensing operation, only PMOS transistor Q44 operates to reduce overshooting of the LA.

FIG. 10 is a block diagram illustrating a connection between a P-S / A control circuit and a sub memory array when using an internal power supply voltage (VCCA) for an array according to another embodiment of the present invention. Referring to FIG. 10, reference numeral 400 denotes an internal power supply voltage generator for an array and reference numerals 403 to 406 denote sub memory array blocks. When the LA output nodes LA0 to LAi of the sub memory array blocks 403 to 406 are precharged to the precharge voltage VBL by the precharge circuit 109 described above with reference to FIG. 1, the low address strobe signal RASB is logic. When enabled in the low state, the equalization control signal? EQ of the selected block of the plurality of sub-memory array blocks is disabled to logic low (not shown here). After the equalization control signal? EQ of the selected block is disabled to logic low, when? Lapgi of the selected block transitions from a logic high level to a logic low level, charge is supplied from the internal power supply voltage VCCA to the output node of LA. At this time, the internal power supply voltage VCCA is precharged by a stand-by internal power supply voltage generator 401 and a PMOS transistor Q400 at a predetermined predetermined level. In general, the size of the PMOS transistor Q400 is laid out smaller than the size of the PMOS transistor Q401. Therefore, when the signal? Lapgi transitions from the logic-high level to the logic low level, when the charge of the internal power supply voltage VCCA is discharged to the output node of LA, the voltage level of the internal power supply voltage VCCA falls. At this time, when the voltage level of the internal power supply voltage VCCA falls, the circuits for supplying charge to the internal power supply voltage VCCA are an active internal power supply voltage generator 402 and a PMOS transistor 401. The sensing enable signal? S and the signal? Lapgi are both controlled by the activation signal of the low address strobe signal RASB.

11 is a detailed circuit diagram of an internal power supply voltage generator according to an embodiment of the present invention. Referring to FIG. 11, the delay circuit 201 and the latch unit 202 of FIG. 7 and FIG. 8 described above are added to the active internal power supply voltage generator 402 so that the latch signal? Latch transitions to a logic low state after the first sensing. Is maintained at a logic high level. From the second sensing, the active internal power supply voltage generator 402 and the active internal power supply driver, for example, the PMOS transistor Q401, are prevented from operating, thereby preventing overshooting of the internal power supply voltage VCCA. After the first sensing, most of the charge consumed by the internal supply voltage VCCA is supplied by the active internal supply voltage generator 402 and the active internal supply voltage driver, for example, the PMOS transistor Q401. It can also supply enough with the standby internal power supply voltage driver Q400. In addition, instead of maintaining the signal? Lapg_a at a logic high level after the first sensing, there is a method of adjusting the voltage level and the slope of the signal? Lapg_a as shown in FIG. This method is weak because it can be known to those skilled in the art in correspondence with the technical idea in FIG.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (18)

A semiconductor memory device having a sense amplifier which is operated by a predetermined control signal to apply a predetermined voltage to a memory cell, comprising: a sense amplifier driving means driven by an input of a control voltage to drive the sense amplifier, and an input of an activation signal A level control means for selectively generating first and second trigger signals by comparing the sense amplifier driving signal with a preset reference voltage, and outputting a bias control signal corresponding to the first and second trigger signals; A first voltage generated by comparing the external power supply voltage with a voltage of a predetermined defect level and detecting an output level of the external power supply voltage; and an output connected to a control voltage terminal of the sense amplifier driving means. And keeping the control voltage constant in response to the input of the second trigger signal and the bias control signal. And a sense amplifier driving control means for amplifying the control voltage in response to the voltage supplied to the memory cell at high speed, and an input terminal and an input terminal of the power supply voltage sensing means are commonly connected to each other to delay a predetermined time in response to the activation signal. A delay circuit for outputting a signal and one input terminal are connected to an output terminal of the delay circuit, and a type force terminal is commonly connected to an output terminal of the level control means and an input terminal of the sense amplifier driving control means to temporarily store and output a predetermined signal. A sense amplifier control circuit comprising a latch unit. The sense amplifier control circuit of claim 1, wherein the activation signal is a signal synchronized with a row address strobe signal supplied from the outside to access data of a memory cell of a semiconductor memory device. 2. The apparatus of claim 1, wherein the power supply voltage detection means comprises: voltage detection control means for sequentially generating a voltage detection pulse and a voltage comparison control pulse in response to an input of the activation control signal, and the voltage detection pulse and the voltage comparison control. In response to the input of the pulse, the voltage of the predetermined fault level is compared with the level of the external power supply voltage supplied from the outside of the semiconductor memory device to output a level detection signal according to the state of the external power supply voltage to the sense amplifier drive control means. A sense amplifier control circuit comprising a means. 4. The latch circuit of claim 3, wherein the detected level detection signal is latched between the voltage detection means and the sense amplifier driving control means in response to a pulse signal located between the voltage detection pulse and the generation period of the voltage comparison control pulse. And a level detection holding means for outputting. 4. The sense amplifier control circuit according to claim 3, wherein the voltage detecting means generates a level detection signal indicating a defect of the external power supply voltage when the external power supply voltage is lower than a predetermined defect level. 6. The PMOS transistor of claim 5, wherein the sense amplifier driving means has a source connected to the external power supply voltage, a drain connected to a P sense amplifier in the sense amplifier, and a gate connected to an output terminal of the sense amplifier driving control means. Sense amplifier control circuit, characterized in that. The method of claim 6, wherein the sense amplifier driving control means, the output node is connected to the control voltage input node of the sense amplifier driving means, the control voltage is lowered in response to the first trigger signal and the bias control signal and the A control means for raising the control voltage in response to a second trigger signal; a channel is formed at an output node of the external power supply voltage and the control voltage supply means; and the channel is cut off in response to the output of a level detection signal. A sense amplifier control circuit comprising a switch for transitioning to ground level. The PMOS transistor of claim 7, wherein the switch has a source connected to the external power supply voltage, a drain connected to a control voltage input node of the sense amplifier driving means, and the channel blocked when the level detection signal is input to the gate. Sense amplifier control circuit, characterized in that. 9. The apparatus of claim 7 or 8, wherein the level control means comprises: comparison means for comparing a voltage applied to the memory cell with a preset reference voltage in response to the activation signal, and an internal lower than a level of the external power supply voltage. A level shifting means for shifting and outputting an input of an activation signal having a level of a power supply voltage to a level of an external power supply voltage, and connected between said external power supply voltage and an output node of said comparing means, and responding to an output of said level shifting means Comparator output control means for enabling or disabling the output of the comparing means, triggering means for selectively outputting a first trigger signal and a second trigger signal in accordance with the output of the comparing means, and the internal power supply voltage and ground. A voltage having a predetermined level as a bias control signal to the control means in response to the first trigger signal. It characterized that the composed class bias means for the sense amplifier control circuit. A semiconductor memory device having a sense amplifier for supplying a sensing voltage to a memory cell in response to an input of a first voltage and supplying an active restore voltage to the memory cell in response to an input of a second voltage. Is connected to a first sense amplifier driving means and a first sense amplifier driving means for driving the sense amplifier to a first voltage and being driven at an input of a first control voltage, and the sense by input of a second control voltage. A second sense amplifier driving means for driving the amplifier to a second voltage and an activation signal for activating the memory cell to compare the sense amplifier driving signal with a preset reference voltage to selectively select the first and second trigger signals. Level control means for generating a bias control signal in response to the first and second trigger signals; Power supply voltage sensing means for detecting and maintaining the level of the external power supply voltage by comparing the voltages, and first and second outputs are connected to control voltage terminals of the first and second sense amplifier driving means, respectively. A first control voltage maintained at a predetermined level is supplied to the first sense amplifier driving means in response to the input of the first and second trigger signals and the bias control signal, and a second control voltage is supplied in response to the level detection signal. And a sense amplifier driving control means for supplying the second sense amplifier driving means to rapidly shift the voltage supplied to the memory cell. 12. The sense amplifier control circuit of claim 10, wherein the activation signal is a signal synchronized with a row address strobe signal supplied from the outside to access data of a memory cell of a semiconductor memory device. 12. The apparatus of claim 11, wherein the power supply voltage detection means comprises: voltage detection control means for sequentially generating a voltage detection pulse and a voltage comparison control pulse in response to an input of the activation control signal, and the voltage detection pulse and the voltage comparison control. In response to the input of the pulse, the voltage of the predetermined fault level is compared with the level of the external power supply voltage supplied from the outside of the semiconductor memory device to output a level detection signal according to the state of the external power supply voltage to the sense amplifier drive control means. A sense amplifier control circuit comprising a means. 13. The apparatus of claim 12, wherein the detected level detection signal is latched between the voltage detection means and the sense amplifier driving control means in response to a pulse signal located between the voltage detection pulse and the generation period of the voltage comparison control pulse. And a level detection holding means for outputting. 13. The sense amplifier control circuit according to claim 12, wherein the voltage detection means generates a level detection signal indicating a defect of the external power supply voltage when the external power supply voltage is lower than a predetermined defect level. 15. The apparatus of claim 14, wherein the level control means comprises: comparing means for comparing a voltage applied to the memory cell with a preset reference voltage in response to the activation signal, and a level of an internal power supply voltage lower than a level of the external power supply voltage. Level shifting means for shifting and outputting an input of an activation signal having a level to an external power supply voltage, and being connected between the external power supply voltage and an output node of the comparing means and responsive to the output of the level shifting means; A comparator output control means for enabling or disabling the output of a signal and selectively supplying a first trigger signal of a first level and a second trigger signal of a second level to the sense amplifier driving control means according to the output of the comparing means; And a trigger means connected between the internal power supply voltage and a ground voltage to supply a voltage having a predetermined level in response to the first trigger signal. And a bias means for supplying the sense amplifier drive control means as a bias control signal. 16. The apparatus of claim 15, wherein the sense amplifier driving control means comprises: power supply means for supplying the external power supply voltage to the first sense amplifier driving means and a first control voltage input node, and the output node being the first sense amplifier driving means. A control means connected to a first control voltage input node of the first control voltage, the control means for maintaining the first control voltage at a predetermined level in response to the first trigger signal and a bias control signal, and in response to an output of the level detection signal; And a second control voltage supply means for supplying a second control voltage which is much lower than one control voltage to said second sense amplifier drive control means. 17. The apparatus of claim 16, wherein the first and second sense amplifier driving means comprise: a source connected to an external power supply voltage, a drain connected to a control terminal of the sense amplifier, and each gate connected to an output node of the control means and the first means. 2. A sense amplifier control circuit characterized in that the NMOS transistors are connected to the output node of the control voltage supply means. 17. The sense amplifier control circuit of claim 15 or 16, wherein the second control voltage is a ground level voltage.