KR20030095633A - Mos transistor having asymmetrical spacers and method of fabricating the same - Google Patents

Abstract

PURPOSE: A MOS(Metal Oxide Semiconductor) transistor having an asymmetric spacer and a manufacturing method therefor are provided to be capable of improving the degree of integration and reducing resistivity when operating the transistor. CONSTITUTION: A MOS transistor is provided with a substrate(102), a gate electrode(112) having a gate isolating layer(110), and a plurality of gate spacers(118,118a) formed at both sidewalls of the gate electrode. At this time, the lower width of the second spacer(118a) is relatively smaller than that of the first spacer(118). The MOS transistor further includes the first conductive type low doping impurity region(114b) formed at the lower portion of the first spacer, the first conductive type high doping impurity region(120b), the first electrode formed at the upper portion of the first conductive type high doping impurity region, the first conductive type low doping impurity region(114a) formed at the lower portion of the second spacer, the second conductive type well pickup region(122d), and the second electrode.

Description

A MOS transistor having an asymmetric spacer and a method of manufacturing the same {MOS TRANSISTOR HAVING ASYMMETRICAL SPACERS AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing the same, and more particularly, to a MOS transistor having an asymmetric spacer on a sidewall of a gate electrode, and a method of manufacturing the same.

As we enter the era of Very Large Scale Integration (VLSI), the power dissipation of NMOS devices is becoming a serious problem, so the development of low power consumption technology is indispensable. The CMOS technology proposed for the breakthrough of this problem has resulted in a power reduction of 1/2 to 1/4.

Fig. 1A shows a CMOS inverter, which is composed of transistors of NMOS and PMOS. The gates of the NMOS and the PMOS are tied together to be an input terminal of the inverter, and the drains of the NMOS and PMOS are the output terminals of the inverter.

When the above-described CMOS inverters are cross-connected, they become SRAM cells as shown in Fig. 1B.

Referring to FIG. 1B, an SRAM cell is composed of two access transistors AT1 and AT2, two pull-up transistors PT1 and PT2, and two driver transistors DT1 and DT2. Transistors PT1 and DT1 constitute a first inverter, and transistors PT2 and DT2 constitute a second inverter. The first and second inverters are cross connected at two nodes N1 and N2. The source regions of the transistors DT1 and DT2 are connected to the ground line Vss, and the source regions of the transistors PT1 and PT2 are connected to the power supply line VDD. The drain of the transistor AT1 is connected to the bit line BL1, and the drain of the transistor AT2 is connected to the bit line BL2. The source of transistor AT1 and the source of transistor AT2 are connected to node N1 and node N2, respectively. Gate electrodes of the transistors AT1 and AT2 are connected to the common word line WL.

FIG. 2 illustrates a cross-sectional view of an actual implementation of the CMOS inverter of FIG. 1A.

Referring to FIG. 2, a field region 8 defining an active region is formed in the substrate 2, and an NMOS 50 and a PMOS 60 are disposed between the field regions 8.

The NMOS 50 includes a gate stack composed of a gate insulating film 10, a gate electrode 12, and a gate spacer 18, low doping impurity regions 14a and 14b, and high doping impurity regions 20a and 20b. Source and drain regions 23a and 23b. The source and drain regions 23a and 23b are located in the p well 6 formed in the substrate, and the p well pickup region 22c is disposed adjacent to the source region 23a.

The PMOS 60 is composed of a gate stack composed of a gate insulating film 10, a gate electrode 12, and a gate spacer 18, low doping impurity regions 16a and 16b, and high doping impurity regions 22a and 22b. Source and drain regions 25a, 25b. The source and drain regions 25a and 25b are located in the n well 4 formed in the substrate, and the n well pickup region 20c is disposed adjacent to the source region 25a.

The silicide layer 26 is formed on the active region of the substrate adjacent to the gate stacks of the NMOS and PMOS.

The gate electrodes 12 of the NMOS and PMOS are electrically connected to each other to be an input terminal Vin, and the drain regions 23b and 25b of the NMOS and PMOS are connected to each other by a metal wiring 30a so that the output terminal Vout is connected to each other. do.

The source region 23a and the p well pick-up region 22c of the NMOS are connected to the ground power source Vss through the metal wiring 30b. Similarly, the source region 25a and the n well pick-up region 20c of the PMOS are connected to the power supply voltage Vdd through the metal wiring 30c. Unexplained reference numeral 28 denotes an insulating film.

In the above-described structure, the ground power source Vss is applied to the p well 6 to the p well pickup region 22c, and the power supply voltage Vdd is applied to the n well 4 to the n well pickup region 20c. do. As such, the well bias voltage applied to the p well 6 and the n well 4 improves the threshold voltage (Vth) and helps to stabilize the electrical characteristics of each transistor.

However, as the integration of the device proceeds, the area for forming the n-type highly doped impurity region and the p-type highly doped impurity region is reduced, and as shown in FIG. A method of forming only (20d, 22d) is considered.

Referring to FIG. 3, a p-type highly doped impurity region 22d is formed on the source terminal side of the NMOS transistor, and an n-type highly doped impurity region 20d is formed on the source terminal side of the PMOS transistor.

However, the CMOS inverter having the above structure has the following problems.

First, an unwanted PN junction (shown as 'A' and 'B' in the figure) is formed on the substrate under the gate spacer of the NMOS and PMOS transistors. This may cause the inverter to not operate by blocking the current path as a reverse diode in the operation of the inverter.

Second, since the low doping impurity regions 14a and 16a are low in concentration and high in resistance, the MOS transistor may operate to reduce the flow of current.

Due to the above problems, it is necessary to develop a MOS transistor that realizes integration and does not block the current path of the MOS transistor and does not increase resistance during operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a MOS transistor and a method of manufacturing the same, which can be integrated and have a reduced resistance during operation.

1A is a circuit diagram showing a CMOS inverter,

1B is a circuit diagram showing an SRAM cell,

2 and 3 are cross-sectional views of the CMOS inverter of FIG.

4 is a cross-sectional view illustrating a structure of a MOS transistor according to an embodiment of the present invention;

5A through 5C are cross-sectional views illustrating a method of manufacturing a MOS transistor according to an exemplary embodiment of the present invention in a process order.

* Explanation of symbols for the main parts of the drawings

2, 102: substrate 4, 104: n well

6, 106: p well 8, 108: field area

10, 110: gate insulating film 12, 112: gate electrode

14a, 14b, 114a, 114b: n-type low doping impurity region

16a, 16b, 116a, 116b: p-type low doping impurity region

20a, 20b, 20c, 20d, 120b, 120d: n-type highly doped impurity region

22a, 22b, 22c, 22d, 122b, 122d: p-type highly doped impurity region

30a, 30b, 30c, 130: metal wiring

In order to achieve the above object, the MOS transistor of the present invention is composed of a gate electrode, a first electrode and a second electrode. The gate electrode is formed on the substrate via a gate insulating film, and is formed on both sidewalls of the gate electrode, and the second spacer includes gate spacers having a lower width relative to the first spacer. The first electrode may include a low conductivity doping impurity region of a first conductivity type formed on a substrate under the first spacer, a highly conductive doping impurity region of a first conductivity type formed on a substrate adjacent to the first spacer, and a high conductivity of the first conductivity type. A first silicide film formed on the doped impurity region. The second electrode may include a low conductivity doped impurity region of a first conductivity type formed on a substrate under the second spacer, a well pickup region of a second conductivity type formed on a substrate adjacent to the second spacer, and a well of the second conductivity type. And a second silicide film formed on at least a portion of the pickup region and the low doping impurity region of the first conductivity type. The first electrode may be a source electrode, the second electrode drain electrode, or vice versa. In addition, the first conductivity type may be n-type, the second conductivity type may be p-type, or vice versa.

In order to achieve the above object, the manufacturing method of the MOS transistor of the present invention first forms a gate electrode via a gate insulating film on the substrate. The gate electrode is used as a mask for ion implantation to form a low conductivity doped impurity region of a first conductivity type and to form first and second gate spacers on both sidewalls of the gate electrode. A doping impurity region of a first conductivity type is formed on the substrate adjacent to the first gate spacer, and a well pickup region of a second conductivity type is formed on the substrate adjacent to the second gate spacer. Selectively etching the second spacer to expose at least a portion of the low doping impurity region of the first conductivity type, forming a first silicide film on the highly doped impurity region of the first conductivity type, and simultaneously A second silicide film is formed on the well pick-up region of the type and the exposed doped impurity region of the at least one portion of the first conductivity type.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view illustrating a structure of a MOS transistor according to an embodiment of the present invention.

Referring to FIG. 4, a field region 108 defining an active region is formed in the substrate 102, and an NMOS 150 and a PMOS 160 are disposed between the field regions 108.

The NMOS 150 includes a gate stack composed of a gate insulating film 110, a gate electrode 112, and gate spacers 118 and 118a, low doping impurity regions 114a and 114b, and high doping impurity regions 120b and 122d. Configured source and drain regions. Here, reference numeral 122d functions as a p well pick-up area. The source and drain regions are located in p wells 106 formed in the substrate. The gate spacer formed on the sidewall of the gate electrode 112 is asymmetrical and the gate spacer 118a on the source electrode side is recessed while exposing the low-doped drain region 114a. The silicide layer 126 is formed on the exposed low-doped impurity region 114a and the p-well pick-up region 122d to form a barrier-free current path of the PN junction and to reduce the resistance.

The PMOS 160 includes a gate stack composed of a gate insulating layer 110, a gate electrode 112, and gate spacers 118 and 118a, a low doping impurity region 116a and 116b, and a high doping impurity region 120d and 122b. Source and drain regions. Here, reference numeral 120d functions as an n well pick-up area. The source and drain regions are located in n well 104 formed in the substrate. The gate spacer formed on the sidewall of the gate electrode 112 is asymmetrical and the gate spacer 118a on the source electrode side is recessed while exposing the low doped drain region 116a. The silicide layer 126 is formed on the exposed low-doped impurity region 116a and the n-well pick-up region 120d to form a barrier-free current path of the PN junction and to reduce resistance. Unexplained reference numeral '128' denotes an insulating film, and reference numeral '130' denotes a metal wiring.

5A through 5C are cross-sectional views illustrating a method of manufacturing a MOS transistor according to an exemplary embodiment of the present invention in a process order.

Referring to FIG. 5A, n well 104 and p well 106 are formed on substrate 102 using respective well masks (not shown). A field region 108 defining an active region is defined in a substrate including n wells and p wells. Subsequently, the gate insulating film 110 and the gate conductive film 112 are sequentially stacked on the substrate 102 on which the active region is defined. The gate conductive layer 112 and the gate insulating layer 110 are patterned to form the gate electrode 112 via the gate insulating layer 110. Subsequently, a mask pattern (not shown) covering the PMOS region 160 is formed, and the n-type low-doped impurity is formed by using the mask pattern, the gate electrode 112 and the field region 108 as a mask for ion implantation. Area 114 is formed. Subsequently, the mask pattern is removed and a mask pattern covering the NMOS region 150 is formed, and p-type low doping is performed using the mask pattern, the gate electrode 112, and the field region 108 as a mask for ion implantation. An impurity region 116 is formed. A spacer insulating layer is formed on the entire surface of the substrate including the gate electrode 112 and anisotropic plasma etched back to form a gate spacer 118 on sidewalls of the gate electrode 112. Subsequently, a mask pattern (not shown) defining an n-type highly doped impurity region is formed, and the mask pattern, the gate electrode 112 having the gate spacer 118 formed on a sidewall, and the field region 108 are formed. Is used as a mask for ion implantation to form n-type highly doped impurity regions 120b and 120d. The n-type impurity region 120b formed in the NMOS 150 region becomes a drain region of the NMOS, and the n-type impurity region 120d formed in the PMOS 160 applies a bias to the n well 104. n well pick-up area 120d. As described above, the n well pick-up region 120d is formed adjacent to the p-type low-doped impurity region 116 to form a PN diode (reference numeral 'B').

Next, a mask pattern (not shown) defining a p-type highly doped impurity region is formed, and the mask pattern, the gate electrode 112 and the field region 108 having the gate spacer 118 formed on a sidewall thereof are formed. P-type highly doped impurity regions 122b and 122d are formed using as a mask for ion implantation. The p-type impurity region 1202b formed in the PMOS 160 region becomes a drain region of the PMOS, and the p-type impurity region 122d formed in the NMOS 150 region applies a bias to the p well 104. P well pick-up area 122d. As described above, the p-well pick-up region 122d is formed adjacent to the n-type low-doped impurity region 114 to form a PN diode (a portion 'A').

Referring to FIG. 5B, a mask pattern 124 is formed to expose spacers formed on sidewalls of source regions of the NMOS and PMOS transistors. The exposed spacer 118 is partially etched using the mask pattern 124 as an etch mask to form a spacer pattern 118a exposing portions of the low-doped impurity regions 114 and 116.

Referring to FIG. 5C, the mask pattern 124 is removed, and the n-type highly doped impurity regions 120b and 120d, the p-type highly doped impurity regions 122b and 120d, and the exposed low-doped impurity regions 114 are illustrated. , And the silicide layer 126 is formed on the layer 116. Depending on the material constituting the gate electrode 112, a silicide layer may be formed on the top surface of the gate electrode 112. The silicide layer 126 is made of any one metal selected from among cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), Pt (platinum), Hf (hafnium), and Pd (palladium). Can be formed.

The silicide layer 126 is formed between the p well pick-up region 122d and the n-type low-doped impurity region 114 in the NMOS region and the n-well pick-up region 120d and the p-type low doping in the PMOS region. The barrier of the current path by the diode B formed between the impurity regions 116 is electrically connected. By reducing the width of the spacer 118a of the source region of the MOS transistor, the silicide layer 126 is formed on the low-doped impurity regions 114 and 116 to form a current path and reduce resistance.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention as described above, by forming the spacers formed on both sidewalls of the MOS transistors asymmetrically, it is possible to form a MOS transistor whose integration is realized while the resistance is not reduced during operation.

Claims (11)

A gate electrode formed on the substrate via a gate insulating film; Gate spacers formed on both sidewalls of the gate electrode, and the second spacer having a lower width relatively to that of the first spacer; A low doping impurity region of a first conductivity type formed on a substrate under the first spacer, a high doping impurity region of a first conductivity type formed on a substrate adjacent to the first spacer, and a high doping impurity region of the first conductivity type A first electrode composed of a first silicide film formed on the first silicide film; And A low doping impurity region of a first conductivity type formed in a substrate below the second spacer, a well pickup region of a second conductivity type formed in a substrate adjacent to the second spacer, and a well pickup region of the second conductivity type and the A MOS transistor comprising a second electrode composed of a second silicide film formed on at least a portion of a low doping impurity region of a first conductivity type. The method of claim 1, And a first electrode of the MOS transistor is a drain electrode, and a second electrode of the MOS transistor is a source electrode. The method of claim 2, And the transistor is an NMOS transistor, and the source electrode is connected to a ground power source. The method of claim 2, And the transistor is a PMOS transistor, and the source electrode is connected to a power supply voltage. The method of claim 1, The MOS transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. The method of claim 1, And the first conductivity type is p-type, and the second conductivity type is n-type. Forming a gate electrode through the gate insulating film on the substrate; Forming a low doping impurity region of a first conductivity type using the gate electrode as a mask for ion implantation; Forming first and second gate spacers on both sidewalls of the gate electrode; Forming a highly conductive doping impurity region of a first conductivity type in the substrate adjacent the first gate spacer; Forming a well pick-up region of a second conductivity type in the substrate adjacent the second gate spacer; Selectively etching the second spacer to expose at least a portion of the low doping impurity region of the first conductivity type; And A first silicide film is formed on the highly conductive doped impurity region of the first conductivity type, and at the same time, a second silicide is formed on the well pickup region of the second conductivity type and the lightly doped impurity region of the at least part of the first conductivity type. A method of manufacturing a MOS transistor comprising the step of forming a film. The method of claim 7, wherein Selectively etching the second spacer to expose the impurity region of the first conductivity type, Forming a mask pattern covering the first spacer but exposing the second spacer; And And anisotropically etching the second spacer using the mask pattern as an etch mask. The method of claim 7, wherein Wherein the first conductivity type is n-type, and the second conductivity type is p-type. The method of claim 7, wherein The first conductive type is p-type, and the second conductive type is n-type manufacturing method of the MOS transistor characterized in that formed. The method of claim 7, wherein The silicide layer may be formed of any one metal selected from cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), Pt (platinum), Hf (hafnium), and Pd (palladium). The manufacturing method of a MOS transistor.