KR20030091232A - Isolation method of semiconductor devices using trench - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device using a trench is provided to reduce a junction leakage current by forming an active region penetrating oxide layer or insulation layer under a junction, and to decrease parasitic capacitance by decreasing the quantity of injected impurities for forming a source/drain region. CONSTITUTION: Oxidation accelerating ions are implanted into a semiconductor substrate(210) to form an oxidation accelerating ion implantation layer(212) having a predetermined depth from the surface of the substrate. A mask pattern fro defining an active region and a trench formation region is formed on the semiconductor substrate. The semiconductor substrate is etched to form a trench by using the mask pattern as an etch mask until the oxidation accelerating ion implantation layer is exposed. The exposed oxidation accelerating ion implantation layer is selectively oxidized to form an oxide layer penetrating the inside of the active region. The trench is filled with an insulation layer.

Description

Isolation method of semiconductor devices using trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of separating semiconductor devices using trenches, in particular, a method of selectively oxidizing a semiconductor substrate using oxidation promoting ions so that the oxide film penetrates into the active region and an insulating film in the lower portion of the active region using isotropic etching. The present invention relates to a semiconductor device separation method that can be filled.

As semiconductor devices are highly integrated, efforts have been made to reduce device isolation regions and to secure more active regions. A representative one of them is a thin trench isolation technology. The thin trench isolation technique is based on a method of forming a trench in a semiconductor substrate to isolate devices, and then embedding an insulating film such as an oxide film in the trench. Therefore, according to the thin trench isolation technology, unlike the LOCOS (LOCal Oxidation of Silicon) method, the reduction of the active area by bird's beak does not occur. It is possible to flatten it, which is advantageous for the subsequent process.

However, the thin trench isolation technique has several drawbacks, despite the above advantages, which do not fully support high integration. A representative one of them is that current leaks from the junction, and the reliability of the device is lowered by the junction capacitance, that is, the parasitic capacitance. In particular, if a leakage of current from a junction and a parasitic capacitance increase in a DRAM device, the time required for the device to retain data is greatly reduced, and the operation speed of the device is degraded. do.

Looking at the leakage of the current in more detail, it is necessary to periodically refresh the data stored in the cell in order to store specific data in the DRAM cell. If there is a lot of leakage current, the data holding time will be shorter, so you will have to refresh more often, which will consume more power. In addition, since the read / write cannot be performed during the refresh, the speed of the semiconductor device is reduced.

The conventional techniques presented to solve the above problems can be divided into two categories. One is to reduce the leakage current by blocking the leakage path through which the charge charged to the cell capacitor escapes, and the other is to increase the amount of charged charge itself by increasing the area of the cell capacitor. will be. From a general point of view, it is necessary to have a structure that can satisfy both of the above conditions, that is, to make the capacity of the capacitor as large as possible and to find the main leakage path through which the charge escapes from the capacitor and to minimize the leakage of charge. It's the best way.

However, the method of increasing the area of the cell capacitor has reached a certain limit because of the limited size of the device. Therefore, much research is focused on reducing current leakage.

1 is a plan view of a semiconductor device formed by a semiconductor device isolation method using a trench according to the prior art, and FIG. 2 is a line AA ′ (left side of FIG. 2) and BB ′ line (right side of FIG. 2) of FIG. 1. Is a cross-sectional view taken along

1 and 2, the semiconductor substrate 110 is divided by an insulating layer 116 in which the active region 10 and the device isolation region are embedded in the trench, respectively, and the well and the source / drain regions 118 are separated from each other. It is formed in each of the active regions 10 to form a junction. A gate oxide layer 130 and a plurality of gate electrode patterns 132 and 134 are formed on the semiconductor substrate 110, and gate spacers 236 are formed on sidewalls of the gate electrode patterns 132 and 134.

Although not shown in the drawing, in the case where the semiconductor device is a DRAM device, after the gate patterns 132 and 134 of FIG. 2 are formed, a bit line (not shown) is formed, and then a capacitor is positioned above the junction. The capacitor is electrically connected to the semiconductor substrate through the contact.

As can be seen from Fig. 2, in the case of a semiconductor device including a device isolation region formed by a conventional technique, the area in which the junction in the active region 10 is in contact with the substrate 110 is large. There is a problem that the charge stored in the leakage through the junction to the substrate.

In addition, the miniaturization of the device increases the possibility that a cell transistor may interfere with the operation of neighboring cells, thereby causing an error. To prevent this, a threshold voltage must be maintained at a certain level or more. In order to maintain a high threshold voltage, it is necessary to increase the doping concentration of impurities injected into the substrate. However, increasing the doping concentration not only causes more leakage of the above-mentioned current, but also increases the junction capacitance, which results in worse refresh characteristics of the semiconductor device.

Therefore, in order to solve the above problem and improve the refresh characteristics of the DRAM device, there is a need to reduce the area in which the junction contacts the substrate, thereby minimizing leakage of current through the junction.

SUMMARY OF THE INVENTION A technical problem to be solved by the present invention is a trench including a device isolation region capable of forming a semiconductor device having a structure capable of reducing leakage current through a junction and reducing junction capacitance in an improved process. It is to provide a semiconductor device separation method used.

1 is a plan view of a semiconductor device formed by a semiconductor device isolation method using a trench according to the prior art;

FIG. 2 is a cross-sectional view taken along the AA 'line (left side of FIG. 2) and BB' line (right side of FIG. 2) of FIG. 1;

3 is a plan view of a semiconductor device formed by a semiconductor device isolation method using a trench in accordance with the present invention;

4 through 9 are cross-sectional views illustrating a method of separating a semiconductor device in accordance with a first embodiment of the present invention, according to a process sequence. The left side of FIGS. 4 through 9 are along the AA ′ line of FIG. 3. 9 is a cross-sectional view taken along the line BB 'of FIG. 3, and

10 to 15 are cross-sectional views illustrating a method of separating a semiconductor device in accordance with a second embodiment of the present invention, in order of processing. The left-side view of FIGS. 10 to 15 is along the AA ′ line of FIG. 3. 15 is a cross-sectional view taken along the line BB 'of FIG.

<Explanation of symbols for the main parts of the drawings>

10, 20: active region 110, 210, 310: semiconductor substrate

116, 216, 316: trench filling insulating film

118, 218, 318: source / drain regions

130, 230, 330: gate oxide film 132, 232, 332: gate electrode

134, 234, 334 capping film

136, 236, 336: Gate spacer

212 oxidation promoting ion implantation layer

214: active area penetration oxide film

222, 322: pad oxide film

224, 324: nitride film for trench formation

326: Active area protection spacer

The semiconductor device isolation method using a trench according to the present invention for achieving the above technical problem is a step of forming an oxidation-promoting ion implantation layer having a predetermined depth from the surface of the semiconductor substrate by implanting oxidation-promoting ions into the semiconductor substrate Forming a mask pattern defining an active region and a trench forming region on the substrate; forming a trench by etching the semiconductor substrate until the oxidation-promoting ion implantation layer is exposed using the mask pattern as an etching mask; Selectively oxidizing the oxidation promoting ion implantation layer to form an oxide film that penetrates into the active region and filling the trench with an insulating film.

The oxidation promoting ion implantation layer may be formed to be shallower than the depth at which the trench is formed.

Fluorine ions may be used as the oxidation promoting ions to be injected into the oxidation promoting ion implantation layer.

An oxide film can be used as the insulating film filling the trench.

The semiconductor device may be a DRAM device.

An oxide film penetrating the active region may be formed under the capacitor node junction.

Another semiconductor device isolation method using a trench according to the present invention for achieving the above technical problem is to form a mask pattern defining an active region and a trench isolation region on the semiconductor substrate and using the mask pattern as an etching mask Etching the substrate to a depth where a source / drain is to be formed, forming an active region protection spacer on the side of the mask pattern and the active region, and using the mask pattern and the active region protection spacer as an etching mask, the semiconductor substrate in the trench isolation region And etching the semiconductor substrate to form a trench that penetrates into the lower portion of the active region, and filling the trench with an insulating layer.

An oxide film may be used as the insulating film filling the trench.

The active area protection spacer may be formed of a nitride film.

The semiconductor device may be a DRAM device.

An insulating layer penetrating into the active region may be formed under the capacitor node junction.

According to the present invention, an oxide film or an insulating film is formed under the junction. Thus, the junction leakage current and junction capacitance can be reduced. And since the oxidation promoting ion is first implanted at a predetermined depth and selectively oxidized to form an oxide film, the thickness and depth of the oxide film can be easily adjusted. And because the simplified process is applied, the process is easy and production costs can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the technical spirit of the present invention to be thoroughly and completely disclosed, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layer regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

3 through 9 illustrate a method of forming a semiconductor device isolation region using trench isolation and subsequently forming a gate pattern and a source / drain region according to a first preferred embodiment of the present invention. Therefore, the drawings are shown. FIG. 3 is a plan view of the semiconductor device of FIG. 9, and FIGS. 4 to 8 are lines AA 'of FIG. 3 (left side of FIGS. 4 to 9) and BB' lines (right side of FIGS. 4 to 9). Sections cut along the side.

3, unlike FIG. 1, it can be seen that the active region 20 is divided by a dotted line. The edge portion 22 of the active region 20 is a portion in which an active region penetrating oxide film is formed at a predetermined depth, and the present invention forms such an oxide film under the active region 20 to prevent leakage of current and to junction. Capacitance can be reduced. Hereinafter, a method of separating a semiconductor device using a trench for forming an oxide promoting ion implantation layer according to a process sequence to form an oxide film penetrating the lower portion of an active region will be described.

Referring to FIG. 4, the oxidation promoting ion implantation layer 212 is formed by implanting oxidation promoting ions at a predetermined depth into the semiconductor substrate 210 using ion implantation. As the oxidation promoting ion, fluorine ions or chlorine ions may be used. The depth at which the oxidation promoting ion implanted layer 212 is formed is determined in consideration of the depth at which the source / drain regions are formed and the depth at which the trench is formed for device isolation. That is, when the trench is formed, the oxidation promoting ion implantation layer 212 should be exposed to the side of the trench, and the oxide film formed by the oxidation promotion ion implantation layer 212 may be able to block a portion of the source / drain junction. do. Crystal lattice damaged by the implantation of oxidation promoting ions is cured by annealing.

Referring to FIG. 5, the surface of the silicon substrate 210 is oxidized to form a pad oxide film 222, and then a trench forming nitride film 224 to be used as a hard mask is deposited thereon. Then, a photoresist is applied to form trenches, which are active regions and device isolation regions, and then patterned using a photolithography process, followed by a trench forming nitride film 224 and a pad oxide film on the region where the trenches are to be formed. The 222 and the silicon substrate 210 are sequentially etched to form trenches. The depth of the silicon substrate 210 to be etched is preferably equal to or deeper than the depth of the oxidation promoting ion implantation layer 212 to expose the oxidation promoting ion implantation layer 212. That is, in the case where the trench is formed by etching the silicon substrate in the device isolation region, all or part of the oxidation promotion ion implantation layer 212 in the device isolation region is etched and formed in the active region. ) Is preferably exposed to the sides of the trench.

Referring to Fig. 6, only the silicon substrate where the oxidation promoting ion implantation layer 212 is formed is selectively oxidized to form an active region penetrating oxide film 214. The active region penetrating oxide film 214 is formed by performing a thermal oxidation process. A portion of the semiconductor substrate into which oxidation promoting ions such as fluorine ions are implanted causes an oxidation reaction first to form an oxide film only in this portion. .

Therefore, in the semiconductor device having the above-described structure, even if impurities are implanted in a subsequent process to form the source / drain regions 218, a path where current leakage occurs because the area where the junction contacts the substrate is reduced by the oxide film. Will decrease. In addition, when the leakage current decreases, the amount of impurities injected to form the source / drain may be reduced. The selective oxide film forming process according to the present invention is not only capable of controlling the depth and thickness at which the oxide film is formed, but also the manufacturing process is simple. That is, in the above method, the depth, thickness, etc. of forming the oxidation-promoting ion implantation layer can be controlled by controlling only the amount of the oxidation-promoting ions to be implanted and the implantation energy, and the thickness and depth of the oxide film penetrating into the active region can be easily controlled. Can be adjusted.

Next, referring to FIG. 7, the trench is filled using an insulating film 216, for example, an oxide film, to electrically isolate the cells. Then, the trench filling insulating layer 316, the trench forming nitride film 224 and the pad oxide film 222 on the remaining active regions are removed and the semiconductor substrate is planarized to complete the device isolation region.

Referring to FIG. 8, a gate insulating layer 230, a doped polysilicon layer, and a capping layer are sequentially deposited on a semiconductor substrate divided into a device isolation region and an active region, and then a gate pattern 232 is formed using a photolithography process. , 234). Referring to FIG. 9, a cell transistor is completed by implanting ions into the semiconductor substrate 210 to form a source and a drain 218 and then forming a gate spacer 236 using an insulating layer.

3 and 10 to 15 are processes to show a method of forming a semiconductor device isolation region using trench isolation and a process of subsequently forming a gate pattern and a source / drain region according to a second embodiment of the present invention. The figures are shown in order. 3 is a plan view of the semiconductor device of FIG. 15, and FIGS. 10 to 15 are lines AA '(left side of FIGS. 4 to 9) and BB' lines (right side of FIGS. 4 to 9) of FIG. Sections cut along the side.

Referring to FIG. 10, the surface of the silicon substrate 310 is oxidized to form a pad oxide film 322, and then a trench forming nitride film 324 to be used as a hard mask is deposited thereon. A photoresist is then applied to form trenches, the active and device isolation regions, and then patterned using a photolithography process. That is, the trench forming nitride film 324, the pad oxide film 322, and the silicon substrate 310 on the region where the trench is to be formed are sequentially etched one step. The depth of the silicon substrate 310 to be etched is about the depth at which the source / drain regions 318 (see FIG. 15) are to be formed, which will be described later.

Referring to FIG. 11, the spacer 326 for protecting the active region is formed on the sidewalls of the active region 20 and the mask patterns 322 and 324 using a deposition and etching process in this field. The active area protection spacer 326 is preferably formed using a nitride film. Next, referring to FIG. 12, using the mask patterns 322 and 324 and the active area protection spacer 326 as an etch mask, anisotropic etching of only the semiconductor substrate in the trench formation region is performed to perform two-step etching to a depth at which the trench is formed. do.

Referring to FIG. 13, the trench is subjected to isotropic etching again to the semiconductor substrate etched to the depth of the trench. As a result, the upper portion of the active region 20 in which the active region protection spacer 326 is formed is protected from etching, but since the lower active region 20 is etched away to a predetermined depth, the trench is removed from the lower portion of the active region. It will penetrate until. Since the portion of the active region 20 protected from etching is the region where the source / drain is to be formed in a subsequent process, this portion should not be etched, and after this one-step etching, the active region protection spacer 326 is formed. And then perform a two-step etch to the depth of the trench.

Referring to FIG. 14, the trench filling insulating layer 316 is filled with the trench penetrating to the lower portion of the active region. The trench filling insulating layer 316 generally uses an oxide film. Then, the trench filling insulating layer 316, the trench forming nitride film 224 and the pad oxide film 222 on the remaining active regions are removed to planarize the semiconductor substrate to complete the device isolation region.

Since the process of FIG. 15 is the same as the process described above with reference to FIG. 8, description thereof will be omitted here.

After the process of FIGS. 8 and 15 is completed, in order to complete the DRAM device, although not shown, an interlayer insulating film is coated and a bit line is formed. In the above process, the capacitor node is formed on the semiconductor substrate in the portion where the active region penetrating oxide films 214 and 316 are formed, and the capacitor dielectric film, the upper electrode, and the metal wiring are sequentially formed. In the DRAM device completed in this manner, since the oxide film or the insulating film is formed under the junction of the capacitor node, the contact area between the junction and the substrate is reduced and the path from which the charge from the capacitor leaks is reduced. Therefore, when the amount of leakage current decreases, the refresh characteristic of the DRAM device may be improved, and the operation speed of the device may be improved.

According to the present invention, since the active region penetrating oxide film or the insulating film is formed below the junction, the junction leakage current can be reduced, and the amount of impurities injected to form the source / drain regions can be reduced, thereby reducing the parasitic capacitance. A semiconductor device can be formed. In addition, not only the depth and thickness of the trench penetrating oxide film may be easily adjusted, but also the process may be simplified, thereby reducing manufacturing period and manufacturing cost.

Claims (11)

Implanting oxidation promotion ions into the semiconductor substrate to form an oxidation promotion ion implantation layer having a constant depth from the surface of the semiconductor substrate; Forming a mask pattern defining an active region and a trench formation region on the semiconductor substrate; Etching the semiconductor substrate using the mask pattern as an etch mask to form a trench until the oxidation promoting ion implantation layer is exposed; Selectively oxidizing the exposed oxidation promoting ion implantation layer to form an oxide film penetrating into the active region; And And separating the trench with an insulating film. The method of claim 1, wherein the oxidation promoting ion implantation layer is formed to be shallower than a depth at which the trench is formed. The method of claim 1, wherein the oxidation promoting ions injected into the oxidation promoting ion implantation layer are fluorine ions. The method of claim 1, wherein the insulating film filling the trench is formed of an oxide film. The method of claim 1, wherein the semiconductor device is a DRAM device. The method of claim 5, wherein the active region penetrating oxide layer is formed under a capacitor node junction. Forming a mask pattern on the semiconductor substrate, the mask pattern defining an active region and a trench isolation region; First etching the semiconductor substrate to a depth at which a source / drain is to be formed using the mask pattern as an etching mask; Forming an active region protection spacer on side surfaces of the mask pattern and the active region; Second etching the semiconductor substrate in the trench isolation region using the mask pattern and the active region protection spacer as an etching mask; Isotropically etching the semiconductor substrate to form a trench that penetrates to the bottom of the active region; And And separating the trench with an insulating film. 8. The method of claim 7, wherein the insulating film filling the trench is formed of an oxide film. The method of claim 7, wherein the active area protection spacer is formed of a nitride film. 10. The method of claim 8 or 9, wherein the semiconductor device is a DRAM device. The method of claim 7, wherein the oxide film penetrating into the active region is formed under the capacitor node junction.