KR20030090059A - bipolar transistor fabricating method - Google Patents
bipolar transistor fabricating method Download PDFInfo
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- KR20030090059A KR20030090059A KR1020020028044A KR20020028044A KR20030090059A KR 20030090059 A KR20030090059 A KR 20030090059A KR 1020020028044 A KR1020020028044 A KR 1020020028044A KR 20020028044 A KR20020028044 A KR 20020028044A KR 20030090059 A KR20030090059 A KR 20030090059A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 241000047703 Nonion Species 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 abstract 1
- 208000032368 Device malfunction Diseases 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 E14 ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005347 demagnetization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 바이폴라 트랜지스터 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method of manufacturing bipolar transistor devices.
최근에 하이 스피드용 실리콘-게르마늄 바이씨모오스 공정 개발이 점점 이슈화되고 있는 실정이다. 이에 따라 NPN 바이폴라 트랜지스터 소자의 에미터와 베이스 단자를 제조할 경우에 소자의 퍼포먼스 개선을 위해 에미터와 베이스간 오버랩 마진이 적당히 확보되어지는 것이 필요하게 된다.Recently, development of silicon-germanium bismosose process for high speed has been increasingly an issue. Accordingly, when manufacturing the emitter and the base terminal of the NPN bipolar transistor device, it is necessary to properly secure the overlap margin between the emitter and the base to improve the performance of the device.
통상의 바이폴라 트랜지스터 제조공정에서는 에미터와 베이스의 스페이스가 0.3 미크론 미터내외로 한정되는데, 베이스 영역위에 에미터 영역을 형성할 시에 건식 식각 및 습식 식각에 대한 디메지 및 언더 컷이 유발되는 문제점이 있다.In the conventional bipolar transistor manufacturing process, the space between the emitter and the base is limited to about 0.3 micron, and when the emitter region is formed on the base region, demagnetization and undercut for dry etching and wet etching are caused. have.
도 1 내지 도 4는 통상적인 바이폴라 트랜지스터 소자의 제조방법을 차례로 보여주는 공정단면도들이다. 도 1을 참조하면, NPN 소자를 형성하기 위해 NBL(2), 및 에피층(3) 구조를 형성하고, 실리콘-게르마늄 성장을 시킨 이후 공정진행을 행한 공정단면이 보여진다. 즉, 피형의 기판(1)에 NBL(2), 및 에피층(3),DN(4),SIC(5),N+(6)을 차례로 형성한 후, 실리콘-게르마늄 막(7)을 전면 성장시킨 다음 베이스 패드 산화막(8)의 패터닝 공정 까지를 진행한 결과구조이다. 도 2를 참조하면, 베이스를 형성하기 위한 베이스 폴리실리콘(9)의 데포지션과 에미터 스페이서를 형성하기 위한 산화막(10)의 형성과정이 보여진다.1 to 4 are process cross-sectional views sequentially showing a method of manufacturing a conventional bipolar transistor device. Referring to FIG. 1, a cross-sectional view of the process of forming the NBL (2) and epi layer (3) structures to form the NPN device, and performing the process after growing the silicon-germanium is shown. That is, after forming the NBL (2), the epi layer (3), the DN (4), the SIC (5), and the N + (6) in order on the substrate 1 to be formed, the silicon-germanium film 7 is formed on the entire surface. After the growth, the patterning process of the base pad oxide film 8 was performed. Referring to FIG. 2, the deposition of the base polysilicon 9 for forming the base and the formation of the oxide film 10 for forming the emitter spacers are shown.
도 3을 참조하면, 에미터 윈도우(11)를 형성하기 위해 사진공정/산화막 건식식각/감광막 제거/베이스 폴리 건식 식각을 행하면, 도 3의 에미터 윈도우(11)의 형상이 나타난다. 이 때, 잔여 산화막 두께 관리가 크리티컬하게 요구되어진다.Referring to FIG. 3, when the photolithography process / oxide dry etching / photoresist removal / base poly dry etching is performed to form the emitter window 11, the shape of the emitter window 11 of FIG. 3 appears. At this time, residual oxide film thickness management is critically required.
도 4는 에미터 형성을 위해 산화막 1000Å, 폴리 실리콘 1000Å을 차례로 데포지션 한 후에 스페이서 식각과 산화막 습식식각 후의 결과단면을 보인 것이다. 여기서, 언더 컷(12)이 매우 심하게 발생되어 있는 것을 알 수 있다.Figure 4 shows the resulting cross-section after spacer etching and oxide film wet etching after deposition 1000nm oxide and 1000nm polysilicon in order to form the emitter. Here, it can be seen that the undercut 12 is generated very severely.
상기한 바와 같이 산화막 식각공정을 통해 실리콘-게르마늄 막(7)의 상부까지 산화막을 제거할 경우 습식식각의 특성에 기인하여 언더 컷이 필연적으로 발생하게 된다. 이러한 언더 컷이 발생되면 에미터와 베이스간의 스페이스가 감소하게되어 에미터 베이스간의 누설전류가 증가되고, 이에 따라 소자특성의 열화가 유발되는 문제점이 있다.As described above, when the oxide film is removed to the top of the silicon germanium film 7 through the oxide film etching process, undercut is inevitably generated due to the wet etching characteristics. When such an undercut occurs, the space between the emitter and the base is reduced and the leakage current between the emitter base is increased, thereby causing deterioration of device characteristics.
따라서, 본 발명의 목적은 종래의 문제를 해결할 수 있는 바이폴라 트랜지스터 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a bipolar transistor manufacturing method that can solve the conventional problems.
본 발명의 다른 목적은 에미터 패터닝 후에 진행하는 습식식각시 습식 식각에 의한 언더 컷을 최소화하는 바이폴라 트랜지스터 소자의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of fabricating a bipolar transistor device that minimizes undercuts due to wet etching during wet etching after emitter patterning.
본 발명의 또 다른 목적은 에미터와 베이스간의 스페이스를 최대한 확보하여 누설 전류에 의한 소자 동작 불량을 방지하고 소자 능력을 최대화할 수 있는 바이폴라 트랜지스터 소자의 에미터 형성방법을 제공함에 있다.It is still another object of the present invention to provide a method of forming an emitter of a bipolar transistor device capable of securing a maximum space between an emitter and a base to prevent device malfunction due to leakage current and to maximize device capability.
본 발명의 또 다른 목적은 에미터와 베이스간의 스페이스를 최대한 확보하여 에미터와 베이스간의 구조적인 문제에 의한 누설 패스를 차단할 수 있는 에미터 제조방법을 제공함에 있다.Still another object of the present invention is to provide an emitter manufacturing method capable of blocking a leakage path due to a structural problem between the emitter and the base by ensuring a maximum space between the emitter and the base.
본 발명의 또 다른 목적은 에미터 패터닝 후에 잔여 산화막에 이온주입을 진행하여 후속의 습식식각시 습식 식각율을 차별화하여 언더 컷을 최소화하는 방법을 제공함에 있다.Another object of the present invention is to provide a method of minimizing undercut by differentiating wet etch rate during subsequent wet etching by performing ion implantation on the remaining oxide film after emitter patterning.
상기한 목적들을 달성하기 위한 본 발명의 일 양태(one aspect)에 따라, 바이폴라 트랜지스터의 제조방법은, 에미터 패터닝 후에 잔여 산화막에 이온주입을진행하는 것에 의해 후속의 습식식각시 이온주입 산화막과 이온주입되지 않은 산화막에 대하여 습식 식각율 차이가 나도록 하여 실리콘-게르마늄 막의 언더 컷을 최소화하는 것에 의해, 에미터와 베이스간의 스페이스를 최대한 확보하여 누설 전류에 의한 소자 동작 불량을 방지하고 소자 능력을 최대화한다.According to one aspect of the present invention for achieving the above objects, a method of manufacturing a bipolar transistor, the ion implantation oxide film and the ion during the subsequent wet etching by performing ion implantation to the remaining oxide film after the emitter patterning Minimize the undercut of the silicon-germanium film by making the wet etch rate difference with respect to the non-implanted oxide film to maximize the space between the emitter and the base to prevent device malfunction due to leakage current and maximize device capability .
도 1 내지 도 4는 통상적인 바이폴라 트랜지스터 소자의 제조방법을 차례로 보여주는 공정단면도들1 to 4 are cross-sectional views sequentially showing a method of manufacturing a conventional bipolar transistor device.
도 5 내지 도 7은 본 발명의 실시 예에 따른 바이폴라 트랜지스터 소자의 제조방법을 보인 공정단면도들5 to 7 are process cross-sectional views illustrating a method of manufacturing a bipolar transistor device according to an exemplary embodiment of the present invention.
이하에서는 본 발명에 따른 바이폴라 트랜지스터 소자의 제조방법에 대한 바람직한 실시 예가 첨부한 도면을 참조로 상세히 설명될 것이다.Hereinafter, a preferred embodiment of a method of manufacturing a bipolar transistor device according to the present invention will be described in detail with reference to the accompanying drawings.
먼저, 본 발명에서는 이온주입 산화막과 이온주입되지 않은 산화막과의 식각 비율차를 최대화하여 종래의 언더컷 문제를 최소화한다. 언더컷을 최소화하여 에미터와 베이스간의 스페이스 능력을 최대화하면 누설 전류에 의한 소자 동작 불량이 방지되어 결국 트랜지스터 소자의 동작 퍼포먼스가 최대로 되는 것이다.First, the present invention minimizes the conventional undercut problem by maximizing the etching rate difference between the ion implantation oxide film and the ion implantation oxide film. Maximizing the space capability between emitter and base by minimizing undercut prevents device malfunction due to leakage current, resulting in maximum operating performance of transistor devices.
도 5 내지 도 7은 본 발명의 실시 예에 따른 바이폴라 트랜지스터 소자의 제조방법을 보인 공정단면도들이다.5 to 7 are process cross-sectional views illustrating a method of manufacturing a bipolar transistor device according to an exemplary embodiment of the present invention.
먼저, 도 5를 참조하면, 산화막 식각율을 차별화하여 스페이스 감소가 최소화되도록 하기 위해, 종래와 같이 도 1 및 도 2의 구조를 형성하고, 건식식각을 통하여 상부 산화막, 감광액, 및 중간 폴리실리콘 층을 제거한 후, 도 3의 결과물에 보여지는 잔여 산화막에 고농도 저에너지로 이온주입을 진행하는 공정이 보여진다. 여기서, 이온주입이 이루어진 영역과 이루어지지 아니한 영역은 습식 식각율에서 차이가 나게 된다. 본 발명에서는 산화막 식각율의 차를 이용하여 언더 컷을 최소화하여 에미터 베이스간의 수평 스페이스가 최대로 확보될 수 있도록 하는 것이다. 이 경우에 이온주입 조건은 고농도(~ E14 ions/㎠ 이상), 저에너지(10keV 내외)이고, 소오스 가스로는 As, BF2이다.First, referring to FIG. 5, in order to differentiate the oxide etch rate to minimize space reduction, the structures of FIGS. 1 and 2 are formed as in the related art, and the upper oxide, photoresist, and intermediate polysilicon layers are formed through dry etching. After the removal, the process of ion implantation at high concentration and low energy to the residual oxide film shown in the result of FIG. 3 is shown. Here, the region where the ion implantation is performed and the region where the ion implantation is not made are different in the wet etching rate. In the present invention, the undercut is minimized by using the difference in oxide etching rate so that the horizontal space between the emitter bases can be secured to the maximum. In this case, ion implantation conditions are high concentration (~ E14 ions / cm 2 or more), low energy (about 10 keV), and source gases are As and BF2.
도 6을 참조하면, 폴리 스페이서의 형성 후에 잔여 산화막(300Å 이내)을 습식식각을 통해 제거한 결과가 보여진다. 여기서, 습식식각에 의한 언더 컷이 참조부호 (13)에서와 같이 종래의 경우에 비해 감소됨을 알 수 있다. 결국, 본 발명에서는 이온주입을 행하여, 습식 식각시 수직과 수평방향의 식각율 변화를 유발하는 것에 의해 언더컷을 최소화한다. 그럼에 의해, 에미터 베이스간의 스페이스 감소가 최대로 억제되는 것이다.Referring to FIG. 6, the result of removing the residual oxide film (within 300 μs) by wet etching after forming the poly spacer is shown. Here, it can be seen that the undercut by the wet etching is reduced as compared with the conventional case as in reference numeral (13). As a result, in the present invention, ion implantation is performed to minimize the undercut by causing etch rate changes in the vertical and horizontal directions during wet etching. This minimizes the space reduction between emitter bases.
도 7은 에미터 형성 후 에미터 전극(14)을 형성하기 위한 폴리 데포지션 및 에미터 폴리 식각 공정을 진행한 결과를 보여준다. 후속 공정의 콘택 및 메탈 배선 공정을 추가로 진행하면 바이폴라 트랜지스터가 비로서 완성된다.7 shows the results of the poly deposition and emitter poly etching process for forming the emitter electrode 14 after the emitter is formed. Further contact and metallization processes in subsequent steps complete the bipolar transistor as a ratio.
상기한 설명에서는 본 발명의 바람직한 실시예 들을 도면을 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 아래의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the foregoing description, the preferred embodiments of the present invention have been described with reference to the drawings, but those skilled in the art can vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.
상기한 바와 같이, 이온주입 산화막과 이온주입되지 않은 산화막과의 식각 비율차를 최대화하여 종래의 언더컷 문제를 최소화하는 본 발명의 트랜지스터 제조방법에 따르면, 에미터와 베이스간의 스페이스 능력이 최대화됨에 따라 누설 전류에 의한 소자 동작 불량이 방지되어 소자의 동작 퍼포먼스가 최대로 되는 효과가 있다.As described above, according to the transistor manufacturing method of the present invention, which minimizes the conventional undercut problem by maximizing the etching rate difference between the ion implantation oxide film and the non-ion implantation oxide film, leakage as the space capability between the emitter and the base is maximized. The defective device operation due to the current is prevented, and the operation performance of the device is maximized.
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