KR20030083815A - Mutual interference and beat generation protection circuit of digital tuner being built-in demodulation ic - Google Patents

Abstract

PURPOSE: A circuit for preventing interference and bit generation of a digital tuner including a demodulation IC is provided to eliminate interference and bit generation in a tuner according to the second oscillation frequency of a tuner demodulator and the nth harmonic of the second crystal oscillator. CONSTITUTION: A circuit for preventing interference and bit generation of a digital tuner(110) grounds the first OSC(113) of the tuner and the second OSC(123) of a tuner demodulator(120) to common ground, and connects an inductor(130) between the second OSC of the tuner demodulator and the ground to eliminate interference and bit generation in the tuner according to the second oscillation frequency of the tuner demodulator and the nth harmonic of the second crystal oscillator(121).

Description

Mutual interference and bit generation prevention circuit of the demodulation IC built-in digital tuner {MUTUAL INTERFERENCE AND BEAT GENERATION PROTECTION CIRCUIT OF DIGITAL TUNER BEING BUILT-IN DEMODULATION IC}

The present invention relates to a digital tuner, and more particularly, the first OSC of the tuner section and the second OSC of the tuner demodulation section are grounded to a common ground, and then the tuner demodulation section is connected by connecting an inductor between the second OSC and the ground of the tuner demodulator section. The present invention relates to a circuit for preventing mutual interference and bit generation of a digital tuner with a demodulation IC for removing mutual interference and bit generation by the nth harmonic of the second oscillation frequency and the second quartz crystal.

The trend of current digital tuners is to embed demodulation ICs in the tuner. The digital tuner uses a separate digital and analog power supply to reduce the influence of each other, because the performance of the digital tuner is reduced due to interference between the tuner demodulator (digital signal processor) and the tuner (analog signal processor). The circuit is designed on the principle of separation.

For example, QAM demodulation ICs used in digital cable tuners include chips that use 28.9MHz crystal oscillators and 4MHz crystal oscillators. The system clock of the QAM demodulation IC is about 58 MHz, and the Philips QAM demodulation IC uses 14 times of 4 MHz and the ST demodulation IC of 2 times. The tuner also uses a PLL IC in addition to the QAM demodulation IC, which uses a 4MHz crystal oscillator from OSC.

However, since the conventional tuner has two crystal oscillators required by the QAM demodulation IC and the PLL IC, a beat occurs due to the interference between the crystal harmonics of the demodulation IC of the demodulation IC and the signal of the OSC, resulting in VHF LOW or VHF HIGH (50 MHz). There is a problem that seriously affects the performance of ~ 450MHz) channel, but in order to solve this problem, power and ground must be completely separated in a small digital tuner, but this is also impossible due to the narrow space.

Accordingly, an object of the present invention is to solve the above problems, by grounding the first OSC of the tuner unit and the second OSC of the tuner demodulator to a common ground and then connecting the inductor between the second OSC and the ground of the tuner demodulator. The second oscillation frequency of the demodulator and the n-th harmonic of the second crystal oscillator are used to exclude mutual interference and bit generation from the tuner unit.

1 is a block circuit diagram schematically showing a configuration of a circuit for preventing interference and bit generation in a digital tuner with a demodulation IC according to the present invention.

<Explanation of symbols for main parts of the drawings>

110: tuner portion 111, 121: first and second crystal oscillator

113, 123: 1st, 2 OSC115: PLL IC

120: tuner demodulation unit 125: demodulation IC

130: inductor

Features of the present invention for achieving the above object,

A first OSC generating a first oscillation frequency through a first quartz crystal oscillator and a first oscillation frequency generated from the first OSC are applied to compare a first oscillation frequency with a reference frequency to obtain a voltage according to a phase difference between the two frequencies. A demodulator IC configured to perform demodulation by receiving a tuner unit including a generated PLL IC, a second OSC generating a second oscillation frequency through a second quartz crystal, and a second oscillation frequency generated from the second OSC. In the digital tuner composed of a tuner demodulator comprising:

Ground the first OSC of the tuner and the second OSC of the tuner demodulator to a common ground;

An inductor is coupled between the second OSC of the tuner demodulator and ground to eliminate mutual interference and bit generation by the second oscillation frequency of the tuner demodulator and the nth harmonic of the second quartz crystal. It is done.

Hereinafter, the configuration and operation of the mutual interference and bit generation prevention circuit of the demodulation IC built-in digital tuner according to the present invention will be described in detail with reference to FIG.

1 is a block circuit diagram schematically showing a configuration of a mutual interference and bit generation prevention circuit of a digital tuner with a demodulation IC according to the present invention.

Referring to FIG. 1, the mutual interference and bit generation prevention circuit 100 of the demodulation IC built-in digital tuner according to the present invention includes a tuner unit 110, a tuner demodulator 120, and an inductor 130.

The tuner unit 110 receives an oscillation frequency generated from the first OSC 113 and the oscillation frequency generated by the first OSC 113 through the first quartz crystal 111 to generate an oscillation frequency and a reference frequency. Comparing with the PLL IC 115 for generating a voltage according to the phase difference of the two frequencies.

The tuner demodulator 120 is configured to generate an oscillation frequency of 20 to 30 MHz (OFDM: 20.48 MHz, VSB: 25 MHz, QAM: 28.92 MHz) through the second quartz crystal 121, and a second And a demodulation IC 125 for performing demodulation by receiving the oscillation frequency generated from the OSC 123. Here, the first OSC 113 of the tuner unit 110 and the second OSC 123 of the tuner demodulator 120 are grounded to a common ground, respectively.

The inductor 130 excludes interference and bit generation from the tuner unit 110 by the second oscillation frequency of the second OSC 123 of the tuner demodulator 120 and the nth harmonic of the second quartz crystal oscillator 121. It is connected between the second OSC 123 of the tuner demodulator 120 and the ground. Here, the reason why the inductor 130 is installed is because the frequency characteristic of the inductor 130 does not pass well as the frequency increases, and as the inductor value increases, the frequency does not pass through the second OSC 123. Mutual interference can be reduced by preventing the second oscillation frequency and the nth harmonic of the second quartz crystal 121 from being passed to the ground.

Hereinafter, an operation of a circuit for preventing interference and bit generation of a digital tuner with a demodulation integrated circuit according to the present invention will be described in detail with reference to FIG. 1.

First, when an oscillation frequency of 4 MHz generated by the first quartz crystal oscillator 111 of the first OSC 113 is applied to the PLL IC 115, the PLL IC 115 compares the oscillation frequency with a reference frequency and phase difference between the two frequencies. Generate the voltage according to and output it to the other end.

Meanwhile, when an oscillation frequency of 28.92 MHz generated from the second crystal oscillator 121 of the second OSC 123 is applied to the demodulation IC 125, the demodulation IC 125 demodulates the input RF signal.

In this case, since the first OSC 113 and the second OSC 123 are grounded to the common ground, mutual interference and bits may be generated by the oscillation frequency generated by each crystal oscillator, but the second OSC 123 and the ground may be generated. Since the inductor is connected to each other, the oscillation frequency of the second OSC 123 is prevented from entering the ground side.

This prevents bits from being generated due to interference caused by the use of two crystal oscillators, and further miniaturizes the digital tuner by using one common ground.

As described above, according to the mutual interference and bit generation prevention circuit of the demodulation IC built-in digital tuner according to the present invention, the first OSC of the tuner section and the second OSC of the tuner demodulation section are grounded to a common ground and then the second OSC of the tuner demodulation section is used. By connecting the inductor between the ground and the ground, the second oscillation frequency of the tuner demodulator and the nth harmonic of the second modified oscillator may exclude or minimize mutual interference and bit generation in the tuner unit.

Claims (1)

A first OSC generating a first oscillation frequency through a first quartz crystal oscillator and a first oscillation frequency generated from the first OSC are applied to compare a first oscillation frequency with a reference frequency to obtain a voltage according to a phase difference between the two frequencies. A demodulator IC configured to perform demodulation by receiving a tuner unit including a generated PLL IC, a second OSC generating a second oscillation frequency through a second quartz crystal, and a second oscillation frequency generated from the second OSC. In the digital tuner composed of a tuner demodulator comprising: Ground the first OSC of the tuner and the second OSC of the tuner demodulator to a common ground; An inductor is coupled between the second OSC of the tuner demodulator and ground to eliminate mutual interference and bit generation by the second oscillation frequency of the tuner demodulator and the nth harmonic of the second quartz crystal. A circuit for preventing interference and bit generation in a digital tuner with a built-in demodulation IC.