KR20030083364A - Plasma display panel - Google Patents

Abstract

PURPOSE: A plasma display panel is provided to minimize an erroneous discharge caused due to the high temperature during the operation of the plasma display panel. CONSTITUTION: A plasma display panel comprises an upper substrate arranged in a discharge cell, and which has a scan electrode(48Y) and a sustain electrode(48Z) formed on the upper substrate; an upper dielectric layer(34) formed on the upper substrate in such a manner that first areas have thicknesses lower than the thickness of the second area, wherein the upper dielectric layer accumulates the wall charge generated during a plasma discharge into the first areas; and a protective film(36) formed on the upper dielectric layer.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel for minimizing erroneous discharge due to a high temperature state when driving the plasma display panel.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

1 and 2, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan electrode 28Y and a sustain electrode 28Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided.

Each of the scan electrodes 28Y and the sustain electrodes 28Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y and 13Y formed on one edges of the transparent electrodes. 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 28Y and the sustain electrode 28Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 28Y and the sustain electrode 28Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell from the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied.

For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 3, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

4 is a diagram illustrating a driving waveform of a PDP supplied to the subfields shown in FIG. 3, and FIGS. 5A to 5C are diagrams showing wall charge states when driving a PDP at room temperature.

In Fig. 4, Y represents a scan electrode and Z represents a sustain electrode. And X represents an address electrode.

4 and 5, the PDP is divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the ramp-up waveform RP is applied to all the scan electrodes Y simultaneously. This ramp-up waveform RP causes a slight discharge in the cells of the full screen to generate wall charges in the cells. After the ramp-up waveform RP is supplied in the set-down period, the ramp-down waveform -RP falling at a positive voltage lower than the peak voltage of the ramp-up waveform RP is simultaneously applied to the scan electrodes Y. .

The ramp-down waveform (-RP) generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly retaining wall charges required for address discharges in the full screen cells. Let's go.

In the address period, the negative scan pulse SP is sequentially applied to the scan electrodes Y, and the positive data pulse DP is applied to the address electrodes X. As the voltage difference between the scan pulse SP and the data pulse DP and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied as shown in FIG. 5A. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive polarity DC voltage Zdc of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses SUSPy and SUSPz are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is added between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulses (SUSPy, SUSPz) are applied while the wall voltage and the sustain pulses (SUSPy, SUSPz) in the cell are added. As in 5b, sustain discharge occurs in the form of surface discharge. At this time, wall charges are formed on the scan electrode Y and the sustain electrode Z as shown in FIG. 5C by the sustain discharge. Finally, after the sustain discharge is completed, an erase ramp waveform EP having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

On the other hand, when the temperature rises during PDP driving, wall charges are reduced on the scan electrode Y and the address electrode X. FIG. The rise in temperature leads to an increase in current and at the same time promotes the activation of the wall charge particles. That is, part of the wall charges formed on the surface of the electrode due to the sustain discharge between the scan electrode (Y) and the sustain electrode (Z) is separated between the electrodes (Y, Z) due to the temperature rise. In this case, the charge accumulated due to the sustain discharge disappears due to the self erase discharge as shown in FIG. 6. That is, unnecessary discharge is caused between the scan electrode Y and the sustain electrode Z.

In particular, as the gap between the scan electrode (Y) and the sustain electrode (Z) goes toward the gap (Gap), the dissipation of wall charges is increased, and as the accumulation of wall charges is accumulated on the gap side, the discharge voltage decreases. The longer the loss of wall charge is, the longer the loss becomes. This means that the wall charge amount during data writing during T1 and the wall charge amount during data writing during TN as shown in FIG. 7B may be different in the address period. That is, the longer the scanning time is, the higher the wall charge loss is, and the data voltage for the last address discharge is inevitably increased. This phenomenon is more pronounced as the temperature rises.

In order to solve this problem, another PDP of the prior art has changed the characteristics of the upper dielectric layer 14 formed on the upper substrate. First, as shown in FIG. 8, the capacitance C is increased by reducing the thickness d1> d2 of the upper dielectric layer 14 to prevent high temperature mis-discharge. However, PDP according to the first case is effective in preventing high temperature mis-discharge, but has a disadvantage in that dielectric breakdown occurs due to a lower potential barrier.

Second, as shown in FIG. 9, a large dielectric constant (ε1 <ε2) is used as the upper dielectric layer 14 to increase the capacitance C to prevent high temperature mis-discharge. However, PDP according to the second case, although slightly effective in preventing high temperature discharge, did not cause a change in overall characteristics.

Accordingly, an object of the present invention is to provide a plasma display panel which prevents erroneous discharge due to high temperature driving by increasing the capacitance by lowering the thickness of the dielectric layer only at a portion where wall charges are accumulated due to the address discharge.

Another object of the present invention is to provide a plasma display panel in which a change in capacitance is adjusted in an electrode pad portion.

It is still another object of the present invention to provide a plasma display panel in which a change in capacitance is adjusted in a panel terminal unit as well as a display panel.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a cross-sectional view of discharge cells of the plasma display panel illustrated in FIG. 1.

3 illustrates a subfield included in one frame of a conventional plasma display panel.

FIG. 4 is a waveform diagram showing driving waveforms applied to respective electrodes during the subfields shown in FIG.

5A to 5C are diagrams showing wall charge states during sustain discharge in the discharge cells of the plasma display panel according to the related art.

6 is a view showing the state of the wall charge when the discharge cell of the plasma display panel according to the prior art at high temperature.

7A and 7B are drive waveform diagrams showing an address discharge during T1 and TN in the address period of the subfield shown in FIG.

8 is a view showing a change in thickness of the upper dielectric layer in the PDP according to the prior art.

9 is a view showing the change in dielectric constant of the upper dielectric layer in the PDP according to the prior art.

10 is a perspective view illustrating a PDP according to a first embodiment of the present invention.

FIG. 11 is a plan view of the top plate illustrated in FIG. 10.

12 is a plan view of a top plate in a PDP according to a second embodiment of the present invention.

13 is a plan view of a top plate in a PDP according to a third embodiment of the present invention.

14 is a plan view of a PDP according to a fourth embodiment of the present invention.

15 is a cross-sectional view taken along the line "A-A '" in FIG. 14.

16 is a plan view of a PDP according to a fifth embodiment of the present invention.

FIG. 17 is a cross-sectional view taken along the line B-B 'in FIG. 14.

<Description of Symbols for Main Parts of Drawings>

2,76,96: top plate 4,74,92: bottom plate

10,30,60,80: Upper substrate 12Y, 12Z, 32Y, 32Z, 62,82: Transparent electrode

13Y, 13Z, 33Y, 33Z, 63,83: Metal Bus Electrode

14,34: upper dielectric layer 16,36: protective film

18: address electrode 20X: address electrode

22: lower dielectric layer 24: partition wall

26: phosphor layer 28Y, 48Y: scan electrode

28Z, 48Z: Sustain electrodes 52a, 54a, 56a: first upper dielectric portion

52b, 54b, 54c, 56b: second upper dielectric portion

64, 84: metal bus electrode pads 66a, 86a: first upper dielectric layer

66b, 86b: second upper dielectric layer 68a, 68b: metal electrode

70,90: Protective film 72: Seal material

In order to achieve the above objects, a plasma display panel according to an exemplary embodiment of the present invention is a plasma display panel including a plurality of discharge cells, the upper substrate having a scan electrode and a sustain electrode arranged in parallel in the discharge cell, and the upper substrate. An upper dielectric layer formed on the upper dielectric layer, the upper dielectric layer having predetermined first regions formed on the upper dielectric layer having a lower thickness than the second region except the first region to accumulate a large amount of wall charges generated during plasma discharge in the first regions; It is characterized by including a protective film.

In the present invention, a lower substrate having an address electrode formed to intersect the scan electrode and the sustain electrode, a lower dielectric layer entirely coated on the lower substrate, and a partition wall vertically formed on the lower substrate to divide each discharge cell. And a phosphor formed on the inner wall of the partition and the surface of the lower dielectric layer in order to be excited by the light generated by the plasma discharge and to emit light.

The first regions having a lower thickness than the second region of the upper dielectric layer in the present invention are characterized by any one of a pattern mask and a laser.

The predetermined first area of the present invention is characterized in that the center portion of the upper substrate to include a gap between the scan electrode and the sustain electrode.

The predetermined first regions of the present invention may include a gap region between the scan electrode and the sustain electrode, and an electrode surface region formed on the scan electrode and the sustain electrode adjacent to the gap region, respectively.

The predetermined first region in the present invention may be an upper region of the scan electrode adjacent to a gap region between the scan electrode and the sustain electrode.

According to another embodiment of the present invention, a plasma display panel includes a panel display unit for displaying an image by plasma discharge, and a panel terminal unit connected to an upper edge of the panel display unit to supply power and driving signals; The panel terminal portion extends from the panel display portion and is sequentially stacked on the upper substrate and the metal bus electrode pads, a first upper dielectric layer formed on the metal bus electrode pads to form capacitance, and the first upper dielectric layer. It is formed to surround the side and edges, characterized in that it comprises a metal electrode to increase the total capacitance, including the capacitance in the panel display.

In the present invention, the metal electrode is formed only on the entire upper surface of the first upper dielectric layer.

The panel display unit in the present invention is composed of a top plate, a bottom plate and a material for sealing the top / bottom plate; The upper plate may include a scan electrode and a sustain electrode on which the transparent electrode and the metal bus electrode are arranged side by side on the upper substrate, and a second upper dielectric layer formed to cover the scan electrode and the sustain electrode to accumulate wall charges generated during plasma discharge. And a protective film formed on the second upper dielectric layer.

In the present invention, the lower plate may include a lower substrate on which an address electrode is formed to intersect the scan electrode and the sustain electrode, a lower dielectric layer entirely coated on the lower substrate, and vertically formed on the lower substrate to form respective discharge cells. And a partition formed on the inner wall of the partition and the surface of the lower dielectric layer to be excited and emitted by the light generated by the plasma discharge.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 10 to 17.

10 is a perspective view illustrating a PDP according to a first embodiment of the present invention. FIG. 11 is a plan view of the top plate illustrated in FIG. 10.

In FIG. 10, since the lower plate in the PDP according to the first embodiment of the present invention is substantially the same as the lower plate 4 shown in FIG. 1, the same reference numerals are used, and detailed description thereof will be omitted.

In the configuration of FIG. 10, the PDP according to the first embodiment of the present invention is largely divided into an upper plate 2 and a lower plate 4.

In the configuration of FIGS. 10 and 11, the upper plate 2 includes the scan electrode 48Y and the sustain electrode 48Z formed on the upper substrate 30, and the scan electrode 48Y and the sustain electrode 48Z side by side. An upper dielectric layer 34 and a passivation layer 36 are sequentially stacked on the formed upper substrate 30.

Each of the scan electrodes 48Y and the sustain electrodes 48Z has a line width smaller than that of the transparent electrodes 32Y and 32Z and the transparent electrodes 32Y and 32Z, and the metal bus electrodes 33Y, which are formed at one edges of the transparent electrodes, respectively. 33Z). The transparent electrodes 32Y and 32Z are usually formed on the upper substrate 30 by indium tin oxide (ITO). The metal bus electrodes 33Y and 33Z are usually made of metal such as chromium (Cr) or the like. It is formed on the transparent electrodes 32Y and 32Z and serves to reduce the voltage drop caused by the transparent electrodes 32Y and 32Z having high resistance.

The upper dielectric layer 34 includes the first upper dielectric portion 52a formed at the top edge and a gap between the scan electrode 48Y and the sustain electrode 48Z. The second upper dielectric part 52b is formed to have a thickness lower than that of the dielectric part 52a. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 34. At this time, the second upper dielectric portion 52b is formed of a pattern mask or a laser at the same thickness as the first upper dielectric portion 52a.

The passivation layer 36 prevents damage to the upper dielectric layer 34 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 36, magnesium oxide (MgO) is usually used.

In the PDP having such a configuration, wall charges are formed on the surface of the scan electrode 48Y and the sustain electrode 48Z in response to the address discharge caused by the counter discharge. In particular, wall charges are formed in a large amount on the surfaces of the gaps between the scan electrodes 48Y and the sustain electrodes 48Z and the surfaces of the scan electrodes 48Y and the sustain electrodes 48Z adjacent to the surface discharges after the counter discharges. Therefore, in the PDP according to the first embodiment of the present invention, a large amount of wall charges is formed on the second upper dielectric portion 52b corresponding to the surface of the scan electrode 48Y and the sustain electrode 48Z, as shown in FIG. .

Accordingly, the PDP according to the first embodiment of the present invention promotes activation of the wall charges due to the temperature rise, so that even if the accumulated charges are lost by the self-discharge discharge, the scan electrodes 48Y are prevented by the second upper dielectric portion 52b. ) And a large amount of wall charges can be left in the gap region between the sustain electrode 48Z and the sustain electrode 48Z. As a result, in the PDP according to the first embodiment of the present invention, even though some wall charges due to self-erasing discharge disappear, the data voltage according to the difference in the wall charges of the initial scan T1 and the last scan TN in the address period is different. The size can be reduced.

12 is a plan view of a top plate in a PDP according to a second embodiment of the present invention.

Referring to FIG. 12, the PDP according to the second embodiment of the present invention shows an upper dielectric layer 34 formed in the gap region between the scan electrode 48Y and the sustain electrode 48Z in FIG. It is formed at the same height as the first upper dielectric portion 52a.

That is, the upper dielectric layer 34 includes a first upper dielectric portion 54a formed at the top edge and a gap region between the scan electrode 48Y and the sustain electrode 48Z, and the scan electrode 48Y and the sustain electrode. The second upper dielectric parts 54b and 54c formed on the scan gap 48Y and the sustain electrode 48Z adjacent to the gap region between the 48Z and lower than the first upper dielectric part 54a, respectively, are formed. Equipped. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 34. In this case, the second upper dielectric parts 54b and 54c are formed by a pattern mask or a laser at the same thickness as the first upper dielectric part 54a. Except for the upper dielectric layer 34, the remaining components are formed in the same manner as in FIG.

The PDP having such a structure includes second upper dielectric portions 54b and 54c, which are portions in which wall charges are formed on the surfaces of the scan electrode 48Y and the sustain electrode 48Z in accordance with the address discharge caused by the counter discharge. This is to form a large amount of wall charge in). This is because the first embodiment of reducing the thickness of the upper dielectric layer 34 in the gap Gap between the scan electrode 48Y and the sustain electrode 48Z may cause a decrease in efficiency. As a result, the PDP according to the second embodiment of the present invention can prevent erroneous discharge by reducing wall charge loss during high temperature driving.

13 is a plan view of a top plate in a PDP according to a third embodiment of the present invention.

Referring to FIG. 13, the PDP according to the third embodiment of the present invention includes a second upper dielectric part 54c formed on the surface of the sustain electrode 48 as compared with FIG. 12. It is formed at the same height.

In detail, the upper dielectric layer 34 includes a first upper dielectric part 56a coated on the upper substrate 30 to cover the scan electrode 48Y and the sustain electrode 48Z, and the scan electrode 48Y. The second upper dielectric part 56b formed by a pattern mask or a laser having a thickness lower than that of the first upper dielectric part 56a on the gap region between the and sustain electrode 48Z and the adjacent scan electrode 48Y, respectively. It is provided. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 34. Except for the upper dielectric layer 34, the remaining components are formed in the same manner as in FIG.

In the PDP having such a configuration, wall charges are formed on the surface of the scan electrode 48Y and the sustain electrode 48Z in response to the address discharge caused by the counter discharge. At this time, a large amount of wall charge is formed in the second upper dielectric part 56b formed on the surface of the scan electrode 48Y. This prevents the possibility of lowering the efficiency of the first embodiment in which the thickness of the upper dielectric layer 34 is reduced in the gap between the scan electrode 48Y and the sustain electrode 48Z, and the wall charge generated during the selective writing. The loss can be reduced. As a result, the PDP according to the third embodiment of the present invention can prevent mis-discharge by reducing wall charge loss during high temperature driving.

FIG. 14 is a view showing a plan view of a PDP according to a fourth embodiment of the present invention, and FIG. 15 is a view showing a section cut along the line "A-A '" in FIG.

14 and 15, when the PDP according to the fourth embodiment of the present invention reduces the thickness of the upper dielectric layer 34 in the display area of the PDP according to the prior art and the first to third embodiments of the present invention. In order to prevent the possibility of causing dielectric breakdown, the capacitance of the panel is increased in the electrode pad portion, which is a region other than the display region.

The PDP according to the fourth embodiment of the present invention is divided into a panel display portion P1 and a panel terminal portion P2. First, the panel display unit P1 has the same structure as described with reference to FIG. 1. To explain this, the panel display unit P1 is formed of a seal material 72 that seals the upper plate 76, the lower plate 74, the upper plate, and the lower plate to form a discharge cell. The upper plate 76 includes transparent electrodes 62Y, 62Z; 62 constituting a scan electrode or a sustain electrode formed side by side on the upper substrate 60, and metal bus electrodes 63Y, 63Z; 63 formed at an edge on the transparent electrode. ), A metal bus electrode pad 64 extending from the metal bus electrode 63 to the panel terminal portion P2, the transparent electrode 62, the metal bus electrode 63 and the metal bus electrode pad 64. The first upper dielectric layer 66a and the passivation layer 70 are sequentially stacked on the upper substrate 60 so as to cover the upper substrate 60.

The panel terminal portion P2 may include a metal bus electrode pad 64 formed on the upper substrate 60 to extend from the panel display portion P1, and a second upper dielectric layer formed to cover a predetermined region of the metal bus electrode pad 64. Metal electrodes 68a and 68b formed to cover the side surfaces of the second upper dielectric layer 66b and the flexible printed circuit (FPC) for supplying an external driving signal. It is composed of In this case, the metal electrodes 68a and 68b are formed on the upper substrate 60 to have a '┌' or '또는' shape to surround the second upper dielectric layer 66b.

In addition, the first upper dielectric layer 66a and the second upper dielectric layer 66b may be configured to have different thicknesses and dielectric constants.

The PDP according to the fourth embodiment of the present invention having such a configuration has a first capacitance C1 formed in the first upper dielectric layer 66a in the panel display portion P1 and a second upper dielectric layer in the panel terminal portion P2. The total capacitance is increased by the second capacitance C2 formed at 66b. As a result, the PDP according to the fourth embodiment of the present invention forms a large amount of wall charges on the top plate surface. This can be seen as Equation 1, wherein the first and second capacitances C1 and C2 have a series connection configuration.

Here, Ca is a capacitance formed between the first metal electrode 68a and the metal bus electrode pad 64, and Cb is a capacitance formed between the second metal electrode 68b and the metal bus electrode pad 64.

As a result, the PDP according to the fourth embodiment of the present invention forms a metal electrode 68 on a predetermined region of the side surface and the upper surface of the second upper dielectric layer 66b of the panel terminal portion P2 to increase the total capacitance applied to the display panel. In the high temperature driving, the wall charge loss due to the self-erasing discharge is compensated for, thereby minimizing the erroneous discharge.

FIG. 16 is a view showing a plan view of a PDP according to a fifth embodiment of the present invention, and FIG. 17 is a view showing a section cut along the line “B-B '” in FIG. 14.

16 and 17, when the PDP according to the fifth embodiment of the present invention decreases the thickness of the upper dielectric layer 34 in the display area of the PDP according to the prior art and the first to third embodiments of the present invention. In order to prevent the possibility of causing dielectric breakdown, the capacitance of the panel is increased in the electrode pad portion, which is a region other than the display region. In particular, the PDP according to the fifth embodiment of the present invention is configured such that the capacitance formed in the panel terminal portion P2 is connected in series instead of the parallel connection type in the fourth embodiment.

The PDP according to the fifth embodiment of the present invention is divided into a panel display portion P1 and a panel terminal portion P2. First, the panel display unit P1 has the same structure as described with reference to FIG. 1. To illustrate this, the panel display unit P1 is formed of a seal material 92 that seals the upper plate 96, the lower plate 94, the upper plate, and the lower plate to form a discharge cell. The upper plate 96 includes transparent electrodes 82Y, 82Z; 82 constituting a scan electrode or a sustain electrode formed side by side on the upper substrate 80, and metal bus electrodes 83Y, 83Z; 83 formed at an edge on the transparent electrode. ), A metal bus electrode pad 84 extending from the metal bus electrode 83 to the panel terminal portion P2, the transparent electrode 82, the metal bus electrode 83, and the metal bus electrode pad 84; The first upper dielectric layer 86a and the passivation layer 90 are sequentially stacked on the upper substrate 80 so as to cover the upper substrate 80.

The panel terminal portion P2 may include a metal bus electrode pad 84 formed on the upper substrate 80 to extend from the panel display portion P1, and a second upper dielectric layer 86b formed to cover the metal bus electrode pad 84. And a second electrode 88 formed on the second upper dielectric layer 86b. In addition, the first upper dielectric layer 86a and the second upper dielectric layer 86b may be configured with different thicknesses and dielectric constants.

The PDP according to the fifth embodiment of the present invention having such a configuration has a first capacitance C1 formed in the first upper dielectric layer 86a in the panel display portion P1 and a second upper dielectric layer in the panel terminal portion P2. The total capacitance is reduced by the second capacitance C2 formed at 66b. This can be seen as Equation 2, wherein the first capacitance C1 and the second capacitance C2 have a parallel connection configuration.

Accordingly, the PDP according to the fifth embodiment of the present invention forms a metal electrode 88 on the second upper dielectric layer 86b of the panel terminal portion P2 to reduce the total capacitance applied to the display panel, thereby self-erasing at high temperature. Compensation for the wall charge loss due to the discharge can minimize the mis-discharge.

The PDPs according to the fourth and fifth embodiments of the present invention can induce a total capacitance change applied to the panel by changing the thickness and dielectric constant of the second upper dielectric layer in the panel terminal portion P2. The total capacitance can be adjusted according to the state of the upper dielectric layer formed in P2), thereby preventing mis-discharge caused by high temperature driving.

As described above, the plasma display panel according to the present invention lowers the thickness of the upper dielectric layer only at the portion where the wall charges are accumulated, thereby reducing the change in the discharge voltage such as the data voltage and the wall charges even in the wall charge loss generated during high temperature driving. Misdischarge caused by loss can be minimized. In addition, the plasma display panel according to the present invention can adjust the total capacitance value within a range that does not concern the breakdown by controlling the change in capacitance at the panel terminal portion.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

In the plasma display panel composed of a plurality of discharge cells, An upper substrate on which a scan electrode and a sustain electrode are formed in parallel in the discharge cell; An upper dielectric layer having predetermined first regions on the upper substrate having a lower thickness than the second region except for the first region to accumulate a large amount of wall charges generated during plasma discharge in the first regions; And a passivation layer formed on the upper dielectric layer. The method of claim 1, A lower substrate having an address electrode formed to intersect the scan electrode and the sustain electrode; A lower dielectric layer entirely coated on the lower substrate; A partition wall formed vertically on the lower substrate to divide each discharge cell; And a phosphor formed on the inner wall of the partition and the surface of the lower dielectric layer to be excited by light generated by the plasma discharge and to emit light. The method of claim 1, And the first regions having a thickness lower than the second region of the upper dielectric layer are formed by any one of a pattern mask and a laser. The method of claim 2, And the predetermined first region is a central portion of the upper substrate to include a gap between the scan electrode and the sustain electrode. The method of claim 2, The predetermined first regions may include a gap region between the scan electrode and the sustain electrode; And an electrode surface region formed on the scan electrode and the sustain electrode adjacent to the gap region. The method of claim 2, And the predetermined first region is an upper region of the scan electrode adjacent to a gap region between the scan electrode and the sustain electrode. A panel display unit which displays an image by plasma discharge, A panel terminal part connected to an upper edge of the panel display part to supply power and driving signals; The panel terminal portion extends from the panel display portion and is sequentially stacked on the upper substrate and the metal bus electrode pads; A first upper dielectric layer formed on the metal bus electrode pad to form capacitance; And a metal electrode formed to surround sidewalls and edges of the first upper dielectric layer to increase the total capacitance including the capacitance in the panel display unit. The method of claim 7, wherein The metal electrode is connected to a flexible printed circuit (FPC) for supplying an external drive signal. The method of claim 8, And the metal electrode constitutes a parallel capacitor with the metal bus electrode pad. The method of claim 8, And the metal electrode is formed only on the entire upper surface of the first upper dielectric layer. The method of claim 10, And said metal electrode constitutes a series capacitor with said metal bus electrode pad. The method of claim 7, wherein The panel display unit is composed of an upper plate, a lower plate, and a material for sealing the upper and lower plates; The upper plate may include a scan electrode and a sustain electrode on which the transparent electrode and the metal bus electrode are formed side by side on the upper substrate; A second upper dielectric layer formed to cover the scan electrode and the sustain electrode to accumulate wall charges generated during plasma discharge; And a passivation layer formed on the second upper dielectric layer. The method of claim 12, The lower plate may include a lower substrate having an address electrode formed to intersect the scan electrode and the sustain electrode; A lower dielectric layer entirely coated on the lower substrate; A partition wall formed vertically on the lower substrate to divide each discharge cell; And a phosphor formed on the inner wall of the partition and the surface of the lower dielectric layer to be excited by light generated by plasma discharge and to emit light.