KR20030075343A - Circuit for driving liquid crystal display panel and method for driving thereof - Google Patents

Abstract

PURPOSE: A circuit for driving an LCD panel and a method for driving the LCD panel are provided to discharge electric charges of a liquid crystal capacitor via a gate driving circuit when the external power supply is blocked, thereby removing the after-images generated by the residual charges. CONSTITUTION: A circuit for driving an LCD panel includes an LCD panel(110) formed with pixels formed of TFTs(111) and liquid crystal capacitors(112) connected to the TFTs in the matrix shape, gate and source driving circuits(140,150) mounted around the LCD panel for driving the LCD panel, a timing control circuit(160) for generating first and second control signals(161,162) by receiving image data signals(r,g,b), vertical and horizontal synchronizing signals(HSYNC,VSYNC) and clock signals(CLK). The first control signal is applied to a gate driving voltage generator(170) and the second control signal is applied to the source driving circuit. The gate driving voltage generator is driven by the first and second power voltages(VON, VOFF) from a DC/DC converter(180) and generates first and second clock signals(CK,CKB) and a starting signal(ST) to output to the gate driving circuit. The DC/DC converter is connected to a power-off discharging circuit(175) which generates a third power voltage(VONA) for keeping a high level state for a predetermined time even when the first power voltage is discharged.

Description

Liquid crystal display panel driving circuit and driving method thereof {CIRCUIT FOR DRIVING LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR DRIVING THEREOF}

The present invention relates to a driving circuit of a liquid crystal display panel and a driving method thereof, and more particularly, to a driving circuit of a liquid crystal display panel capable of preventing an afterimage phenomenon in which a screen is not erased even after power supplied to the liquid crystal display panel is cut off. It relates to a driving method thereof.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. Therefore, in order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface between the user and the information processing apparatus is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage compared to a CRT type display device, and is capable of full color and is emerging as a next generation display device.

In general, an LCD includes a display unit for displaying an image and a backlight unit for providing light to the display unit.

1 is a view schematically showing a conventional liquid crystal display device.

Referring to FIG. 1, a display unit includes a liquid crystal display panel in which a plurality of pixels including a thin film transistor (TFT) 11 and a liquid crystal capacitor 12 connected to the TFT 11 are formed in a matrix form. 10) and driving units 20 and 30 for driving the liquid crystal display panel 10.

The liquid crystal display panel 10 includes a plurality of gate lines G1 to Gn extending in a low direction and a plurality of data lines D1 to Dm extending in a column direction. The gate electrode 11a of the TFT 11 is commonly connected to the gate lines G1 to Gn in a row direction, and the source electrode 11b is commonly connected to the data lines D1 to Dm in a column direction. do. The drain electrode 11c of the TFT 11 is connected to the liquid crystal capacitor 12.

On the other hand, a driving unit including a gate driving circuit 20 and a source driving circuit 30 is mounted around the liquid crystal display panel 10. Specifically, the gate driving circuit 20 is connected to one end of the plurality of gate lines G1 to Gn to sequentially apply gate driving signals to the plurality of gate lines G1 to Gn. In addition, the source driving circuit 30 is connected to one end of the plurality of data lines D1 to Dm to sequentially apply data driving signals to the plurality of data lines D1 to Dm.

The timing control circuit 40 receives the image data signal RGB, the vertical and horizontal synchronization signals HSYNC, VSYNC, and the clock signal CLK to receive the first control signal 41 and the second control signal 42. Occurs.

Here, the first control signal 41 output from the timing control circuit 40 is provided to the gate driving voltage generator 50, and the second control signal 42 is provided to the source driving circuit 30. do.

The gate driving voltage generator 50 receives the first control signal 41 and generates a clock signal and a start signal ST including first and second clock signals CK and CKB to generate the gate driving circuit ( 20) to provide. Here, the gate driving voltage generator 50 is connected to the DC / DC converter 60 that receives the external power VDD from the outside and generates the first and second power voltages VON and VOFF. 2 It is driven by the supply voltage (VON, VOFF).

Accordingly, the gate driving circuit 20 receives the clock signals CK and CKB and the start signal ST from the gate driving voltage generator 50, and receives a first power supply voltage from the DC / DC converter 60. VON) and the second power supply voltage VOFF are respectively output, and the gate driving signal is output and applied to the gate lines G1 to Gn at an appropriate time.

In this case, when the gate lines G1 to Gn are sequentially driven, the source driving circuit 30 may drive a data driving signal, that is, image data according to the second control signal 42 from the timing control circuit 40. The signal RGB is provided to the data lines D1 to Dm at an appropriate time. As such, the liquid crystal display is driven to display an image.

However, when the user intentionally cuts off the power or the power is cut off due to a power failure while the LCD is displaying an image, an after-image phenomenon in which an afterimage appears on the screen of the LCD for a predetermined period of time occurs. do. This afterimage phenomenon occurs because the charges charged in the liquid crystal capacitor 12 are not immediately discharged even after the power is cut off, and is maintained for a predetermined time.

FIG. 2 is a diagram illustrating voltage waveforms when power supplied to the liquid crystal display shown in FIG. 1 is cut off.

Referring to FIG. 2, when the external power supply VDD provided to the liquid crystal display device is cut off at the first time T1, the first power supply voltage VON may not have passed the first time T1. At the second time T2, the signal is grounded to the ground level. However, the second power supply voltage VOFF is restored to the ground level at the third time T3 after a predetermined time has elapsed since the first power supply voltage VON is down to the ground level.

In the conventional structure, since the gate driving voltage output from the gate driving circuit cannot be restored to the ground state even after the external power supply VDD is cut off, the liquid crystal capacitor 12 remains charged. Accordingly, even after the power supply VDD supplied to the liquid crystal display device is cut off, an afterimage phenomenon in which the screen of the liquid crystal display device is maintained for a long time occurs.

Accordingly, an object of the present invention is to provide a driving circuit of a liquid crystal display panel which can prevent an afterimage phenomenon in which the screen does not erase for a predetermined time even after the external power provided to the liquid crystal display panel is cut off.

Another object of the present invention is to provide a power-off discharge circuit for a liquid crystal display device which can prevent an afterimage phenomenon in which a screen is not erased for a predetermined time even after the external power supply is cut off.

Another object of the present invention is to provide a liquid crystal display device including a driving circuit of the liquid crystal display panel which can prevent an afterimage phenomenon in which the screen is not erased for a predetermined time even after the external power supply is cut off.

Another object of the present invention is to provide a method of driving a liquid crystal display device capable of preventing an afterimage phenomenon in which a screen is not erased for a predetermined time even after the power is cut off.

1 is a view schematically showing a conventional liquid crystal display device.

FIG. 2 is a diagram illustrating voltage waveforms when power supplied to the liquid crystal display shown in FIG. 1 is cut off.

3 is an exploded perspective view illustrating in detail a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a view showing in detail a structure in which a power-off discharge circuit according to an exemplary embodiment of the present invention is applied to the liquid crystal display panel shown in FIG. 3.

FIG. 5 is a block diagram illustrating a shift register constituting the gate driving circuit shown in FIG. 4.

FIG. 6 is a circuit diagram illustrating an internal circuit of each stage of the shift register illustrated in FIG. 5.

FIG. 7 is a waveform diagram of each stage shown in FIG. 5.

FIG. 8 is a circuit diagram specifically illustrating an internal configuration of the power off discharge circuit shown in FIG. 4.

FIG. 9 is a waveform diagram illustrating the VBE potential of the transistor illustrated in FIG. 8.

FIG. 10 is a diagram illustrating each voltage waveform shown in FIG. 8.

FIG. 11 is a graph illustrating a time relationship during which the third power supply voltage and the second power supply voltage shown in FIG. 8 are discharged.

The liquid crystal display panel driving circuit for achieving the above object of the present invention includes a switching element coupled to a gate line and a data line, and a liquid crystal capacitor coupled to the switching element, and is coupled to a liquid crystal display panel for displaying an image. .

Here, the driving circuit of the liquid crystal display panel is a voltage converter for generating first and second power voltages respectively by receiving external power, and receiving the first power voltage from the voltage converter to cut off the external power supply. A voltage holding unit configured to output a third power supply voltage for maintaining the first power supply voltage at a high level for a first time, and receiving the second power supply voltage from the voltage converter to cut off the external power supply. And a power off discharge part including a discharge part for outputting a second power supply voltage that becomes a ground level before the first time, and generating and applying a gate driving voltage to the gate line to drive the switching element. The second power supply voltage and the third power supply voltage supplied from the second power supply voltage and coupled to the switching element when the external power supply is cut off. It includes a gate driver for discharging the charge charged in the liquid crystal capacitor.

A power-off discharge circuit for a liquid crystal display device for achieving another object of the present invention is coupled to a gate driving circuit for driving a switching element formed in the liquid crystal display panel when the external power supply applied to the gate driving circuit is cut off. Discharge the liquid crystal capacitor coupled with the switching element.

Here, the power-off discharge circuit receives a first power supply voltage and provides a third power supply voltage to the gate driving circuit which maintains the first power supply voltage at a high level for a first time after the external power supply is cut off. By supplying the voltage holding unit and the second power supply voltage to the gate driving circuit by providing a second power supply voltage is lowered to the ground level before the first time after the external power supply is cut off, And a discharge unit for discharging the charges charged in the liquid crystal capacitor coupled to the switching element through the gate driving circuit when the external power supply is cut off.

According to another aspect of the present invention, a liquid crystal display device includes a switching element, a liquid crystal capacitor coupled to the switching element, a gate line and a data line coupled to the switching element, and a liquid crystal display panel for displaying an image. A voltage converter configured to receive external power and generate first and second power voltages respectively; a high level state until a first time after the external power supply is cut off by receiving the first power voltage from the voltage converter; A voltage supply unit for outputting a third power supply voltage for maintaining a second power supply voltage; The switching by generating a power-off discharge part including an output discharge part and a gate driving voltage and applying the gate driving voltage to the gate line Receiving the drive of characters, providing said second supply voltage and said third power supply voltage from the power-off discharge part includes a gate driving unit for discharging the electric charge charged in the liquid crystal capacitor, coupled to the switching element when the external power supply interruption .

According to another aspect of the present invention, a method of driving a liquid crystal display when power is cut off may include receiving an external power source to discharge a liquid crystal capacitor coupled to a switching element formed on the liquid crystal panel when the external power supply is cut off. Generating first and second power voltages, respectively, receiving the first power voltage and maintaining the first power voltage at a high level for a first time after the external power supply is cut off and after the first time; Generating a discharged third power supply voltage; generating a second power supply voltage that is inputted to the second power supply voltage; and generating a second power supply voltage that is down to the ground level before the first time after the external power supply is cut off; Receiving a second power supply voltage and the third power supply voltage to cut off the external power supply, and the third power supply voltage is in a high level state; And discharging the electric charge charged in the liquid crystal capacitor coupled to the switching element of the liquid crystal display panel when the voltage is in the low level state.

As described above, the power-off discharge circuit used in the above-described liquid crystal display device may receive a second power supply voltage that receives a first power supply voltage and maintains the second power supply voltage at a high level until a first time after the external power supply is cut off. A voltage holding part provided to the gate driving circuit and a third power supply voltage to be input to the gate driving circuit by lowering the second power supply voltage to a ground level before the first time after the external power supply is cut off; And a discharge unit for discharging the charge charged in the liquid crystal capacitor through the gate driving circuit when the external power supply is cut off.

Therefore, the liquid crystal display device includes the power-off discharge circuit, thereby discharging the liquid crystal capacitor within a predetermined time even after the power is cut off, thereby preventing the afterimage phenomenon of the liquid crystal display panel.

Hereinafter, a liquid crystal display device having a power off discharge circuit according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

However, as an embodiment of the present invention, a structure of an a-si liquid crystal display device in which a gate driving circuit and a source driving circuit are integrated on a liquid crystal display panel by a TFT process will be described. However, it should be noted that the present invention can be sufficiently applied to other structures such as a poly-si liquid crystal display.

3 is an exploded perspective view illustrating in detail a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display 500 largely includes a display unit 100, a backlight unit 200, a chassis 300, and a cover 400.

The display unit 100 includes a liquid crystal display panel 110, a flexible printed circuit (FPC) 190, and a driving chip 195.

The liquid crystal display panel 110 includes a TFT substrate 120 as a lower substrate, a color filter substrate 130 as an upper substrate, and a liquid crystal layer (not shown) provided therebetween. A gate driving circuit (not shown) and a source driving circuit (not shown) are formed on the TFT substrate 120 by an a-Si thin film process. In addition, a driving chip 195 is attached to the TFT substrate 120. The driving chip 195 is electrically connected to an external circuit board (not shown) by the FPC 190.

The color filter substrate 130 is a substrate on which RGB pixels and transparent common electrodes are formed.

The backlight assembly 200 includes a lamp assembly 220, a light guide plate 240, optical sheets 260, a reflective plate 280, and a storage container 290.

4 is a diagram illustrating a structure in which a power-off discharge circuit according to an exemplary embodiment of the present invention is applied to the liquid crystal display shown in FIG. 3.

Referring to FIG. 4, the display unit 100 includes a liquid crystal display panel 110 and a liquid crystal display in which a plurality of pixels including a TFT 111 and a liquid crystal capacitor 112 connected to the TFT 111 are formed in a matrix form. The driving unit 140 is configured to drive the panel 110. Specifically, the liquid crystal display panel 110 has a plurality of gate lines G1 to Gn extending in a row direction and a plurality of data lines D1 to Dm extending in a column direction.

In this case, the gate electrode 111a of the TFT 111 is commonly connected to the gate lines G1 to Gn in the row direction, and the source electrode 111b is common to the data lines D1 to Dm in the column direction. Is connected. The drain electrode 111c of the TFT 111 is connected to the liquid crystal capacitor 112.

On the other hand, a driving unit including a gate driving circuit 140 and a source driving circuit 150 is mounted around the liquid crystal display panel 110. Specifically, the gate driving circuit 140 is connected to one end of the plurality of gate lines G1 to Gn to sequentially apply gate driving signals to the plurality of gate lines G1 to Gn. In addition, the source driving circuit 150 is connected to one end of the plurality of data lines D1 to Dm and sequentially applies data driving signals to the plurality of data lines D1 to Dm.

The timing control circuit 160 receives the image data signal RGB, the vertical and horizontal synchronization signals HSYNC and VSYNC, and the clock signal CLK to receive the first control signal 161 and the second control signal 162. Occurs.

Here, the first control signal 161 output from the timing control circuit 160 is provided to the gate driving voltage generator 170, and the second control signal 162 is provided to the source driving circuit 150. do.

The gate driving voltage generator 170 receives the first control signal 161 and generates a clock signal and a start signal ST including first and second clock signals CK and CKB to generate the gate driving circuit ( 140). Here, the gate driving voltage generator 170 is connected to the DC / DC converter 180 which receives external power VDD from an external source and generates first and second power voltages VON and VOFF. It is driven by receiving the first and second power supply voltages VON and VOFF from the converter 180.

In the present invention, the timing control circuit 160 and the gate driving voltage generator 170 are separated and described. However, the poly-si liquid crystal display uses an integrated timing controller in which the timing control circuit 160 and the gate driving voltage generator 170 are integrated. Accordingly, in the poly-si liquid crystal display, a clock signal and a start signal ST including first and second clock signals CK and CKB for driving the gate driving circuit 140 are generated from an integrated timing controller. The gate driving circuit 140 is provided.

The DC / DC converter 180 is connected to a power off discharge circuit 175. Specifically, the first and second power supply voltages VON and VOFF output from the DC / DC converter 180 are provided to the power-off discharge circuit 175 and pass through the power-off discharge circuit 175. The gate driving circuit 140 is provided to be the third and second power supply voltages VONA and VOFF, respectively.

Thereafter, when the external power supply VDD provided to the liquid crystal display device is cut off, the power-off discharge circuit 175 may maintain the high power level for a predetermined time even when the first power supply voltage is discharged. The voltage VONA is generated and provided to the gate driving circuit 140. In addition, the power-off discharge circuit 175 quickly discharges the second power voltage VOFF provided from the DC / DC converter 180. The internal structure and specific operation of the power-off discharge circuit 175 will be described later.

As described above, the gate driving circuit 140 includes the clock signals CK and CKB, the start signal ST, the third power voltage VONA, and the second power voltage provided from the gate driving voltage generator 170. The gate driving signal is output and applied to the gate lines G1 to Gn at an appropriate time.

In this case, when the gate lines G1 to Gn are sequentially driven, the source driving circuit 150 may generate a data driving signal, that is, an image according to the second control signal 162 provided from the timing control circuit 160. The data signal RGB is provided to the data lines D1 to Dm at an appropriate time. As the liquid crystal display device is implemented as described above, an image may be displayed.

FIG. 5 is a block diagram illustrating a shift register constituting the gate driving circuit shown in FIG. 4. 6 is a circuit diagram illustrating an internal circuit of each stage of the shift register illustrated in FIG. 5, and FIG. 7 is an output waveform diagram of each stage of FIG. 5.

Referring to FIG. 5, the gate driving circuit 140 includes one shift register 141 to which a plurality of stages SRC1 to SRCn are cascaded. The shift register 141 is configured such that the output terminal OUT of each stage is connected to the input terminal IN of the next stage, so that each stage is connected in a dependent manner. In addition, the shift register 141 is one dummy stage SRCn + 1 connected to the next stage of the Nth stage SRCn in addition to the N stages SRC1 to SRCn corresponding to the gate lines G1 to Gn. More).

Here, each stage SRC1 to SRCn + 1 includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal input terminal CK and CKB, a third power voltage input terminal VONA, and The second power supply voltage input terminal VOFF is provided.

The start signal ST is input to the input terminal IN of the first stage SRC1. Here, the start signal ST is a pulse signal synchronized with the vertical synchronization signal VSYNC from the timing control circuit 160 shown in FIG.

The output signals OUT1 to OUTn of each stage are connected to corresponding gate lines G1 to Gn. The first clock signal CK is provided to the odd-numbered stages SRC1 and SRC3, and the second clock signal CKB is provided to the even-numbered stages SRC2 and SRC4. In this case, the first clock signal CK and the second clock signal CKB have phases opposite to each other.

Output signals OUT2, OUT3, and OUT4 of the next stage (for example, SRC2, SRC3, and SRC4) are input to the control terminal CT of each stage (for example, SRC1, SRC2, and SRC3) as control signals. . That is, the control signal input to the control terminal CT is used to lower the output signal of the previous stage to the low level.

Therefore, since the output signals of each stage sequentially have an active period (high state), corresponding gate lines are sequentially selected in the active period of each output signal.

Referring to FIG. 6, each stage of the shift register 141 includes a pull up unit 142, a pull down unit 144, a pull up driver 146, and a pull down driver 148.

The pull-up unit 142 includes a first NMOS transistor NT1 having a drain connected to a clock signal input terminal CK, a gate connected to a first node N1, and a source connected to an output terminal OUT. do.

The pull-down unit 144 includes a second NMOS transistor NT2 having a drain connected to an output terminal OUT, a gate connected to a second node N2, and a source connected to a second power supply voltage VOFF. do.

The pull-up driving unit 146 includes a first capacitor C1 and third to fifth NMOS transistors NT3 to NT5. The first capacitor C1 is connected between the first node N1 and the output terminal OUT. The third NMOS transistor NT3 has a drain connected to a third power supply voltage VONA, a gate connected to an input terminal IN, and a source connected to the first node N1. The fourth NMOS transistor NT4 has a drain connected to the first node N1, a gate connected to the control terminal CT, and a source connected to the second power voltage VOFF. In addition, the fifth NMOS transistor NT5 has a drain connected to the first node N1, a gate connected to the second node N2, and a source connected to the second power supply voltage VOFF.

Here, the size of the third NMOS transistor NT3 is about two times larger than the size of the fifth NMOS transistor NT5.

The pull-down driver 148 includes sixth and seventh NMOS transistors NT6 and NT7. In the sixth NMOS transistor NT6, a drain and a gate are commonly coupled to a third power supply voltage VONA, and a source is connected to the second node N2. In the seventh NMOS transistor NT7, a drain is connected to the second node N2, a gate is connected to the first node N1, and a source is coupled to the second power supply voltage VOFF.

The size of the sixth NMOS transistor NT6 is about 16 times larger than the size of the seventh NMOS transistor NT7.

As shown in FIG. 7, when the first and second clock signals CK and CKB and the start signal ST are supplied to the shift register 141, the start signal ST is performed in the first stage SRC1. In response to the leading edge of the signal, the high level section of the first clock signal CK is generated as the first output signal OUT1 at the output terminal OUT. Thereafter, in the second stage SRC2, in response to the first output signal OUT2 of the first stage SRC1, a high level section of the second clock signal CKB is output to the output terminal OUT. Is generated as (OUT2). As described above, the first to nth output signals OUT1 to OUTn are sequentially generated at the output terminal OUT of each stage.

Hereinafter, when the external power supply VDD provided to the liquid crystal display device is cut off, the power for discharging the third and second power supply voltages VONA and VOFF provided to the gate driving circuit 140 described above. The internal circuit configuration of the off discharge circuit 175 will be described in detail.

FIG. 8 is a diagram illustrating in detail the internal circuit configuration of the power-off discharge circuit 175 illustrated in FIG. 4, and FIG. 9 is a waveform diagram illustrating the VBE potential of the transistor illustrated in FIG. 8. 9, the X axis represents time (us) and the Y axis represents voltage (V).

Referring to FIG. 8, the power-off discharge circuit 175 provides a discharge path for discharging the second power supply voltage VOFF provided from the DC / DC converter 180 when the external power supply VDD is cut off. The discharge unit 176 and the voltage holding unit 177 generating the third power source voltage VONA that is maintained high for a predetermined time even after the external power source VDD is cut off.

Specifically, the discharge unit 176 is the emitter terminal is grounded, the collector terminal is connected to the second power supply voltage terminal (VOFF) of the DC / DC converter 180, the base terminal through the resistor (R) At the same time as the emitter terminal is connected to the external power terminal (VDD) through a second capacitor (C2). Here, a bipolar transistor BJT may be used for the transistor TR.

8 and 9, when the external power supply provided to the external power terminal VDD is cut off, the discharge unit 176 is charged with the second capacitor C2 while the transistor TR is charged. The voltage (VBE) is applied to the resistance (R) between the emitter stage and the base stage. At this time, the voltage VBE becomes equal to or greater than the first threshold voltage of the first transistor TR, so that the transistor TR is turned on and the second power voltage VOFF is grounded. Down to the level.

In this case, the second power supply voltage VOFF down to the ground level is provided to the gate driving circuit 140 through the second power supply voltage terminal VOFF.

Therefore, when the external power source VDD is cut off, the discharge unit 176 of the power-off discharge circuit 175 quickly discharges the second power source voltage VOFF of the DC / DC converter 180, thereby The voltage level of the second power supply voltage VOFF is lowered to the ground level.

The voltage holding part 177 has an anode connected to a first power supply voltage terminal VON of the DC / DC converter 180 and a cathode connected to a third power supply voltage terminal VONA and one end thereof. A capacitor C3 is connected to the cathode of the diode D and the other end is grounded. The capacitor C3 maintains the third power supply voltage VONA applied to the third power supply voltage terminal VONA to a high state for a predetermined time even when the external power supply VDD is cut off.

Specifically, the voltage holding part 177 receives the first power supply voltage VON from the DC / DC converter 180, and the voltage applied to the diode D is a second threshold of the diode D. When the voltage rises above the voltage, the diode D is forward biased, and the diode D is turned on.

When the diode D is turned on, the capacitor C3 is charged by the first power voltage VON. Subsequently, when the external power supply VDD is cut off and the first power supply voltage VON is discharged, the diode D is reversely biased so that the diode D is turned off so that the capacitor C3 is turned off. Maintains a charged state for a predetermined time. Therefore, the third power supply voltage VONA is output to the third power supply voltage terminal VONA, which is maintained at a high state for a predetermined time.

6 and 8, the discharge process when the external power supply VDD is cut off in relation to the shift register 141 constituting the gate driving circuit 140 will be described below.

In the conventional case in which the power-off discharge circuit 175 is not used, when the external power supply VDD is cut off, the first power supply voltage VON is discharged and provided as a gate input of the second NMOS transistor NT2. As a result, even if the second NMOS transistor NT2 is in the high impedance state and the second power supply voltage VOFF applied to the source terminal of the second NMOS transistor NT2 is changed to the ground level, the second power supply voltage VOFF at the ground level. This did not affect the output voltage (VOUT) of the shift resistor.

Accordingly, the TFTs of the liquid crystal display panel having the output voltage VOUT of the shift register as the gate input are turned off so that the charges charged in the respective liquid crystal capacitors are not discharged.

In the present invention, when the external power supply VDD is cut off, the third power supply voltage VONA that maintains the high level for a predetermined time is set through the sixth NMOS transistor NT6 of the shift register 141. 2 is applied to the gate of the NMOS transistor NT2 to keep the second NMOS transistor NT2 turned on. Since the second NMOS transistor NT2 maintains the turn-on state, the second power supply voltage VOFF of the ground level is transferred to the output voltage VOUT of the shift register so that each TFT of the liquid crystal display panel is turned on. In this state, charges charged in each liquid crystal capacitor are discharged through the shift register 141 and the discharge unit 176. As a result, afterimage phenomenon can be prevented.

That is, according to the present invention, even when the external power supply VDD is cut off, the voltage holding part 177 that can maintain the third power voltage VONA for a predetermined time and when the external power supply VDD is cut off are supplied. The main feature is the provision of a discharge unit 176 that quickly brings the voltage VOFF to ground level.

8 and 9, the internal circuit configuration of the power-off discharge circuit 175 according to the present invention has been described in detail. However, the discharge unit 176 of the power off discharge circuit 175 is not limited to the circuit using the transistor shown in FIG. That is, if the second power supply voltage VOFF is discharged only while the third power supply voltage VONA output from the voltage holding unit 177 is maintained in a high state, a circuit other than a transistor may be used. Of course, it can be configured and implemented.

FIG. 10 is a diagram illustrating voltage waveforms illustrated in FIG. 8, and FIG. 11 is a graph illustrating a time relationship between discharge of the third power voltage and the second power voltage shown in FIG. 8. 10 and 11, the X axis represents time (us) and the Y axis represents voltage (V).

6 and 10, the gate driving voltage VOUTn applied to the last, i.e., N-th gate line of the liquid crystal display panel in the state where the external power source VDD is applied is generated with a high period. Thereafter, when the external power source VDD applied to the liquid crystal display device is cut off, the second power source voltage VOFF is quickly restored to the ground level. Meanwhile, when the external power supply VDD is cut off, the first power supply contact voltage VON is down to the ground level, but the third power supply voltage VONA is maintained at a high state.

Referring to FIG. 11, the second power supply voltage VOFF is lowered to the ground level GND at a first time T1, and the third power supply voltage VONA is later than the first time T1. It discharges after the second time T2. That is, the relationship T2> T1 is established between the first time T1 when the second power supply voltage VOFF is discharged and the second time T2 when the third power supply voltage VONA is discharged.

11 and 6, since the third power supply voltage VONA remains high for a predetermined time even when the external power supply VDD is cut off, the second NMOS transistor NT2 is turned off. It remains turned on. In this case, as the second power supply voltage VOFF is restored to the ground level, the second power supply voltage VOFF down to the ground level is turned on through the second NMOS transistor NT2 in the turn-on state. The drive voltage VOUTn is restored to the ground level.

Accordingly, even after the power supply VDD provided to the liquid crystal display device is cut off, an afterimage phenomenon in which the screen is not erased for a predetermined time can be prevented.

The power-off discharge circuit used in the above-described liquid crystal display device receives the first power supply voltage VON and drives the gate to a third power supply voltage that is maintained at a high level until a first time after the external power supply is cut off. A voltage holding part provided to the circuit and a second power supply voltage to be input to the gate driving circuit by lowering the second power supply voltage to a ground level before the first time after the external power supply is cut off; And a discharge unit for discharging charges charged in the liquid crystal capacitor through the gate driving circuit when the external power supply is cut off.

Therefore, the liquid crystal display device includes the power-off discharge circuit so that the electric charge charged in the liquid crystal capacitor can be discharged through the gate driving circuit when the external power supply is cut off, so that the liquid crystal capacitor can be removed even after the conventional external power supply is cut off. Since the charged charges are not discharged, an afterimage phenomenon in which the liquid crystal capacitor is charged for a predetermined time may be prevented.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (9)

A liquid crystal display panel driving circuit comprising a switching element coupled to a gate line and a data line and a liquid crystal capacitor coupled to the switching element and coupled to a liquid crystal display panel for displaying an image. A voltage converter configured to receive external power and generate first and second power voltages, respectively; A voltage holding unit configured to receive the first power voltage from the voltage converting unit and output a third power voltage maintaining a high level state until a first time after the external power supply is cut off; A power-off discharge unit including a discharge unit configured to receive a power supply voltage and output a second power supply voltage which becomes a ground level before the first time after the external power supply is cut off; And Generating and applying a gate driving voltage to the gate line to drive the switching device, and receives the second power supply voltage and the third power supply voltage from the power-off discharge unit and is coupled to the switching device when the external power supply is cut off. And a gate driver for discharging the electric charge charged in the love capacitor. The method of claim 1, wherein the voltage holding unit, A diode receiving the first power voltage through a cathode end; And A first capacitor coupled to an anode end of the diode and the other end to a ground, and outputting a voltage charged to the first capacitor as a third power voltage for the first time after the external power supply is cut off. A liquid crystal display panel drive circuit. The method of claim 1, wherein the discharge unit, A transistor having a first end grounded and receiving the second power supply voltage through a second end, the transistor including a resistor coupled between the first end and the third end and turned on when the external power supply is cut off; And And a second capacitor having one end coupled to the external power source and the other end coupled to the third end to operate the transistor to turn on when the external power supply is cut off. . 4. The liquid crystal display panel driving circuit as claimed in claim 3, wherein the transistor is a bipolar transistor (BJT). A power-off discharge circuit coupled to a gate driving circuit for driving a switching element formed in a liquid crystal display panel to discharge a liquid crystal capacitor coupled to the switching element when an external power supply applied to the gate driving circuit is cut off, A voltage holding unit configured to receive a first power voltage and provide a third power voltage to the gate driving circuit to maintain a high level until a first time after the external power supply is cut off; And After receiving the second power supply voltage, the second power supply voltage is lowered to ground level and provided to the gate driving circuit before the first time after the external power supply is cut off. And a discharge unit for discharging the charged charges through the gate driving circuit. The method of claim 5, wherein the voltage holding unit, A diode receiving the first power voltage through a cathode end; And A first capacitor coupled to the anode end of the diode and the other end to ground, and outputting a voltage charged to the first capacitor as a second power voltage for the first time after the external power supply is cut off. A power-off discharge circuit for a liquid crystal display device. The method of claim 5, wherein the discharge unit, A transistor having a first end grounded and receiving the third power supply voltage through a second end, the resistor being coupled between the first end and the third end and turned on when the external power supply is cut off; And And a second capacitor having one end coupled to the external power supply and the other end coupled to the third end to operate the transistor to turn on when the external power supply is cut off. Off-discharge circuit. A liquid crystal display panel including a switching element, a liquid crystal capacitor coupled to the switching element, a gate line and a data line coupled to the switching element, and configured to display an image; A voltage converter configured to receive external power and generate first and second power voltages, respectively; A voltage holding unit configured to receive the first power voltage from the voltage converting unit and output a third power voltage maintaining a high level state until a first time after the external power supply is cut off; A power-off discharge unit including a discharge unit configured to receive a power supply voltage and output a second power supply voltage which becomes a ground level before the first time after the external power supply is cut off; And Generating and applying a gate driving voltage to the gate line to drive the switching device, and receives the second power supply voltage and the third power supply voltage from the power-off discharge unit and is coupled to the switching device when the external power supply is cut off. And a gate driver for discharging electric charges charged in the liquid crystal capacitor. A driving method of a liquid crystal display device for discharging a liquid crystal capacitor coupled with a switching element formed on a liquid crystal display panel when an external power supply is cut off, Generating first and second power voltages respectively by receiving external power; Receiving the first power voltage and maintaining a high level until a first time after the external power supply is cut off and generating a third power voltage discharged after the first time; Receiving a second power supply voltage and generating a second power supply voltage lowered to a ground level before the first time after the external power supply is cut off; And The switching element of the liquid crystal display panel when the second power supply voltage and the third power supply voltage are supplied and the external power supply is cut off so that the third power supply voltage is in a high level state and the second power supply voltage is in a low level state. And discharging the electric charge charged in the liquid crystal capacitor coupled to the liquid crystal display.