KR20030073996A - Method for manufacturing metal line - Google Patents

Method for manufacturing metal line Download PDF

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Publication number
KR20030073996A
KR20030073996A KR1020020013823A KR20020013823A KR20030073996A KR 20030073996 A KR20030073996 A KR 20030073996A KR 1020020013823 A KR1020020013823 A KR 1020020013823A KR 20020013823 A KR20020013823 A KR 20020013823A KR 20030073996 A KR20030073996 A KR 20030073996A
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South Korea
Prior art keywords
metal line
layer
barrier layer
metal
titanium
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KR1020020013823A
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Korean (ko)
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전인규
김승현
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동부전자 주식회사
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Priority to KR1020020013823A priority Critical patent/KR20030073996A/en
Publication of KR20030073996A publication Critical patent/KR20030073996A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a metal line is provided to prevent the side surface of the metal line from being contaminated by forming a spacer at both side surfaces of the metal line. CONSTITUTION: Titanium(20) is formed on the sidewall and bottom of a trench formed in the upper portion of an insulation layer. Tungsten(22) is filled in the rest of the trench. The first barrier layer(24), a metal layer(26) and the second barrier layer(28) are sequentially formed on the trench region. An unnecessary portion of the first barrier layer, the second barrier layer and the metal layer is eliminated to pattern the metal line. The spacer(30) is formed on the side surface of the metal line.

Description

메탈 라인 제조 방법{METHOD FOR MANUFACTURING METAL LINE}Metal line manufacturing method {METHOD FOR MANUFACTURING METAL LINE}

본 발명은 메탈 라인(metal line) 제조 방법에 관한 것으로, 특히, 메탈 라인 옆면이 오염되는 것을 방지하면서 메탈 라인을 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a metal line, and more particularly, to a method for manufacturing a metal line while preventing the side of the metal line from being contaminated.

현재 고집적화 된 반도체 제조 공정에 있어서 배선간의 절연을 위해 실리콘-옥사이드 층(silicon-oxide layer)을 이용하고 있다. 또한 유전 상수를 낮추기 위한 방법으로 FSG 절연층을 사용하기도 한다.Currently, silicon-oxide layers are used to insulate interconnects in highly integrated semiconductor manufacturing processes. FSG insulating layers are also used to reduce the dielectric constant.

특히 비메모리 제품에서는 다층 배선 구조를 가지고 있으며, 각각의 배선 라인은 위/아래로 배리어 층(barrier layer)을 포함하고 있다. 상기 배리어 층은 티타늄(Ti)이나 주석(TiN)으로 이루어진다.In particular, non-memory products have a multilayer wiring structure, and each wiring line includes a barrier layer up and down. The barrier layer is made of titanium (Ti) or tin (TiN).

그러나, 배선 라인의 옆면은 패터닝(patterning) 시 그대로 노출되며, 직접적으로 절연막과 접촉하게 된다. 따라서, 배선 라인의 옆면이 용매 찌꺼기(solvent residue)로 오염된 경우 절연층 자체의 불량을 가져오며, FSG 절연막을 가지는 구조에서는 "F" 어택(attack)에 대해서도 취약한 상태이다. 또한, 비아 콘택 홀(via contact hole) 형성시 미스-얼라인(mis-align)에 의한 배선 옆면 노출 상태에서 텅스텐-플러그(W-plug) 형성시 "WF6가스"에 의한 배선 부식 등이 유발된다.However, the side surface of the wiring line is exposed as it is during patterning, and comes into direct contact with the insulating film. Therefore, when the side surface of the wiring line is contaminated with solvent residues, the insulation layer itself is defective, and the structure having the FSG insulation layer is also vulnerable to the "F" attack. In addition, when the via contact hole is formed, wire corrosion may be caused by “WF 6 gas” when the tungsten plug is formed in the exposed state of the wiring side due to mis-alignment. do.

일반적으로 배선 라인 형성시 접착(adhesion) 및 배리어 역할을 위한 티타늄 층이나 주석 층을 전/후에 함께 형성한다.In general, when forming a wiring line, a titanium layer or a tin layer is formed together before and after to serve as an adhesion and a barrier.

도 1은 종래의 기술에 따른 메탈 라인 제조 방법의 일 실시예를 나타낸 단면도이다.1 is a cross-sectional view showing an embodiment of a metal line manufacturing method according to the prior art.

먼저, 산화막 등으로 이루어진 절연층 상부에 트렌치(trench)를 형성한다.First, a trench is formed on an insulating layer made of an oxide film or the like.

트렌치의 측벽 및 바닥에 티타늄(10)을 형성한다.Titanium 10 is formed on the sidewalls and bottom of the trench.

트렌치의 나머지 부분에는 텅스텐(12)으로 채운다.The rest of the trench is filled with tungsten (12).

트렌치 영역의 표면에 티타늄이나 주석으로 이루어진 제 1 배리어 층(14), 메탈 층(16), 및 티타늄이나 주석으로 이루어진 제 2 배리어 층(18)을 차례로 형성한 후, 제 1, 제 2 배리어 층(14, 18) 및 메탈 층(16)의 불필요한 부분을 제거하여 메탈 라인을 패터닝한다.After the first barrier layer 14 made of titanium or tin, the metal layer 16, and the second barrier layer 18 made of titanium or tin are formed sequentially on the surface of the trench region, the first and second barrier layers are formed. Unnecessary portions of the 14 and 18 and the metal layers 16 are removed to pattern the metal lines.

이와 같은 종래의 기술은 메탈 라인의 옆면 즉, 티타늄/주석 층-메탈 층-티타늄/주석 층의 옆면이 그대로 노출된다. 따라서, 메탈 라인 후속 공정에서 그 옆면이 용매 찌꺼기로 오염되어 접착력이 약해지는 등의 결점이 있다.This conventional technique exposes the side of the metal line, that is, the side of the titanium / tin layer-metal layer-titanium / tin layer. Therefore, in the subsequent process of the metal line, the side surface is contaminated with solvent residues, so that the adhesive strength becomes weak.

본 발명은 상술한 종래 기술의 결점을 해결하기 위하여 안출된 것으로, 메탈 라인 옆면에 스페이서(spacer)를 형성하여 메탈 라인 옆면이 오염되는 것을 방지하는 메탈 라인 제조 방법을 제공하는 데 그 목적이 있다.The present invention has been made to solve the above-described drawbacks of the prior art, and an object of the present invention is to provide a metal line manufacturing method for forming a spacer on the side of the metal line to prevent the metal line side from being contaminated.

도 1은 종래의 기술에 따른 메탈 라인 제조 방법의 일 실시예를 나타낸 단면도,1 is a cross-sectional view showing an embodiment of a metal line manufacturing method according to the prior art,

도 2는 본 발명에 따른 메탈 라인 제조 방법의 일 실시예를 나타낸 단면도.Figure 2 is a cross-sectional view showing an embodiment of a metal line manufacturing method according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

20 : 티타늄 22 : 텅스텐20: titanium 22: tungsten

24, 28 : 제 1, 제 2 배리어 층24, 28: first and second barrier layer

26 : 메탈 층 30 : 스페이서26 metal layer 30 spacer

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 메탈 라인 제조 방법의 일 실시예를 나타낸 단면도이다.2 is a cross-sectional view showing an embodiment of a metal line manufacturing method according to the present invention.

먼저, 산화막 등으로 이루어진 절연층 상부에 트렌치를 형성한다.First, a trench is formed on an insulating layer made of an oxide film or the like.

트렌치의 측벽 및 바닥에 티타늄(20)을 형성한다.Titanium 20 is formed on the sidewalls and bottom of the trench.

트렌치의 나머지 부분에는 텅스텐(22)으로 채운다.The remainder of the trench is filled with tungsten 22.

트렌치 영역의 표면에 티타늄이나 주석으로 이루어진 제 1 배리어 층(24), 알루미늄으로 이루어진 메탈 층(26), 및 티타늄이나 주석으로 이루어진 제 2 배리어 층(28)을 차례로 형성한 후, 불필요한 제 1, 제 2 배리어 층(24, 28) 및 메탈 층(26)을 제거하여 메탈 라인을 패터닝한다.The first barrier layer 24 made of titanium or tin, the metal layer 26 made of aluminum, and the second barrier layer 28 made of titanium or tin are sequentially formed on the surface of the trench area, and then unnecessary first, The second barrier layers 24 and 28 and the metal layer 26 are removed to pattern the metal lines.

다음, 메탈 라인의 옆면에 주석이나 TaN으로 이루어진 스페이서(30)를 형성한다.Next, a spacer 30 made of tin or TaN is formed on the side of the metal line.

이상에서 설명한 바와 같이, 본 발명은, 메탈 라인 패터닝 후 메탈 층 옆면의 용매 찌꺼기가 절연층과 직접 접촉하는 것을 방지함으로써 접착력이 나빠지는 것을 방지할 수 있다. 비아 콘택 홀 형성시 미스-얼라인에 의한 배선 옆면 노출 상태에서 텅스텐-플러그 형성시 "WF6가스"에 의한 배선 부식을 막을 수 있다.As described above, the present invention can prevent the adhesive force from deteriorating by preventing the solvent residues on the side of the metal layer from directly contacting the insulating layer after the metal line patterning. It is possible to prevent wiring corrosion by "WF 6 gas" when forming tungsten-plug in the exposed state of wiring side by mis-alignment when forming the via contact hole.

Claims (8)

절연층 상부에 형성된 트렌치의 측벽 및 바닥에 티타늄이 형성되고 상기 트렌치의 나머지 부분에는 텅스텐으로 채워져 있는 반도체 소자에 있어서,A semiconductor device in which titanium is formed on sidewalls and bottoms of trenches formed on an insulating layer, and tungsten is filled in the remainder of the trenches. 상기 트렌치 영역의 표면에 제 1 배리어 층, 메탈 층, 및 제 2 배리어 층을 차례로 형성하는 제 1 단계;A first step of sequentially forming a first barrier layer, a metal layer, and a second barrier layer on a surface of the trench region; 상기 제 1, 제 2 배리어 층 및 상기 메탈 층의 불필요한 부분을 제거하여 메탈 라인을 패터닝하는 제 2 단계; 및A second step of patterning a metal line by removing unnecessary portions of the first and second barrier layers and the metal layer; And 상기 메탈 라인의 옆면에 스페이서를 형성하는 제 3 단계를 포함하는 메탈 라인 제조 방법.And forming a spacer on a side surface of the metal line. 제 1 항에 있어서, 상기 제 1 배리어 층은 티타늄으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the first barrier layer is made of titanium. 제 1 항에 있어서, 상기 제 1 배리어 층은 주석으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the first barrier layer is made of tin. 제 1 항에 있어서, 상기 메탈 층은 알루미늄으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the metal layer is made of aluminum. 제 1 항에 있어서, 상기 제 2 배리어 층은 티타늄으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the second barrier layer is made of titanium. 제 1 항에 있어서, 상기 제 2 배리어 층은 주석으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the second barrier layer is made of tin. 제 1 항에 있어서, 상기 스페이서는 주석으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the spacer is made of tin. 제 1 항에 있어서, 상기 스페이서는 TaN으로 이루어진 것을 특징으로 하는 메탈 라인 제조 방법.The method of claim 1, wherein the spacer is made of TaN.
KR1020020013823A 2002-03-14 2002-03-14 Method for manufacturing metal line KR20030073996A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057273A (en) * 1997-12-29 1999-07-15 김영환 Metal wiring formation method of semiconductor device
JP2000232160A (en) * 1999-02-10 2000-08-22 Sony Corp Semiconductor device and its manufacture
KR20020002538A (en) * 2000-06-30 2002-01-10 박종섭 Method for forming contact plug in semiconductor device
KR20020002608A (en) * 2000-06-30 2002-01-10 박종섭 Method for forming bitline in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057273A (en) * 1997-12-29 1999-07-15 김영환 Metal wiring formation method of semiconductor device
JP2000232160A (en) * 1999-02-10 2000-08-22 Sony Corp Semiconductor device and its manufacture
KR20020002538A (en) * 2000-06-30 2002-01-10 박종섭 Method for forming contact plug in semiconductor device
KR20020002608A (en) * 2000-06-30 2002-01-10 박종섭 Method for forming bitline in semiconductor device

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