KR20030073867A - Method for manufacturing mos transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a metal oxide semiconductor(MOS) transistor is provided to control an increase of density in a junction and reduce junction leakage and junction capacitance by performing a pocket ion implantation process only on a channel and a source/drain extension region. CONSTITUTION: A semiconductor substrate(100) is prepared in which an NMOS transistor formation region(I) and a PMOS transistor formation region(II) are defined. An isolation layer(103) is formed on the substrate. A gate oxide layer(110) is formed on the substrate. The first and second gates(112a,112b) are formed on the gate oxide layer in the NMOS and PMOS transistor formation regions, respectively. The first insulation layer pattern covering the first and second gates and the second insulation layer pattern having etch selectivity different from that of the first insulation layer pattern are sequentially formed. Ion implantation processes are selectively performed on the NMOS and PMOS transistor formation regions to form the first and second sources/drains(117,118,119,120), respectively. The first and second epitaxial layers are selectively formed in the substrate corresponding to the first and second sources/drains. Ion implantation processes are selectively performed on the first and second epitaxial layers to form the first and second high density regions(124,126), respectively. The second insulation layer is eliminated. Pocket ions and source/drain extension ions are sequentially implanted into the NMOS and PMOS transistor formation regions, respectively.

Description

MOS transistor manufacturing method {METHOD FOR MANUFACTURING MOS TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor capable of securing high performance and stability of transistors and junctions.

In general, as semiconductor devices are highly integrated, a MOS transistor is a method for forming a shallow source / drain junction having a shallow depth, a method by ion implantation of low energy, a dual ion implantation method using the same, A method of suppressing channeling effect by pre-crystallization is proposed. These methods still lack the physical and chemical characterization of defect formation by implanted ions for the formation of shallow junctions of semiconductor devices of less than 0.1㎛ class. Therefore, the elevation of the source / drain by the selective epitaxial growth method in which the source / drain junction is formed on the upper part of the substrate, instead of the method of forming the shallow junction by ion implantation on the lower part of the substrate surface such as silicon. Drain junctions have been proposed.

However, in the prior art, as the semiconductor devices are increasingly integrated, the gate length is reduced and a short channel effect occurs. Therefore, in order to improve the short channel effect, it is necessary to decrease the junction depth and the source / drain concentration, thereby inevitably increasing the parasitic resistance of the source / drain, thereby degrading the performance of the transistor. In addition, the pocket ion implantation process is performed to improve the short channel effect. However, the pocket ion implantation process is injected into unwanted portions of the junction in addition to the channel region to increase junction leakage and junction capacitance. There was a problem.

Accordingly, an object of the present invention is to provide a MOS transistor manufacturing method capable of reducing the junction liquidity and junction capacitance.

1A to 1K are cross-sectional views illustrating a method of manufacturing a MOS transistor according to the present invention.

Explanation of symbols for main parts of the drawings

100. Semiconductor substrate 102. Charlotte trench

103. Device isolators 104, 106. Wells

110. Gate oxide films 112a and 112b. gate

114, 116. Insulation spacers 117, 118, 119, 120. Source / drain

122. Epitaxial layer 124, 126. High concentration region

128. Silicide layer 160. Buffer membrane

162. Insulator 164. Opening

166. Metal plugs 130, 132, 134, 136, 138, 140. Photoresist pattern

I. NMOS transistor formation area Ⅱ. PMOS transistor formation area

In order to achieve the above object, the present invention provides a method of manufacturing a MOS transistor, the method including: providing a semiconductor substrate having an NMOS transistor forming region and a PMOS transistor forming region; Forming a gate oxide film on the entire surface of the substrate including the device isolation film, forming a first gate in the NMOS transistor formation region of the gate oxide film, and a second gate in the PMOS transistor formation region, respectively, and forming the first and second gates. Sequentially forming a covering first insulating film pattern and a second insulating film pattern having a different etching selectivity from the first insulating film pattern, selectively implanting ions into an NMOS transistor formation region to form a first source / drain, and a PMOS Selectively implanting ions into the transistor formation region to form a second source / drain Selectively forming first and second epitaxial layers on portions corresponding to the first and second sources / drains of the substrate, and selectively implanting ions into the first epitaxial layer to form a first high concentration region. Forming a second high concentration region by selectively implanting ions into the second epitaxial layer, removing the second insulating film pattern, and implanting pocket ions and source / drain into the NMOS transistor formation region. The method includes the steps of sequentially performing extended ion implantation, and then sequentially performing pocket ion implantation and source / drain extended ion implantation in the PMOS transistor formation region.

The gate oxide film may include any one of a silicon oxide film, a silicon nitride film, and a stacked structure of a silicon nitride film and a silicon oxide film.

After the pocket ion implantation and the source / drain expansion ion implantation are sequentially performed in the PMOS transistor formation region, forming an insulating film having an opening for exposing a silicide layer on the resultant, and forming a conductive plug covering the opening. It includes adding.

A silicon nitride film is used as the first insulating film pattern, and a silicon oxide film is used as the second insulating film pattern.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1K are cross-sectional views illustrating a method of manufacturing a MOS transistor according to the present invention.

In the method of manufacturing the MOS transistor of the present invention, as shown in FIG. 1A, a shallow trench 102 is formed in an element isolation region (not shown) of the semiconductor substrate 100, and the shallow A device isolation film 103 is formed to fill the trench 102.

In this case, an NMOS transistor forming region I and a PMOS transistor forming region II are defined in the substrate 100. Subsequently, a mask operation is performed on the substrate on which the device isolation film 103 is formed and an ion implantation process is performed to form a P well 104 in the NMOS transistor forming region I and an N well in the PMOS transistor forming region II. Form 106.

Next, as shown in FIG. 1B, a gate oxide film 110 is formed on the entire surface of the substrate including the P well 104 and the N well 106. In this case, the gate oxide film 110 may use any one of a silicon oxide film, a silicon nitride film, and a stacked structure of a silicon nitride film and a silicon oxide film. Thereafter, a polycrystalline silicon layer doped with an impurity is formed on the gate oxide layer 110, and then the polycrystalline silicon layer is etched by a photolithography process to form an NMOS transistor formation region I and a PMOS transistor formation region II. ) And the first and second gates 112a and 112b, respectively.

Subsequently, as shown in FIG. 1C, a silicon nitride film and an oxide-based oxide film having an etch selectivity different from that of the silicon nitride film are sequentially deposited on the entire surface of the substrate including the first and second gates 112a and 112b. Next, the silicon oxide film and the silicon nitride film are etched through a mask process to form respective first insulating spacers 114 and second insulating spacers 116 covering the first and second gates 112a and 112b. Next, after the photoresist is coated on the entire surface of the resultant substrate, the photoresist is exposed and developed to form a first photoresist pattern 130 covering the PMOS transistor formation region II and exposing the NMOS transistor formation region I. Subsequently, the first photoresist pattern 130 is used as a mask and N + ion implantation is performed on the entire surface of the substrate so that the first source / drain (N +) 117 (118) is disposed on both substrates below the first gate 112a. Form.

Then, as shown in Fig. 1D, the first photoresist pattern is removed. Subsequently, a photoresist film is applied to the entire surface of the substrate including the first source / drain (N +) 117 and 118 again, followed by exposure and development to cover the NMOS transistor formation region I and expose the PMOS transistor formation region II. The second photosensitive film pattern 132 is formed. Subsequently, P + ions are implanted to the entire surface of the substrate using the second photoresist pattern 132 as a mask to form second sources / drains (P +) 119 and 120 on both substrates below the second gate 112b. .

Next, as shown in FIG. 1E, an epitaxial layer (optional) may be selectively covered to cover the first source / drain (N +) 117 118 and the second source / drain (P +) 119, 120. 122).

Afterwards, as shown in FIG. 1F, the third photoresist pattern 134 covering the PMOS transistor formation region II and exposing the NMOS transistor formation region I is exposed on the substrate including the epitaxial layer 122. Form. Subsequently, N + high concentration ion implantation is performed on the epitaxial layer of the NMOS transistor formation region I using the third photoresist pattern 134 as a mask to form the first high concentration region N + 124. In this case, N + ion implanted energy is set within a range such that ions are not implanted deeper than the first source / drain 117 and 118 regions.

Then, as shown in Fig. 1G, the third photoresist pattern is removed. Next, a fourth photoresist pattern 136 is formed on the resultant to cover the NMOS transistor formation region I and expose the PMOS transistor formation region II. Thereafter, the fourth photoresist pattern 136 is used as a mask to form a second high concentration region (P +) 126 by performing P + ion implantation on the entire substrate. In this case, P + ion implantation energy is set within a range such that ions are not implanted deeper than the second source / drain 119 and 120 regions.

Subsequently, as shown in FIG. 1H, after the fourth photoresist pattern is removed, a salicide process is performed to form the first high concentration region (N +) 124 and the PMOS transistor formation region (II) of the NMOS transistor formation region (I). Each salicide layer 128 is formed on the epitaxial layer of the second high concentration region (P +) 126.

Next, as shown in FIG. 1I, a fifth photoresist pattern 138 covering the PMOS transistor forming region II and exposing the NMOS transistor forming region I is exposed on the substrate including the salicide layer 128. Form. Thereafter, using the fifth photoresist pattern 138 as a mask, pocket ion implantation and first source / drain 117 and 118 extended ion implantation (N−) are sequentially performed in the NMOS transistor formation region (I). In this case, reference numeral 150 denotes a state in which pocket ion implantation is performed, and reference numeral 152 illustrates a state in which first source / drain 117 and 118 expansion ion implantation (N−) is performed.

Subsequently, as shown in FIG. 1J, after removing the fifth photoresist pattern, the NMOS is again on the substrate on which the pocket ion implantation and the first source / drain 117 and 118 expansion ion implantation (N−) processes are completed. A sixth photosensitive film pattern 140 covering the transistor forming region I and exposing the PMOS transistor forming region II is formed. Subsequently, pocket ion implantation and second source / drain 119 and 120 extended ion implantation (P−) are performed on the entire surface of the substrate using the sixth photosensitive film pattern 140 as a mask. In this case, reference numeral 154 denotes a pocket ion implanted state, and reference numeral 156 denotes a state in which the second source / drain 119 and 120 extended ion implantation (P−) is performed.

Then, as shown in Fig. 1K, the sixth photosensitive film pattern is removed. Subsequently, an insulating film 162 using a buffer oxide layer 160 and a BPSG is applied to a substrate on which the pocket ion implantation and the second source / drain 119 and 120 expansion ion implantation (P-) processes are completed. Deposition in turn. Thereafter, the buffer layer 160 and the insulating layer 162 are etched by a photolithography process to form an opening 164 exposing the salicide layer 128, and then an insulating film including the opening 164. A metal film is deposited and etched back on the 162 by sputtering to form a metal plug 166 covering the opening 164.

As described above, in the present invention, by limiting the pocket ion implantation to the channel and the source / drain extension region, it is possible to control the increase in concentration in the junction, and to reduce the junction liquidity and the junction capacitance.

In addition, in the present invention, by performing source / drain expansion ion implantation and pocket ion implantation, short channel margins can be secured, and unnecessary boron concentrations of junctions and channels can be reduced, thereby reducing junction liquidity and junction capacitance. Therefore, high performance and stability of the transistor and the junction can be ensured.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

Providing a semiconductor substrate having an NMOS transistor formation region and a PMOS transistor formation region defined therein; Forming a device isolation film separating the device from the device on the substrate; Forming a gate oxide film on an entire surface of the substrate including the device isolation film; Forming a first gate in a NMOS transistor forming region of the gate oxide film and a second gate in a PMOS transistor forming region, respectively; Sequentially forming a first insulating layer pattern covering the first and second gates and a second insulating layer pattern having an etch selectivity different from that of the first insulating layer pattern; Selectively implanting ions into the NMOS transistor formation region to form a first source / drain; Selectively implanting ions into the PMOS transistor formation region to form a second source / drain; Selectively forming first and second epitaxial layers on portions of the substrate corresponding to the first and second sources / drains, Selectively implanting ions into the first epitaxial layer to form a first high concentration region; Selectively implanting ions into the second epitaxial layer to form a second high concentration region; Removing the second insulating pattern; Performing pocket ion implantation and source / drain expansion ion implantation sequentially in the NMOS transistor formation region; And sequentially performing pocket ion implantation and source / drain extension ion implantation into the PMOS transistor formation region. The method of claim 1, wherein the gate oxide film is any one of a silicon oxide film, a silicon nitride film, and a stacked structure of a silicon nitride film and a silicon oxide film. The method of claim 1, wherein after performing pocket ion implantation and source / drain expansion ion implantation in the PMOS transistor formation region, Forming an insulating film having an opening exposing the silicide layer on the resultant, And forming a conductive plug covering the opening. The method of claim 1, wherein a silicon nitride film is used as the first insulating film pattern, and a silicon oxide film is used as the second insulating film pattern.