KR20030073384A - Tuner for using a quartz oscillator in common - Google Patents

Tuner for using a quartz oscillator in common Download PDF

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Publication number
KR20030073384A
KR20030073384A KR1020020012930A KR20020012930A KR20030073384A KR 20030073384 A KR20030073384 A KR 20030073384A KR 1020020012930 A KR1020020012930 A KR 1020020012930A KR 20020012930 A KR20020012930 A KR 20020012930A KR 20030073384 A KR20030073384 A KR 20030073384A
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South Korea
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osc
crystal oscillator
pll
oscillation frequency
demodulation
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KR1020020012930A
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Korean (ko)
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KR100820278B1 (en
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임현우
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엘지이노텍 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/045—Modification of automatic frequency control sensitivity or linearising automatic frequency control operation; Modification of the working range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

PURPOSE: A tuner using a crystal oscillator in common is provided to reduce the bit generation due to an interference by using a demodulation IC(Integrated Circuit) and a PLL(Phase Locked Loop) IC which shares one crystal oscillator. CONSTITUTION: An OSC(Oscillator)(110) generates an oscillating frequency of 4 MHz in a crystal oscillator(111). A PLL IC(120) receives the oscillating frequency generated in the OSC(110) through an oscillating frequency input terminal. A dividing circuit(130) divides the oscillating frequency generated in the OSC(110) by a predetermined multiple. A demodulating IC(140) receives the oscillating frequency received from the crystal oscillator(111) of the OSC(110) through the oscillating frequency input terminal. A low pass filter(150) is provided between the OSC(110) and the PLL IC(120) to eliminate a noise signal out of output signals from the crystal oscillator(111) of the OSC(110). The low pass filter(150) cuts off the interference which is occurred due to transmission of an output signal from the demodulating IC(140).

Description

수정 진동자를 공용으로 사용하는 튜너{TUNER FOR USING A QUARTZ OSCILLATOR IN COMMON}TUNER FOR USING A QUARTZ OSCILLATOR IN COMMON}

본 발명은 튜너에 관한 것으로, 더욱 상세하게는 PLL IC에 사용되는 OSC의 4MHz 수정 진동자를 분주하여 복조 IC에서 공용으로 사용하도록 수정 진동자를 공용으로 사용하는 튜너에 관한 것이다.The present invention relates to a tuner, and more particularly, to a tuner that uses a crystal oscillator in common so as to divide a 4 MHz crystal oscillator of an OSC used in a PLL IC and use the same in a demodulation IC.

일반적으로 튜너에 사용되는 QAM 복조 IC은 28.9MHz의 수정 진동자와 4MHz의 수정 진동자를 사용하는 칩들이 있다. QAM 복조 IC의 시스템 클럭이 약 58MHz를 사용하고 있으며, 필립스사의 QAM 복조 IC의 경우 4MHz를 14배 분주하여 사용하고,ST사의 복조 IC의 경우 2배 분주하여 사용하고 있다.QAM demodulation ICs typically used in tuners include chips that use 28.9MHz crystal oscillators and 4MHz crystal oscillators. The system clock of the QAM demodulation IC is about 58MHz, and the Philips QAM demodulation IC is divided by 14 times 4MHz and ST's demodulation IC is divided by 2 times.

한편 튜너에는 QAM 복조 IC외에 PLL IC가 사용되며, PLL IC는 OSC의 4MHz 수정 진동자를 사용하게 된다.The tuner uses a PLL IC in addition to the QAM demodulation IC, which uses a 4MHz crystal oscillator from OSC.

그러나 이러한 종래의 튜너에는 QAM 복조 IC와 PLL IC에서 필요한 수정 진동자가 2개가 존재하므로 복조 IC의 수정 진동자의 고조파와 OSC의 신호간에 간섭으로 인해 비트(Beat)가 발생하여 VHF LOW 또는 VHF HIGH(50MHz~450MHz)채널에 성능상의 심각한 영향을 미치는 문제점이 있다.However, since the conventional tuner has two crystal oscillators required by the QAM demodulation IC and the PLL IC, a beat occurs due to the interference between the crystal harmonics of the demodulation IC of the demodulation IC and the signal of the OSC, resulting in a VHF LOW or VHF HIGH (50 MHz ~ 450MHz) has a serious performance impact on the channel.

따라서 본 발명의 목적은 상기와 같은 문제점을 해결하기 위한 것으로, 튜너에 하나의 수정 진동자를 사용하여 복조 IC와 PLL IC에서 공용하도록 함으로써 두 개의 수정 진동자의 사용에 따른 간섭으로 인해 비트가 발생되는 것을 미연에 방지하도록 하는데 있다.Accordingly, an object of the present invention is to solve the above problems, by using a single crystal oscillator in the tuner to be shared by the demodulation IC and the PLL IC to generate a bit due to interference caused by the use of two crystal oscillators To prevent it.

도 1은 본 발명에 따른 수정 진동자를 공용으로 사용하는 튜너의 구성을 개략적으로 나타낸 블록 회로도1 is a block circuit diagram schematically showing the configuration of a tuner using a crystal oscillator in common according to the present invention

<도면중 주요부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

110 : OSC111 : 수정 진동자110: OSC111: crystal oscillator

120 : PLL IC130 : 분주 회로120: PLL IC130: frequency divider circuit

140 : 복조 IC150 : 로우 패스 필터140: demodulation IC150: low pass filter

상기와 같은 목적을 달성하기 위한 본 발명의 특징은,Features of the present invention for achieving the above object,

튜너에 있어서,In the tuner,

수정 진동자에서 4MHz의 발진 주파수를 생성하는 OSC와,An OSC generating an oscillation frequency of 4 MHz on a crystal oscillator,

상기 OSC로부터 발생된 발진 주파수를 발진 주파수 입력단을 통해 인가받는 PLL IC와,A PLL IC receiving the oscillation frequency generated from the OSC through an oscillation frequency input terminal;

상기 OSC로부터 발생된 발진 주파수를 소정 배수 분주하는 분주 회로와,A division circuit for dividing the oscillation frequency generated from the OSC by a predetermined multiple,

상기 분주 회로를 통해 분주되어 상기 OSC의 수정 진동자로부터 인가되는 발진 주파수를 발진 주파수 입력단을 통해 인가받는 복조 IC와,A demodulation IC which is divided through the frequency divider circuit and receives an oscillation frequency applied from the crystal oscillator of the OSC through an oscillation frequency input terminal;

상기 OSC와 상기 PLL IC 사이에 구비되어 상기 OSC의 수정 진동자의 출력 신호중 노이즈 신호를 제거하고, 상기 복조 IC의 신호가 전달되어 간섭이 발생되는 것을 차단하는 로우 패스 필터를 포함하는 것을 특징으로 한다.And a low pass filter disposed between the OSC and the PLL IC to remove a noise signal from an output signal of the crystal oscillator of the OSC, and to block a signal from the demodulation IC from being interrupted.

이하, 본 발명에 의한 수정 진동자를 공용으로 사용하는 튜너의 구성을 도 1을 참조하여 상세하게 설명하기로 한다.Hereinafter, a configuration of a tuner using a crystal oscillator in common according to the present invention will be described in detail with reference to FIG. 1.

도 1은 본 발명에 따른 수정 진동자를 공용으로 사용하는 튜너의 구성을 개략적으로 나타낸 블록 회로도이다.1 is a block circuit diagram schematically showing the configuration of a tuner using a crystal oscillator in common according to the present invention.

도 1을 참조하면, 본 발명에 따른 수정 진동자를 공용으로 사용하는 튜너()는, OSC(110)와, PLL IC(120)와, 분주 회로(130)와, 복조 IC(140)와, 로우 패스 필터(150)로 구성된다.Referring to FIG. 1, a tuner () using a crystal oscillator in common according to the present invention includes an OSC 110, a PLL IC 120, a division circuit 130, a demodulation IC 140, and a row. It consists of a pass filter 150.

OSC(110)는 수정 진동자(111)에서 4MHz의 발진 주파수를 생성한다.The OSC 110 generates an oscillation frequency of 4 MHz in the crystal oscillator 111.

PLL IC(120)는 OSC(110)로부터 발생된 발진 주파수를 발진 주파수 입력단(XTAL)을 통해 인가받는다.The PLL IC 120 receives the oscillation frequency generated from the OSC 110 through the oscillation frequency input terminal XTAL.

분주 회로(130)는 OSC(110)로부터 발생된 발진 주파수를 소정 배수 분주한다. 여기에서 분주 회로(130)는 복조 IC(140)의 종류에 따라 복조 IC의 내부에 구비될 수도 있으며, 복조 IC(140)에서 사용되는 시스템 클럭에 따라 발진 주파수를 분주하여 사용한다. 예를 들어 복조 IC(140)가 58MHz의 시스템 클럭을 사용하면 OSC(110)의 수정 진동자(111)의 발진 주파수를 14~15배 분주하는 회로가 사용된다.The division circuit 130 divides the oscillation frequency generated from the OSC 110 by a predetermined multiple. Here, the frequency divider 130 may be provided inside the demodulation IC according to the type of the demodulation IC 140, and divide and use the oscillation frequency according to the system clock used in the demodulation IC 140. For example, when the demodulation IC 140 uses a 58 MHz system clock, a circuit for dividing the oscillation frequency of the crystal oscillator 111 of the OSC 110 by 14 to 15 times is used.

복조 IC(140)는 분주 회로(130)를 통해 분주되어 OSC의 수정 진동자(111)로부터 인가되는 발진 주파수를 발진 주파수 입력단(IN, OUT)을 통해 인가받는다.The demodulation IC 140 is divided through the division circuit 130 to receive the oscillation frequency applied from the crystal oscillator 111 of the OSC through the oscillation frequency input terminals IN and OUT.

로우 패스 필터(150)는 OSC(110)와 PLL IC(120) 사이에 구비되어 OSC(110)의 수정 진동자(111)의 출력 신호중 노이즈 신호를 제거하고, 복조 IC(140)의 신호가 전달되어 간섭이 발생되는 것을 차단한다.The low pass filter 150 is disposed between the OSC 110 and the PLL IC 120 to remove a noise signal from the output signal of the crystal oscillator 111 of the OSC 110, and to transmit a signal of the demodulation IC 140. To prevent interference from occurring.

이하 본 발명에 따른 수정 진동자를 공용으로 사용하는 튜너의 동작을 도 1을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, an operation of a tuner using a crystal oscillator according to the present invention will be described in detail with reference to FIG. 1.

먼저 OSC(110)의 수정 진동자(111)에서 발생된 4MHz의 발진 주파수는 PLL IC(120)와 분주 회로(130)로 각각 인가된다.First, the 4MHz oscillation frequency generated by the crystal oscillator 111 of the OSC 110 is applied to the PLL IC 120 and the divider circuit 130, respectively.

이때 로우 패스 필터(150)를 통해 발진 주파수에 포함된 노이즈가 제거되고, 또한 복조 IC(140)의 신호가 PLL IC(120)로 유입되는 것이 차단된다.At this time, the noise included in the oscillation frequency is removed through the low pass filter 150, and the signal of the demodulation IC 140 is blocked from flowing into the PLL IC 120.

한편 분주 회로(130)에 인가된 발진 주파수는 복조 IC(140)의 시스템 클럭에 맞게 분주되어 인가된다.The oscillation frequency applied to the division circuit 130 is divided and applied according to the system clock of the demodulation IC 140.

따라서 PLL IC와 복조 IC에서 OSC의 수정 진동자를 공용함으로써 회로 설계가 간단해지고, 회로의 제조 단가가 낮춰지며, 종래의 튜너에서 두 개의 수정 진동자의 사용에 따른 간섭으로 인해 비트가 발생되는 것을 미연에 방지한다.Therefore, by sharing the OSC crystal oscillator in the PLL IC and the demodulation IC, the circuit design is simplified, the manufacturing cost of the circuit is lowered, and the bit is generated due to the interference caused by the use of two crystal oscillators in the conventional tuner. prevent.

이상에서 설명한 바와 같이 본 발명에 따른 수정 진동자를 공용으로 사용하는 튜너에 의하면, 튜너에 하나의 수정 진동자를 사용하여 복조 IC와 PLL IC에서 공용하도록 함으로써 두 개의 수정 진동자의 사용에 따른 간섭으로 인해 비트가 발생되는 것을 미연에 방지할 수 있다.As described above, according to the tuner using the crystal oscillator according to the present invention, a single crystal oscillator is used in the tuner to share the demodulation IC and the PLL IC. Can be prevented from occurring.

Claims (1)

튜너에 있어서,In the tuner, 수정 진동자에서 4MHz의 발진 주파수를 생성하는 OSC와,An OSC generating an oscillation frequency of 4 MHz on a crystal oscillator, 상기 OSC로부터 발생된 발진 주파수를 발진 주파수 입력단을 통해 인가받는 PLL IC와,A PLL IC receiving the oscillation frequency generated from the OSC through an oscillation frequency input terminal; 상기 OSC로부터 발생된 발진 주파수를 소정 배수 분주하는 분주 회로와,A division circuit for dividing the oscillation frequency generated from the OSC by a predetermined multiple, 상기 분주 회로를 통해 분주되어 상기 OSC의 수정 진동자로부터 인가되는 발진 주파수를 발진 주파수 입력단을 통해 인가받는 복조 IC와,A demodulation IC which is divided through the frequency divider circuit and receives an oscillation frequency applied from the crystal oscillator of the OSC through an oscillation frequency input terminal; 상기 OSC와 상기 PLL IC 사이에 구비되어 상기 OSC의 수정 진동자의 출력 신호중 노이즈 신호를 제거하고, 상기 복조 IC의 신호가 전달되어 간섭이 발생되는 것을 차단하는 로우 패스 필터를 포함하는 것을 특징으로 하는 수정 진동자를 공용으로 사용하는 튜너.And a low pass filter disposed between the OSC and the PLL IC to remove a noise signal from an output signal of the crystal oscillator of the OSC, and to block a signal from the demodulation IC from being interrupted. Tuner using oscillator in common.
KR1020020012930A 2002-03-11 2002-03-11 Tuner for using a quartz oscillator in common KR100820278B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008063030A1 (en) 2006-11-24 2008-05-29 Alphavision Co., Ltd. Reflector and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0782271B1 (en) * 1995-12-28 2002-03-13 Thomson Consumer Electronics, Inc. Phase locked loop with controllable response time
KR20020069685A (en) * 2001-02-27 2002-09-05 엘지이노텍 주식회사 Voltage control oscillator for digital tuner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008063030A1 (en) 2006-11-24 2008-05-29 Alphavision Co., Ltd. Reflector and manufacturing method thereof

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