CN217388683U

CN217388683U - Circuit for eliminating clock jitter generated during digital audio transmission by utilizing PLL (phase locked loop) technology

Info

Publication number: CN217388683U
Application number: CN202221369584.6U
Authority: CN
Inventors: 刘平
Original assignee: Foshan Shuangmu Sanlin Technology Co ltd
Current assignee: Foshan Shuangmu Sanlin Technology Co ltd
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2022-09-06
Anticipated expiration: 2032-06-02

Abstract

The utility model discloses a circuit that produces clock jitter when utilizing PLL technique to eliminate digital audio transmission relates to the digital audio field, and the circuit that produces clock jitter when should utilizing PLL technique to eliminate digital audio transmission includes: the digital receiving module is used for receiving input audio, generating an LRCK signal and outputting the LRCK signal to the phase discrimination module; the digital phase-locked loop module is used for generating a same-frequency signal with the LPCK signal and outputting the same-frequency signal to the phase discrimination module; outputting the audio signal; compared with the prior art, the beneficial effects of the utility model are that: the utility model processes the phase difference of the digital receiving module and the digital phase-locked loop module, feeds the phase difference back to the digital phase-locked loop module, and eliminates clock jitter; and the performance of the digital phase-locked loop module adopting the chip is far higher than that of the digital receiving module adopting the chip, so that the performance of the whole circuit system is improved.

Description

Circuit for eliminating clock jitter generated during digital audio transmission by utilizing PLL (phase locked loop) technology

Technical Field

The utility model relates to a digital audio frequency field specifically is a circuit that produces clock jitter when utilizing PLL technique to eliminate digital audio transmission.

Background

In prior art digital systems, the audio signal is transmitted using the S/PDIF format, and its transmission requires the use of dedicated transmitting (e.g. CS8406) and receiving chips (e.g. CS8416, PCM9210, etc.).

However, due to the PLL performance inside the chip, the receiving effect is difficult to achieve, and the JITTER (JITTER) of the clock signal recovered by the PLL is large, so that the ideal state is difficult to achieve, and improvement is needed.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an utilize PLL technique to eliminate the circuit that produces clock jitter when digital audio transmission to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a circuit for removing clock jitter generated during digital audio transmission by using PLL technique, comprising:

the digital receiving module is used for receiving input audio, generating an LRCK signal and outputting the LRCK signal to the phase discrimination module;

the digital phase-locked loop module is used for generating a same-frequency signal with the LPCK signal and outputting the same-frequency signal to the phase discrimination module; outputting the audio signal;

the phase discrimination module is used for comparing the LPCK signal with the same-frequency signal and outputting the phase difference of the LPCK signal and the same-frequency signal to the voltage-controlled oscillation module;

the voltage-controlled oscillation module is used for changing the output audio signal of the digital phase-locked loop module according to the phase difference so that the phases of the output audio signal and the LRCK signal are consistent;

the digital receiving module is connected with the phase demodulation module, the digital phase-locked loop module is connected with the phase demodulation module, the phase demodulation module is connected with the voltage-controlled oscillation module, and the voltage-controlled oscillation module is connected with the digital phase-locked loop module.

As a further aspect of the present invention: the digital receiving module comprises an integrated circuit (digital receiving chip) IC5, a pin No. 33 of an integrated circuit IC5 is connected with the third end of the optical fiber seat JK301, a pin No. 35 of an integrated circuit IC5 is connected with the coaxial JK1 through a capacitor, and a pin No. 17 of an integrated circuit IC5 is connected with the phase detection module.

As a further aspect of the present invention: the digital phase-locked loop module comprises an integrated circuit (digital phase-locked loop chip) IC13, a pin No. 10 of the integrated circuit IC13 is connected with the phase detection module, and a pin No. 2 of the integrated circuit IC13 is connected with the voltage-controlled oscillation module through a capacitor.

As the utility model discloses further scheme again: the phase detection module comprises an integrated circuit (phase detector chip) IC1081, a No. 14 pin of the integrated circuit IC1081 is connected with the digital receiving module, a No. 3 pin of the integrated circuit IC1081 is connected with the digital phase-locked loop module, and a No. 13 pin of the integrated circuit IC1081 is connected with the voltage-controlled oscillation module.

As a further aspect of the present invention: the voltage-controlled oscillation module comprises an active voltage-controlled crystal oscillator Y1801, a pin No. 3 of the active voltage-controlled crystal oscillator Y1081 is connected with the digital phase-locked loop module, a pin No. 1 of the active voltage-controlled crystal oscillator Y1081 is connected with an integrated circuit IC66, and a pin No. 3 of an integrated circuit IC66 is connected with a pin No. 13 of the integrated circuit IC1081 through a resistor.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model processes the phase difference of the digital receiving module and the digital phase-locked loop module, feeds back the phase difference to the digital phase-locked loop module, and eliminates clock jitter; and the performance of the digital phase-locked loop module adopting the chip is far higher than that of the digital receiving module adopting the chip, so that the performance of the whole circuit system is improved.

Drawings

Fig. 1 is a schematic diagram of a circuit for eliminating clock jitter generated during digital audio transmission by using PLL technique.

Fig. 2 is a circuit diagram of a circuit for eliminating clock jitter generated during digital audio transmission by using PLL technique.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative work belong to the protection scope of the present invention based on the embodiments of the present invention.

Referring to fig. 1, a circuit for eliminating clock jitter generated during digital audio transmission by using PLL technique includes:

In this embodiment: referring to fig. 2, the digital receiving module includes an integrated circuit (digital receiving chip) IC5, pin No. 33 of the integrated circuit IC5 is connected to the third terminal of the optical fiber base JK301, pin No. 35 of the integrated circuit IC5 is connected to the coaxial JK1 through a capacitor, and pin No. 17 of the integrated circuit IC5 is connected to the phase detecting module.

The integrated circuit IC5 (model number PCM9210, or CS8416, LC89091JA, LC89058WA, AK4117, AK4118, PCM9211, etc.) receives the audio signals from the fiber bench JK301 and the coaxial JK1, and generates an LRCK signal output.

In this embodiment: referring to fig. 2, the digital pll module includes an integrated circuit (digital pll chip) IC13, pin No. 10 of the integrated circuit IC13 is connected to the phase detecting module, and pin No. 2 of the integrated circuit IC13 is connected to the voltage controlled oscillation module through a capacitor.

The integrated circuit IC13 is an MS5351M (or similar chips such as Si5351A, Si5351B, Si5351C, and MS 5351A), generates a signal with the same frequency as the LPCK signal, and generates a phase difference through processing by the phase detection module.

In this embodiment: referring to fig. 2, the phase detection module includes an integrated circuit (phase detector chip) IC1081, a pin 14 of the integrated circuit IC1081 is connected to the digital receiving module, a pin 3 of the integrated circuit IC1081 is connected to the digital phase-locked loop module, and a pin 13 of the integrated circuit IC1081 is connected to the voltage-controlled oscillation module.

The integrated circuit IC1081 is 74HC4046, compares the same frequency signal with the LPCK signal, and outputs the potential difference between the same frequency signal and the LPCK signal to the voltage-controlled oscillation module.

In this embodiment: referring to fig. 2, the voltage controlled oscillation module includes an active voltage controlled crystal oscillator Y1801, a pin 3 of the active voltage controlled crystal oscillator Y1081 is connected to the digital phase-locked loop module, a pin 1 of the active voltage controlled crystal oscillator Y1081 is connected to the IC66, and a pin 3 of the IC66 is connected to a pin 13 of the IC1081 through a resistor.

An oscillation signal is output to the integrated circuit IC13 according to the potential difference signal, so that the phase of the audio signal output from the No. 6 pin of the integrated circuit IC13 is corrected to be the same as the phase of the LRCK signal and the phase of the input audio signal, and clock jitter when the audio signal is received is eliminated. The active voltage controlled crystal oscillator Y1801 is a 3.3V active voltage controlled oscillator, and the frequency is 24MHz, 25MHz, 27Mhz and the like.

The utility model discloses a theory of operation is: the digital receiving module receives input audio, generates an LRCK signal and outputs the LRCK signal to the phase discrimination module, and the digital phase-locked loop module generates a signal with the same frequency as the LPCK signal and outputs the signal to the phase discrimination module; and the phase discrimination module compares the LPCK signal with the same-frequency signal and outputs the phase difference between the LPCK signal and the same-frequency signal to the voltage-controlled oscillation module, and the voltage-controlled oscillation module changes the output audio signal of the digital phase-locked loop module according to the phase difference so that the phases of the output audio signal and the LRCK signal are consistent.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A circuit for eliminating clock jitter generated during digital audio transmission by using PLL technique, comprising:

the circuit for eliminating clock jitter generated during digital audio transmission by utilizing the PLL technology comprises the following steps:

2. The circuit for removing clock jitter during digital audio transmission by using PLL technique according to claim 1, wherein the digital receiving module comprises an integrated circuit IC5, pin 33 of IC5 is connected to the third terminal of JK301, pin 35 of IC5 is connected to the coaxial JK1 through a capacitor, and pin 17 of IC5 is connected to the phase detection module.

3. The circuit for removing clock jitter during digital audio transmission using PLL technique of claim 1, wherein the digital phase-locked loop module comprises an IC13, pin 10 of the IC13 is connected to the phase detection module, and pin 2 of the IC13 is connected to the voltage controlled oscillation module through a capacitor.

4. The circuit for removing clock jitter during digital audio transmission using PLL technique of claim 1, wherein the phase detecting module comprises an IC1081, pin No. 14 of the IC1081 is connected to the digital receiving module, pin No. 3 of the IC1081 is connected to the digital phase-locked loop module, and pin No. 13 of the IC1081 is connected to the voltage controlled oscillation module.

5. The circuit of claim 4, wherein the voltage controlled oscillator module comprises an active voltage controlled crystal Y1801, pin No. 3 of the active voltage controlled crystal Y1081 is connected to the digital phase locked loop module, pin No. 1 of the active voltage controlled crystal Y1081 is connected to the IC66, and pin No. 3 of the IC66 is connected to pin No. 13 of the IC1081 through a resistor.