KR20030072671A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of minimizing the silicidation of polysilicon. CONSTITUTION: A semiconductor substrate(41) is defined to an active region and an isolation region. A polysilicon gate(51a) and a capping layer are sequentially stacked. Germanium ions are implanted into the substrate. After removing the capping layer, an LDD region(55) is formed. After forming a spacer(61) at both sidewalls of the polysilicon gate(51a), a source/drain(63) is formed in the substrate. A metal silicide layer(65) is formed on the surface of the source/drain and the polysilicon gate.

Description

Method for fabricating semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can improve the electrical characteristics of the device by minimizing the silicide formation problem of the gate layer.

A method of manufacturing a semiconductor device according to the prior art will be described with reference to FIGS. 1 to 6.

1 to 6 are cross-sectional views of processes for explaining a method of manufacturing a semiconductor device according to the prior art.

In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1, a trench device isolation film 13 separating a device isolation region and a device region in advance in a semiconductor substrate 11 to secure a region where a device is to be formed first. To form.

Then, as shown in FIG. 2, the wells 15 are formed by performing ion implantation into the semiconductor substrate 11 in the element formation region while the region where the element is not formed is covered with the photosensitive layer 14. Remove (14).

Subsequently, as shown in FIG. 3, the gate oxide layer and the polysilicon or silicon germanium layer are sequentially stacked on the semiconductor substrate 11, and then, the gate oxide layer 17 is selectively removed using a gate mask (mask). ) And the gate electrode 19 are formed.

Next, as illustrated in FIG. 4, LDD ions are sequentially formed by sequentially performing ion implantation to form an LDD ion implantation layer and a halo ion implantation layer in the semiconductor substrate 11 below both sides of the gate electrode 19. The injection layer 21 and the haloion injection layer 23 are formed.

Subsequently, as shown in FIG. 5, a buffer oxide layer 25 is formed on the gate electrode 19 and the gate oxide layer 17, and then an insulating film spacer 27 is formed thereon.

Next, as illustrated in FIG. 5, the source / drain forming impurities are implanted into the semiconductor substrate 11 below both sides of the insulating film spacer 27 to form the source / drain 29.

Next, as shown in FIG. 6, cobalt is deposited on the upper surface of the entire structure, and then the first and second heat treatment processes are performed on the surface of the gate electrode 19 and the source / drain 29 to form a silicide layer ( 31).

However, according to the prior art as described above, depending on the LDD ion implantation layer and the source / drain depth (that is, the junction depth), problems such as deterioration of device characteristics, that is, a hot carrier effect and a short channel effect, may be exhibited. Formation is required.

In addition, the source / drain may first deposit a metal layer capable of reacting with silicon atoms in the substrate in advance and then perform one or two heat treatments as shown in FIG. Through the process of selectively forming a silicide layer through it can solve the problem of resistance.

However, the LDD layer has a problem that the parasitic resistance is increased to obstruct the flow of electricity as the shallow junction is gradually made, which must be solved as the semiconductor device decreases.

Therefore, as described above, as the size of the device decreases when using the prior art, in the case of the MOSFET, the short channel effect and the increase of the parasitic resistance cause difficulty in device operation and decrease in device performance. Formation of silicide together with the formation leads to a technique of lowering contact resistance.

However, in the case of the shallow junction region in which silicide is not formed, the problem of increasing parasitic resistance cannot be solved.

Accordingly, the present invention has been made to solve the above problems of the prior art, it is possible to minimize the silicide of the polysilicon to provide a method for manufacturing a semiconductor device that can be expected to improve the device characteristics and yield according to the device performance The purpose is.

1 to 6 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the prior art.

7 to 13 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the present invention.

[Description of Drawing Reference]

41 semiconductor substrate 43 trench isolation film

45 photosensitive film 47 well

49 gate oxide film 51 polysilicon

53 capping layer 55 LDD ion implantation layer

57: halo ion implantation layer 59: buffer oxide film

61 insulating film spacer 63 source / drain

65 metal silicide film

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: limiting a semiconductor substrate to an element region and an isolation region; Stacking a gate layer and a capping layer on the semiconductor substrate; Patterning the capping layer and the gate layer to form a capping layer pattern and a gate layer pattern; Implanting germanium ions into the semiconductor substrate below both sides of the capping layer pattern; Removing the capping layer pattern and forming an LDD ion implantation layer in the semiconductor substrate under both sides of the gate layer pattern; Forming spacers on both sides of the gate layer pattern, and then forming source / drain in the semiconductor substrate under both spacers; And forming a metal silicide layer on the source / drain and gate layer pattern surfaces.

(Example)

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

7 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

According to the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 7, first, a trench device isolation film 43 for separating a device isolation region and a device region in advance in the semiconductor substrate 41 to secure a region where a device is to be formed. ). At this time, to form the trench isolation layer 43, an STI process technology capable of reducing the area electrically separated between the devices according to the high integration of the device with little bird's beak is applied.

Then, as shown in FIG. 8, the wells 47 are formed by performing ion implantation into the semiconductor substrate 41 in the element formation region while covering the photosensitive film 45 in the region where the element is not to be formed. The photosensitive film 45 is removed. In this case, two repeated processes are performed in the above-described method to implement different kinds of devices. For example, in the case of an NMOSFET, a P well using boron is formed, and in the case of a PMOSFET, an N well using phosphorus and an acenic is formed.

Subsequently, as shown in FIG. 9, the gate oxide layer 49, the polysilicon or silicon germanium layer 51, and the capping layer 53 are sequentially stacked on the semiconductor substrate 41. In this case, deposition of the capping layer 53 may be performed after the doping process is performed in case of additional doping of only the gate. In addition, when the capping layer 53 is deposited, an oxide-based material such as HLD and TEOS and a nitride-based material such as SiN and Si ₃ N ₄ are used. In addition, the deposition thickness of the capping layer 53 has a range of 300 to 1000 kPa.

Then, as shown in FIG. 10, these are selectively removed by a gate mask (not shown) to form the gate oxide film pattern 49a, the gate electrode 51a, and the capping layer pattern 53a. In this case, the capping layer pattern 53a prevents ion implantation into polysilicon to form the gate electrode when the front surface ion implantation is performed without a mask. In addition, the capping layer pattern 53a may be removed immediately after the Ge ion implantation process, and may be removed immediately before formation of a subsequent spacer. At this time, a wet solution is used to remove the capping layer, and a solution of HF series is used.

On the other hand, the doping of the gate electrode may be doped at the same time during the subsequent source / drain formation process or ion implantation may be performed before gate patterning if additional doping is required.

Subsequently, germanium (Ge) is ion-implanted so that germanium is implanted only in the semiconductor substrate where a shallow junction is formed. At this time, germanium is used as an ion source during the ion implantation process, and ionization energy is in the range of 5 KeV to 100 KeV, and dose is in the range of 1E14 to 2E15.

In addition, the tilt and twist during the ion implantation process are in the range of 0 to 60 ° and 0 to 360 °, respectively.

On the other hand, a great feature of germanium ion implantation is that the Si material can be changed to Si-Ge-based material, which increases the doping efficiency of the dopant. Reducing the depth of implantation helps to form shallow junctions.

However, in order to form cobalt silicide, Ge ions interfere with the reaction between Si atoms and Co atoms during cobalt deposition followed by subsequent heat treatment, and thus have localized segregation. Injection volume control is very important. In addition, in the case of polysilicon which is particularly susceptible to silicide formation, it is preferable not to ion implant.

Therefore, by using a technique to form a capping layer on the polysilicon as a layer to prevent the Ge ion implantation.

Next, as shown in FIG. 11, after performing the Ge ion implantation process, LDD ion implantation is performed to form the LDD ion implantation layer 55 in the semiconductor substrate 41 under both sides of the gate electrode 51a. . In this case, as the ion source during the LDD ion implantation process, an anionic or antimony is used in the case of NMOS, and boron fluorine (BF ₂ ) or indium (indium) is used in the case of PMOS. In addition, the energy during the ion implantation process is in the range of 2 KeV to 30 KeV, the dose is in the range of 1E14 to 1E15, and the tilt angle and the twist angle proceed to 0 °, respectively.

Then, by forming the LDD ion implantation layer 55, the electric field of the carriers flowing between the source and the drain is controlled. In this region, the depth and resistance of the LDD region become important for the carrier flow between the source and drain to be controlled.

In addition, this region reduces the size of the device, but the operating voltage of the device does not decrease, resulting in an undesired flow of carriers due to the concentration of very high electric fields in a portion of the channel drain, making it difficult to operate the device. Minimize the phenomenon.

However, a short channel effect characteristic may occur in which the length of the channel is reduced and the threshold voltage is lowered.

Therefore, Ge ion implantation is performed in this region to minimize the parasitic resistance caused by the doping efficiency increase.

Subsequently, ion implantation is further performed at a tilt angle to form a halo ion implantation layer 57 around the LDD ion implantation layer 55 to mitigate short channel effects.

Then, as shown in FIG. 12, after forming the buffer oxide film 59 and the insulating film spacer 61 on the side of the gate electrode 51a, the source and drain in the semiconductor substrate 41 under both sides of the insulating film spacer 61. (63) is formed.

Subsequently, a large amount of ion implantation and RTP annealing are performed so that a high concentration of dopant may exist in the source and drain 63 and the gate electrode 51a. At this time, the gate electrode 51a and the source / drain 63 region are brought into contact with the metal to apply an operating voltage, thereby selectively controlling the flow of carriers.

Then, as shown in FIG. 13, in order to lower the contact resistance with the metal, a metal, for example, cobalt, for example, is deposited to a thickness of 80 to 150 kPa on the upper surface of the entire structure, followed by heat treatment to process the gate electrode 51a and the source. After the silicon in the upper portion of the drain 63 reacts with the metal to form the silicide film 65, the unreacted and remaining residues are removed. At this time, after depositing cobalt Ti or TiN is deposited as a capping layer. In the case of Ti, it is deposited to a thickness of 80 to 150 kPa, and in the case of TiN to 200 to 300 kPa thick.

In addition, the chamber atmosphere is maintained at 100% of N ₂ during the first and second heat treatment, and the unreacted material removal process performed after the first heat treatment uses a wet solution. First, SC-1 solution (NH ₄ OH) is used. : H ₂ O ₂ : H ₂ O = 0.2: 1: 10) at 50 ± 5 ° C. for 10-15 minutes.

Subsequently, using SC-2 solution (HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5) to proceed to 50 ± 5 ℃ for 5 to 10 minutes.

And the temperature and time at the time of secondary heat processing advance in the range of 750-800 degreeC and 20-40 second, respectively.

As described above, the semiconductor device manufacturing method according to the present invention has the following effects.

According to the method of manufacturing a semiconductor device according to the present invention, by implanting Ge only in the LDD region where the shallow junction is formed, the doping efficiency of the dopant implanted to form the junction can be increased, thereby reducing the parasitic resistance of the junction. have.

In addition, by depositing a capping layer on polysilicon prior to Ge ion implantation, it is possible to minimize the problem of formation of silicides of polysilicon due to the presence of Ge, thereby improving device characteristics and yields by increasing device performance.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (13)

Defining a semiconductor substrate as an element region and an isolation region; Stacking a gate layer and a capping layer on the semiconductor substrate; Patterning the capping layer and the gate layer to form a capping layer pattern and a gate layer pattern; Implanting germanium ions into the semiconductor substrate below both sides of the capping layer pattern; Removing the capping layer pattern and forming an LDD ion implantation layer in a semiconductor substrate below both sides of the gate layer pattern; Forming spacers on both sides of the gate layer pattern, and then forming a source / drain in the semiconductor substrate under the spacers; And Forming a metal silicide film on the source / drain and gate layer pattern surfaces. The method of claim 1, wherein the gate layer comprises a gate oxide layer and a polysilicon layer. The method of claim 1, wherein an oxide-based material such as HLD and TEOS and a nitride-based material such as SiN and Si ₃ N ₄ are used as the material for forming the capping layer. The method of claim 1, wherein the capping layer comprises 300 to 1000 Å thick. The method of claim 1, wherein the germanium ion implantation process using germanium as an ion source, the ionization energy is 5 KeV to 100 KeV and the dose is 1E14 to 2E15, the tilt angle and twist angle at the time of ion implantation are 0 to 60, respectively Method of manufacturing a semiconductor device, characterized in that in the range of 0 and 360 °. The semiconductor device according to claim 1, wherein the LDD ion implantation layer forming process has ionization energy of 2 KeV to 30 KeV and dose of 1E14 to 1E15, and the tilt angle at the time of ion implantation progresses to 0 °. Manufacturing method. The method of claim 1, wherein after the formation of the LDD ion implantation layer, ion implantation using a predetermined tilt angle is further performed to form an additional ion implantation layer around the LDD ion implantation layer. The method of claim 1, wherein the forming of the metal silicide layer, Depositing cobalt with a thickness of 80 to 150 mm on the top surface of the entire structure after forming the source / drain; And forming a cobalt silicide film on the surface of the source / drain and gate layer pattern after the heat treatment of the cobalt. The method of claim 8, further comprising forming a capping layer formed of Ti or TiN after depositing the cobalt. The method of claim 9, wherein the capping layer is formed to a thickness of 80 to 150 GPa in the case of Ti, and 200 to 300 GPa in the case of TiN. The method of claim 8, wherein the heat treatment is composed of primary and secondary heat treatment, the temperature and time of the first heat treatment is 250 to 550 ℃ and 30 to 60 seconds, respectively, the temperature and time of the second heat treatment, respectively Method for manufacturing a semiconductor device, characterized in that it is 20 to 40 seconds at 750 to 800 ℃. The method of claim 11, further comprising removing the unreacted material after the first heat treatment, wherein the removing is performed using a wet solution. The method of claim 12, wherein the unreacted material removal process is performed for 10 to 15 minutes at 50 ± 5 ℃ using an SC-1 solution (NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.2: 1:10) After proceeding using a SC-2 solution (HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5) at 50 ± 5 ℃ for a semiconductor device manufacturing method characterized in that for 5 to 10 minutes.