KR20030069272A - Semiconductor device and Method of fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a fabricating method therefor are provided to prevent a bridge without influencing the surface area of high cylindrical lower electrodes by forming a thin support pattern between the sidewalls of the cylindrical lower electrodes. CONSTITUTION: A lower interlayer dielectric(104) is formed on a semiconductor substrate(101). A plurality of lower electrodes(121a) are formed on the lower interlayer dielectric. The support pattern(109b) is interposed between the sidewalls of at least two of the lower electrodes wherein the support pattern is separated from the lower interlayer dielectric. The lower electrodes include buried contact plugs(106) penetrating the lower interlayer dielectric, electrically connected to a predetermined region of the semiconductor substrate through the buried contact plug.

Description

Semiconductor device and method of fabricating the same

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a capacitor and a method for manufacturing the same.

As semiconductor devices become highly integrated, the size of the cells is reduced, making it difficult to form capacitors with sufficient capacitance. In particular, in the case of a DRAM cell composed of one MOS transistor and one capacitor, the capacitance of the capacitor is an important problem.

A widely used method for increasing the capacitance of a capacitor is a method of increasing the area of the capacitor. However, as the planar area decreases due to high integration of semiconductor devices, a method of manufacturing a capacitor having a large height lower electrode is currently used to increase the area of the capacitor.

1 is a cross-sectional view illustrating a conventional semiconductor device having a lower electrode of a cylindrical capacitor.

An interlayer insulating film 2 is laminated on the semiconductor substrate 1. The predetermined region of the semiconductor substrate 1 is in contact with the buried contact plug 3 passing through the interlayer insulating film 2. An etch stop film 4 is positioned on the interlayer insulating film 2. The lower electrode 5 is in contact with the upper surface of the buried contact plug 3. The lower electrode 5 increases the area by increasing the height in order to increase the capacitance. At this time, the lower electrodes 5 may be inclined due to the high height to generate the adjacent lower electrodes 5 and the bridge 6.

SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method for manufacturing the same, which can suppress the occurrence of bridges between the lower electrodes when the capacitor is formed with a large cylindrical lower electrode, without reducing the area of the capacitor.

1 is a cross-sectional view illustrating a conventional semiconductor device having a lower electrode of a cylindrical capacitor.

2 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view for describing a semiconductor device taken along the line II ′ in FIG. 2.

4 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device taken along the line II ′ in FIG. 2.

Provided are a semiconductor device and a method of manufacturing the same for achieving the above technical problem. The semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes formed on a semiconductor substrate and a support pattern interposed between at least two sidewalls of the lower electrodes. The support pattern is spaced apart from the semiconductor substrate. The support pattern is thin and is made of an insulating film having an etch selectivity with respect to an oxide film used as a general interlayer insulating film.

In the method of manufacturing a semiconductor device according to the present invention, a first interlayer insulating film and a support film are sequentially formed on a semiconductor substrate, and the support film is patterned to form a preliminary support pattern for exposing a predetermined region of the first interlayer insulating film. A preliminary lower portion which forms a second interlayer insulating film on the entire surface of the semiconductor substrate having the preliminary supporting pattern, and continuously patterns the second interlayer insulating film, the preliminary supporting pattern and the first interlayer insulating film to expose a predetermined region of the semiconductor substrate; A support pattern interposed between electrode holes and the at least two preliminary lower electrode holes is formed. Lower electrode holes are formed by wet etching the second interlayer insulating layer and the first interlayer insulating layer forming sidewalls of the preliminary lower electrode holes. In this case, protrusions protruding from the support pattern are formed on sidewalls of the lower electrode holes. Cylindrical lower electrodes are formed in the lower electrode holes. The sidewall of the lower electrode surrounds the protrusion of the support pattern. The second interlayer insulating film and the first interlayer insulating film are wet etched and removed. As a result, the outer walls of the lower electrodes are exposed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents can be thorough and complete, and the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

2 and 3 are a plan view and a cross-sectional view, respectively, for explaining a semiconductor device according to an embodiment of the present invention. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

Referring to FIG. 2, a plurality of cylindrical lower electrodes 121a are positioned on the semiconductor substrate 101. A support pattern 109b is interposed between the sidewalls of the lower electrodes 121a. The support pattern 109b is in contact with the sidewalls of the four lower electrodes 121a, and the bottom electrode 121a is in contact with one support pattern 109a. In addition, the support pattern 109b may be in contact with at least two lower electrodes 121a. As a result, the lower electrodes 121a may be prevented from being inclined by the support patterns 109b.

The support pattern 109b is preferably made of an insulating film having an etch selectivity with respect to an oxide film used as a general interlayer insulating film, such as a silicon nitride film.

Referring to FIG. 3, a lower interlayer insulating film is positioned on the semiconductor substrate 101. The predetermined region of the semiconductor substrate 101 contacts the buried contact plug 106 penetrating the lower interlayer insulating film 104. An etch stop layer 107 is disposed on the lower interlayer insulating layer 104. The upper surface of the buried contact plugs 106 is in contact with the lower surface of the lower electrodes 121a. A support pattern 109b is interposed between the lower electrodes 121a. The support pattern 109b is spaced apart from the etch stop layer 107.

4 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device taken along the line II ′ in FIG. 2.

Referring to FIG. 4, a sound separation layer 102 defining an active region is formed on the semiconductor substrate 101. The impurity diffusion layer 103 is formed by implanting impurity ions into the surface of the active region. A buried contact plug 106 is formed on an entire surface of the semiconductor substrate having the impurity diffusion layer 103 and penetrates the lower interlayer insulating film 104 to contact a predetermined region of the impurity diffusion layer 103. ). The buried contact plugs 106 are preferably formed of doped polysilicon. Another lower conductive layer pattern may be formed between the impurity diffusion layer 103 and the lower surface of the buried contact plug 106. For example, it is preferable to form a self-aligning contact pad.

An etch stop layer 107 is formed on the entire surface of the semiconductor substrate including the top surfaces of the buried contact plugs 106. The etch stop film 107 is preferably formed of an insulating film having an etching selectivity, for example, a silicon nitride film, with respect to an oxide film used as a general interlayer insulating film. The first interlayer insulating layer 108 and the supporting layer 109 are sequentially stacked on the etch stop layer 107. The first interlayer insulating film is preferably formed of a CVD silicon oxide film. The support layer 109 may be electrically insulated, and may be formed of an insulating layer having an etching selectivity with respect to the first interlayer insulating layer 108, for example, a silicon nitride layer.

Referring to FIG. 5, the support layer 109 is patterned to form a preliminary support pattern 109a exposing a predetermined region of the first interlayer insulating layer 108. A second interlayer insulating film 110 is formed on the entire surface of the semiconductor substrate including the preliminary support pattern 109a. The second interlayer insulating film 110 may be formed of an insulating film having the same etching selectivity as the first interlayer insulating film 108, for example, a CVD silicon oxide film.

Referring to FIG. 6, the buried contact plug 106 may be patterned by continuously patterning the second interlayer insulating layer 110, the preliminary support pattern 109a, the first interlayer insulating layer 108, and the etch stop layer 107. The preliminary lower electrode holes 120 and the support pattern 109b exposing the upper surfaces of the layers) are formed. In this case, the support pattern 109b is exposed on sidewalls of the preliminary lower electrode holes 120.

Referring to FIG. 7, the lower electrode holes 120a may be formed by wet etching the second interlayer insulating layer 110 and the first interlayer insulating layer 108 forming sidewalls of the preliminary lower electrode holes 120. In this case, the support pattern 109b forms a protrusion k protruding from the sidewall of the lower electrode hole 120a at a slow wet etch rate with respect to the first interlayer insulating film 110 and the second interlayer insulating film 108. . At this time, the length of the protrusion (k) may be formed to 50 ~ 200Å.

Referring to FIG. 8, the lower electrode layer 121 is formed on the entire surface of the semiconductor substrate including the lower electrode hole 120a. In this case, the lower electrode layer 121 is formed to surround the protrusion k of the support pattern 109b protruding from the sidewall of the lower electrode hole 120a. The lower electrode layer 121 is preferably formed of doped polysilicon. A buffer insulating layer 125 is formed on the lower electrode layer 121 to fill the inside of the lower electrode hole 120a. The buffer insulating film 125 may be formed of an insulating film having the same etching selectivity as the second interlayer insulating film 110 and the first interlayer insulating film 108, for example, a CVD silicon oxide film.

Referring to FIG. 9, the buffer insulating layer 125 and the lower electrode layer 121 are planarized until the upper interlayer insulating layer 110 is exposed to form lower electrodes 121a.

Referring to FIG. 10, all of the buffer insulating film 125, the second interlayer insulating film 110, and the first interlayer insulating film 108 remaining in the lower electrode hole 120a are removed by wet etching. In this case, all of the first interlayer insulating film 108 under the support pattern 109b is also removed. The support pattern 109b and the etch stop layer 107 are not removed by having an etch selectivity with respect to the buffer insulating layer and the first and second interlayer insulating layers. Accordingly, the support pattern 109b is formed between the sidewalls of the lower electrodes 121a and spaced apart from the etch stop layer 107 by a predetermined height. The etch stop layer 107 prevents the lower interlayer dielectric layer 104 from being etched. Since the support pattern 109b is formed, a bridge, which is caused by tilting the lower electrodes 121a having a large height, may be prevented.

Referring to FIG. 11, a dielectric layer 130 is formed on a surface of the lower electrode 121a, and an upper electrode 135 is formed on the dielectric layer. In this case, the dielectric layer 130 and the upper electrode 135 are also formed on the outer sidewalls of the lower electrode 121a under the support pattern 109b to form an area of a capacitor including the lower electrode, the dielectric layer and the upper electrode. Does not affect.

As described above, according to the present invention, by forming a thin support pattern interposed between the sidewalls of the cylindrical lower electrodes having a large height, it is possible to prevent the bridge without affecting the surface area of the lower electrodes.

Claims (15)

A lower interlayer insulating film formed on the semiconductor substrate; A plurality of lower electrodes formed on the lower interlayer insulating film; And And a support pattern interposed between at least two sidewalls of the lower electrodes, wherein the support pattern is spaced apart from the lower interlayer insulating film. The method of claim 1, And a buried contact plug penetrating the lower interlayer insulating layer, wherein the lower electrodes are electrically connected to a predetermined region of the semiconductor substrate through the buried contact plug. The method of claim 1, A dielectric film formed on a surface of the lower electrodes; And And an upper electrode formed on the dielectric layer, wherein the lower electrode, the dielectric layer, and the upper electrode form a capacitor. The method of claim 1, And the support pattern is interposed between sidewalls of four neighboring lower electrodes, and the sidewalls of the lower electrodes contact one support pattern. The method of claim 1, The support pattern is a semiconductor device, characterized in that the silicon nitride film Sequentially stacking a first interlayer insulating film and a supporting film on the semiconductor substrate; Patterning the support layer to form a preliminary support pattern; Forming a second interlayer insulating film on the semiconductor substrate having the preliminary support pattern; Preliminarily patterning the second interlayer insulating film, the preliminary support pattern, and the first interlayer insulating film to expose a predetermined region of the semiconductor substrate, and a support pattern interposed between the at least two preliminary lower electrode holes. Forming a; Wet etching the second interlayer insulating film and the first interlayer insulating film to form lower electrode holes, and forming protrusions protruding from the support pattern on sidewalls of the lower electrode holes; Forming a lower electrode surrounding the protrusion of the support pattern in the lower electrode holes; And Removing both the second interlayer insulating film and the first interlayer insulating film by wet etching to form a support pattern interposed between sidewalls of the lower electrodes, wherein the support pattern includes the first interlayer insulating film and the second interlayer insulating film. A method of manufacturing a semiconductor device, characterized in that the insulating film has an etch selectivity with respect to. The method of claim 6, Before forming the first interlayer insulating film, Forming an isolation layer defining an active region on the semiconductor substrate; Implanting impurity ions into the active region to form an impurity diffusion layer; Forming a lower interlayer insulating film over the semiconductor substrate having the impurity diffusion layer; Forming a buried contact plug penetrating the lower interlayer insulating film to expose the impurity diffusion layer; And And forming an etch stop layer on the entire surface of the semiconductor substrate including an upper surface of the buried contact plug, wherein the etch stop layer is also patterned when the preliminary bottom electrode hole is formed so that the preliminary bottom electrode hole forms an upper surface of the buried contact plug. A semiconductor device manufacturing method characterized by exposing. The method of claim 7, wherein The buried contact plug is formed of doped polysilicon. The method of claim 7, wherein The etch stop layer is formed of a silicon nitride film. The method of claim 6, And the supporting film is formed of a silicon nitride film. The method of claim 6, Forming the lower electrodes, Forming a lower electrode layer on an entire surface of the semiconductor substrate including the lower electrode hole; Forming a buffer insulating layer on the lower electrode layer to completely fill the lower electrode hole; And Planarizing the buffer insulating film and the lower electrode film until the second interlayer insulating film is exposed. The method of claim 11, And the buffer insulating film is formed of a silicon oxide film. The method of claim 6, After removing the second interlayer insulating film and the first interlayer insulating film, Forming a dielectric film on an entire surface of the semiconductor substrate including inner and outer walls of the lower electrode; And And forming an upper electrode on the dielectric film. The method of claim 6, And the lower interlayer insulating film, the second interlayer insulating film and the first interlayer insulating film are formed of a CVD silicon oxide film. The method of claim 6, And the lower electrodes are formed of a doped polysilicon film.