KR20030066997A - A data output buffer block and a driving method thereof - Google Patents

Abstract

PURPOSE: A data output buffer block and a driving method thereof are provided to reduce the noise and enhance a driving speed by sensing output data of a data output buffer and deciding the phases identity of the output data. CONSTITUTION: A data output buffer block includes a decision portion(404), an intermediate data generation portion, and an output driving portion(406_1 to 406_8). The decision portion decides the phases identity of data inputted between the first bit and the second bit. The intermediate data generation portion generates intermediate data for the first bit if the phases of input data is identical to another, or the intermediate data having the same timing as the input data for the first bit if the phases of data is not identical to another. The output driving portion is controlled by the intermediate data in order to output the data.

Description

Data output buffer block and its driving method {A DATA OUTPUT BUFFER BLOCK AND A DRIVING METHOD THEREOF}

The present invention relates to a data output buffer block, and more particularly, to a data output buffer block and a driving method thereof for finally outputting data stored in a memory cell to a semiconductor device.

In a semiconductor memory device, a data output buffer serves to output data read from a memory cell at a high speed to an external large load capacitor. The data output buffer must meet the DC sink / source current specification, as well as the various speed specifications. Therefore, in the case of the existing data output buffer, a metal oxide semiconductor (hereinafter referred to as metal oxide semiconductor) constituting the data output buffer for fast switching of the output data signal, that is, from low level to high level or from high level to low level. ("MOS"). The size of the transistor is increased.

As a result, when the output data signal swings from the high level to the low level, the ground swings to ground at a very large potential, causing ground to bounc. In addition, if eight output buffers swing simultaneously, the ground bouncing noise becomes larger, which greatly affects address buffers that are tied to the same ground, so that the address buffers that are not actually toggled act as if they were toggled. The device will fail.

Next, this will be described in detail with reference to FIGS. 1 to 3. First, a circuit of a conventional data output buffer is shown in FIG. As shown in FIG. 1, the data output buffer 100 includes an output buffer unit 102, a latch unit 104, and an output driver 106. The data signal din1 to be output through the data output buffer 100 is applied to both the output buffer unit 102 and the latch unit 104, and the output enable signal poe for activating the data output buffer 100 is Only applied to the output buffer section 102. The data output buffer 100 starts operation when the output enable signal poe transitions from the low level to the high level. The output driver control signals dp and dn generated by the output buffer unit 102 by the data signal din1 and the output enable signal poe are applied to the output driver 106 to constitute the output driver 106. The MOS transistor is driven to selectively output the data signal dout. In FIG. 1, the node gndd indicates the ground to which the source of the NMOS transistor MN1 of the output driver 106 is connected.

A circuit for simulating how the eight data output buffers with the configuration shown in FIG. 1 affects ground bouncing is shown in FIG. As shown in FIG. 2, the nodes gndd of the eight data output buffers 100_1,..., 100_8 are grouped into one and addressed by modeling a metal line existing on an actual layout. It is connected to the ground of the input buffer 202. In FIG. 1, the chip select signal csb input to the address input buffer 202 is always in a low state, and a high level (2.2) of transistor-transistor logic is used as a pad to which an address is input from the outside. Assume that V) is provided.

3 is a signal waveform diagram generated in the simulation according to FIG. 2. 1 and 2 together, the effect of the existing data output buffer (100 in FIG. 1) on the ground bounce will be described. After the input data signal din1 falls from the high level to the low level, when the output enable signal poe rises from the low level to the high level, the output driver of the data output buffer (100 in FIG. 1) (106 in FIG. 1). NMOS transistor MN1 is operated, and the output data signal dout1 swings to a low level. At this time, ground bouncing occurs and the ground nd1 of the address input buffer (202 in FIG. 2) is shaken. As a result, as shown in FIG. 3, the node nd2 through the inverter 204 is ground. Will cause glitches.

The greatest ground bounce occurs when the outputs of the data output buffers all have the same phase, that is, when the output data signals all swing from high level to low level. Therefore, some existing products use a method of sequentially operating output drivers, for example, a method of operating the remaining four drivers after a slight time delay after operating the four drivers. There is a problem that the speed is lowered.

SUMMARY OF THE INVENTION The present invention has been proposed to solve such a problem, and an object thereof is to provide a data output buffer which prevents malfunction due to ground bounce while maintaining a certain driving speed.

1 is a circuit diagram of a conventional data output buffer.

2 is a block diagram of a ground bouncing simulation circuit using a conventional data output buffer.

3 is a signal waveform diagram generated in the simulation according to FIG.

4 is a configuration diagram of a data output buffer block according to the first embodiment of the present invention.

5 is a circuit diagram of an example of a phase determination unit constituting the data output buffer block of FIG.

FIG. 6 is a circuit diagram of an example of an output driver constituting the data output buffer block of FIG. 4. FIG.

7 is a signal waveform diagram generated in the simulation according to FIG.

8 is a configuration diagram of a data output buffer block according to the second embodiment of the present invention.

In order to achieve this object, it is proposed by the present invention to have a new configuration as a data output buffer block for outputting a plurality of bits of data. The data output buffer block according to the present invention comprises phase determination means for determining whether the phase of data input between the first and second bits of the plurality of bits is equal, and phase input means for input data between the two bits. If it is determined that the phases are equal to each other, intermediate data having a predetermined time difference with the input data is generated for the first bit; and if it is determined that the phases of the input data are not equal to each other, the data is substantially the same as the input data for the first bit. And intermediate data generating means for generating intermediate data having a timing, and output driving means controlled by the first and intermediate data to output data. The input data and the intermediate data are preferably in phase.

According to this configuration, the data output through the data output buffer is sensed to determine whether they are in phase, and if they are in phase, the MOS transistors of the output driver are sequentially driven. In this way, when the data output is in the same phase, noise caused by ground bounce can be suppressed to prevent glitches generated in the address input buffer. For data outputs in other phases, the drive speed can be increased by operating the output driver without time delay. This can reduce the possibility of malfunction due to ground bounce while maintaining the driving speed to some extent.

The intermediate data generating means is activated when the phases of the input data are the same between the first and second bits, and is activated to delay the input data by a predetermined time with respect to the first bit to generate the intermediate data. It can be configured with a second signal path that is activated if the phases of the input data are not equal to each other between the second bits, thereby generating intermediate data having a timing substantially the same as the input data for the first bit.

In addition, the present invention provides a method of driving a data output buffer block for outputting a plurality of bits of data, comprising: determining whether input data is in phase between two bits, and input data is in phase by phase determination; And the step of outputting the input data to have a predetermined time difference between the two bits if it is determined to be another feature.

If it is determined by the phase determination that the input data are not in phase, it is preferable to further include outputting the input data at the same time between the two bits. The two bits are preferably bits adjacent to each other.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

4 is a circuit diagram for implementing a ground bouncing simulation for a data output buffer block according to a first embodiment of the present invention. Compared with Fig. 2, in that the output driver 406_1, ..., 406_8 of the data output buffers 402_1, ..., 402_8 for each bit have a new configuration, and that the phase determination unit 404 is further provided. Are distinguished. As shown in Fig. 4, the grounds of the eight data output buffers 402_1, ..., 402_8 are all grouped by nodes gndd, which are addressed to model metal lines on the actual layout. It is electrically connected to the ground nd12 of the input buffer 403.

The configuration shown in FIG. 4 will be described. The phase determining unit 404 receives the signals dinb1 and dinb2 from the latches of the data output buffers 402_1 and 402_2 and receives the signals dinb1 and dinb2 from the input data signals din1 and din2 respectively. It is determined whether the phases are the same, and a signal det1 indicating the determination result is generated and provided to the output drivers 406_1 and 406_2 of the data output buffers 402_1 and 402_2. The output drivers 406_1 and 406_2 selectively allow a predetermined time difference between the output data signals dout1 and dout2 in accordance with the phase determination signal det1 received from the phase determination unit 404. That is, when the phase determination signal det1 indicates that the input data signals din1 and din2 are in phase, the output driving units 406_1 and 406_2 allow a predetermined time difference between the output data signals dout1 and dout2. If the phase determination signal det1 indicates that the input data signals din1 and din2 are not in phase, the output drivers 406_1 and 406_2 output the output data signals dout1 and dout2 at the same timing.

FIG. 5 is a circuit diagram of an example of the phase determination unit 404 constituting the data output buffer block of FIG. 4. As shown in FIG. 5, the phase determiner 404 may be configured of NAND gates 502, 504, 506, 508, and 512 and inverters 510 and 514. NAND gate 502 is input to the two input terminals of the output signal (dinb1, dinb2) of the latch portion of the data output buffer (402_1, 402_2 in Figure 4), the output signal is the input terminal of the NAND gate (504, 506) Is provided. The NAND gate 504 receives the signal dinb1 and the output signal of the NAND gate 502 as two input signals, and the output signal is provided as an input signal of the NAND gate 508. The NAND gate 506 receives the signal dinb2 and the output signal of the NAND gate 502 as two input signals, and the output signal is provided as another input signal of the NAND gate 508. The output signal of the NAND gate 508 is provided to an input terminal of the inverter 510, and the output signal of the inverter 510 is provided as an input signal of the NAND gate 512. An output enable signal poe is received as another input signal of the NAND gate 512, an output signal of the NAND gate 512 is provided as an input signal of the inverter 514, and the inverter 514 is a phase determination signal ( det1) is printed.

Next, the operation of the phase determining unit 404 will be described. If both signals dinb1 and dinb2 are of the same phase, for example, a high level signal, the NAND gate 502 outputs a low level signal and provides it as an input terminal of the NAND gates 504 and 506. Therefore, the NAND gates 504 and 506 both output a high level signal, and the NAND gate 508 outputs a low level signal. The low level signal output from the NAND gate 508 is inverted by the inverter 510 and applied to the input terminal of the NAND gate 512 as a high level signal. At this time, the output enable signal transitions to the high level. Therefore, the NAND gate 512 outputs a low level signal, and the inverter 514 outputs a high level signal as the phase determination signal det1. If both signals dinb1 and dinb2 are low level signals, the NAND gates 504 and 506 output the high level signals. Therefore, as in the case where both signals dinb1 and dinb2 are high level signals, a high level signal is output as the phase determination signal det1. Therefore, when the two signals dinb1 and dinb2 are in phase, the phase determination unit 404 outputs a high level signal as the phase determination signal det1.

On the other hand, when the two signals dinb1 and dinb2 are not in phase, for example, when the signal dinb1 is a high level signal and the signal dinb2 is a low level signal, the NAND gate 502 is a high level signal. The NAND gate 504 outputs a low level signal, and the NAND gate 506 outputs a high level signal. Accordingly, the NAND gate 508 outputs a high level signal, and the inverter 510 inverts the signal and outputs a low level signal to the NAND gate 512. The output enable signal poe is at a high level, but the NAND gate 512 outputs a high level signal, and the inverter is inverted to output a low level signal as the phase determination signal det1. That is, if the two signals dinb1 and dinb2 are not in phase, the phase determination unit 404 outputs a low level signal as the phase determination signal det1.

FIG. 6 is a circuit diagram of an example of an output driver constituting the data output buffer block of FIG. 4. As shown in Fig. 6, two intermediate data generating circuits 602 and 604 and a driving circuit 606 are provided. The signal dp1 provided from the buffer portion of the data output buffer 402_1 of FIG. 4 is provided to the intermediate data generation circuit 602 and the driving circuit 606, and the signal din1 is the intermediate data generation circuit 604. And a driving circuit 606. The intermediate data generation circuits 602 and 604 generate intermediate data dp1 'and dn1', respectively, and provide the intermediate data dp1 'and dn1' to the driving circuit 606. The drive circuit 606 is not only controlled by the signals dp1 and dn1, but also by the intermediate data dp1 'and dn1' to finally output the output data dout1.

As shown in FIG. 6, the intermediate data generation circuit 602 is a PMOS transistor MP61, an NMOS transistor MN61, MN62, MN63, NAND gates 612, 614, and an inverter 608, 610, 616. Can be configured. The NMOS transistor MN63 has both a source and a drain grounded to form a gate capacitor.

First, as described with reference to FIG. 5, when the two signals dinb1 and dinb2 have the same phase, the phase determination signal det1 is a high level signal, and thus the NAND gate 612 is accumulated in the gate of the NMOS transistor MN63. It operates as an inverter for the signal caused by the charged charge. Since the MOS transistors MP61, MN61, and MN62 are configured to have a smaller size than the MOS transistors constituting the conventional data output buffer, the signal dp1 is a path formed of the NMOS transistor MN63 and the NAND gate 612. During the delay, a predetermined time (approximately 2.5 ns in this embodiment) is delayed and output as a signal dp1 '. Therefore, if the phases of the two signals dinb1 and dinb2 are the same, the signal dp1 'is delayed by a predetermined time compared to the signal dp1. However, when the phase determination signal det1 is a low level signal because the phases of the two signals dinb1 and dinb2 are not equal to each other, the NAND gate 612 may apply a signal level to the gate of the NMOS transistor MN63. Since the signal always outputs a high level, the signal dp1 'is determined by the signal that passes through the path of the inverters 608 and 610. The inverters 608 and 610 are configured such that the time passed by the signal dp1 becomes substantially zero, so that when the two signals dinb1 and dinb2 are not in phase, the signals dp1 and dp1 'are substantially equal. Have the same timing.

The intermediate data generation circuit 604 is configured in the same manner as the intermediate data generation circuit 602. That is, the intermediate data generation circuit 604 may include a PMOS transistor MP62, NMOS transistors MN64, MN65, and MN66, NAND gates 622 and 624, and inverters 618, 620, and 626. The intermediate data generation circuit 604 also operates in the same manner as the intermediate data generation circuit 602, so that when the two signals dinb1 and dinb2 have the same phase, the signal dn1 'is delayed by a predetermined time compared to the signal dn1. If the two signals dinb1 and dinb2 are not in phase, the signal dn1 'has substantially the same timing as the signal dn1.

The driving circuit 606 may include a first driver 628 controlled by the signals dp1 and dn1 and a second driver 630 controlled by the signals dp1 'and dn1'. In the first driver 628, when the signal dp1 is at a low level, the PMOS transistor MP63 is turned on so that the node nd6 is connected to the power supply terminal. When the signal dn1 is at a high level, the NMOS transistor MN67 is turned on. Node nd6 is connected to the ground terminal. In the second driver 630, when the signal dp1 ′ is at the low level, the PMOS transistor MP64 is turned on to connect the node nd6 to the power supply terminal. When the signal dn1 ′ is at the high level, the NMOS transistor MN67 is turned on. Is turned on to connect the node nd6 with the ground terminal. As described above, when the two signals dinb1 and dinb2 have the same phase, the signals dp1 'and dn1' have a predetermined time difference with respect to the signals dp1 and dn1, respectively, so that the change in the output signal dout1 is slowed down. If the two signals dinb1 and dinb2 are not in phase, the signals dp1 'and dn1' have substantially the same timing with respect to the signals dp1 and dn1, respectively, so that the change in the output signal dout1 is faster.

7 is a signal waveform diagram generated in the simulation according to FIG. 4. It demonstrates, referring FIG. 4 and FIG. 6 together. As shown in FIG. 7, when the output enable signal poe rises from the low level to the high level while the input data signals din1 and din2 are lowered from the high level to the low level, the phase determination unit (FIG. 5). 404 generates and outputs a phase determination signal det1 rising from a low level to a high level. The intermediate data generation circuit 604 constituting the output driver 406_1 of the phase output buffer 402_1 of FIG. 4 by the phase determination signal 404 of FIG. 5 is a signal dn1 delayed by a predetermined time compared to the signal dn1. ') Is generated and provided to the second driver 630 of the driving circuit 606, so that the change of the output data dout1 becomes slow. However, in the case of the data output buffer 402_2 of FIG. 4, unlike the data output buffer 402_1 of FIG. 4, the output data is normally changed. Accordingly, even when data having the same phase is output through the data output buffers 402_1 and 402_2, the effect on ground bounce is reduced, thereby preventing glitches at the node nd22 of the address input buffer 403.

8 is a configuration diagram of a data output buffer block according to a second embodiment of the present invention. In the embodiment shown in Fig. 4, the phases are compared only between the data output buffers 402_1 and 402_2, so that data output from one data output buffer (402_1 in this embodiment is selectively delayed), but the embodiment shown in Fig. 8 is compared. In the example, the phase of the data to be output between all adjacent data output buffers is compared so that the data output at any one data output buffer is selectively delayed.

In FIG. 8, the phase determining unit 804_1 determines whether the data to be output between the data output buffers 802_1 and 802_2 is the same, and if the phases are the same, the data in any one of the data output buffers 802_1 and 802_2. Slows down the output. The phase determiner 804_2 also operates on the data output buffers 802_3 and 802_4 in the same manner, and the phase determiner 804_3 operates on the data output buffers 802_5 and 802_6, and the phase determiner 804_4 controls the data. It operates on the output buffers 802_7 and 802_8. The embodiment shown in FIG. 8 is more secure for ground bounce than the embodiment shown in FIG. 4.

The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

According to the configuration of the present invention as described above, the data output through the data output buffer is sensed to determine whether or not the same phase, and if the same phase, the MOS transistor of the output driver is sequentially driven. In this way, when the data output is in the same phase, noise caused by ground bounce can be suppressed to prevent glitches generated in the address input buffer. For data outputs in other phases, the drive speed can be increased by operating the output driver without time delay. This can reduce the possibility of malfunction due to ground bounce while maintaining the driving speed to some extent.

Claims (6)

In the data output buffer block for outputting a plurality of bits of data, Phase determination means for determining whether the phase of the data input between the first and second bits of the plurality of bits is the same; If the phase determination means determines that the phases of the input data are equal to each other between the two bits, intermediate data having a predetermined time difference with the input data is generated for the first bit, and the phase of the input data is Intermediate data generating means for generating intermediate data having substantially the same timing as said input data for said first bit if it is determined that they are not equal to each other; Output driving means controlled by the first and intermediate data to output data; And a data output buffer block. The method of claim 1, The intermediate data generating means A first signal path which is activated when the phases of the input data are identical with each other between the first and second bits to generate the intermediate data by delaying the input data by a predetermined time with respect to the first bit; If the phases of the input data are not equal to each other between the first and second bits, the second signal path is activated to generate the intermediate data having a timing substantially the same as the input data for the first bit. And a data output buffer block. The method of claim 1, And the input data and the intermediate data are in phase with each other. The method of claim 1, In the method for driving a data output buffer block for outputting a plurality of bits of data, Determining whether the input data is in phase between the two bits, If it is determined by the phase determination that the input data are in phase, outputting the input data by having a predetermined time difference between the two bits; And a data output buffer block. The method of claim 4, wherein And outputting the input data at the same time between the two bits if the input data determines that the input data is not in phase with the phase determination. The method of claim 4, wherein And the two bits are bits adjacent to each other.