KR20030065817A - Circuit of driving pixel thin flim transistor liquid display - Google Patents

Circuit of driving pixel thin flim transistor liquid display Download PDF

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KR20030065817A
KR20030065817A KR1020020005834A KR20020005834A KR20030065817A KR 20030065817 A KR20030065817 A KR 20030065817A KR 1020020005834 A KR1020020005834 A KR 1020020005834A KR 20020005834 A KR20020005834 A KR 20020005834A KR 20030065817 A KR20030065817 A KR 20030065817A
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gate
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KR100852812B1 (en
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김서윤
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비오이 하이디스 테크놀로지 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G02F1/136245—Active matrix addressed cells having more than one switching element per pixel having complementary transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

PURPOSE: A pixel driving circuit of a thin film transistor liquid crystal display is provided to realize higher gray scales than gray scales supported by a drive IC by dividing a pixel into two sub-pixels and writing different signals in the sub-pixels. CONSTITUTION: First and second sub-pixels(10,12) are formed at pixel areas formed by a plurality of gate lines(20,22) and a plurality of data lines(30). First TFT(Thin Film Transistor)s (50) transmit data signals transmitted through the data lines to first sub-pixels by signals of first gate lines. Second TFTs(52) transmit data signals transmitted through the data lines to second sub-pixels by signals of first gate lines. Third TFTs(54) supply common voltage transmitted through common electrode lines(40) to the first and second sub-pixels by signals of second gate lines. The signals of the gate lines have step type pulse signals having first and second intervals. In the first interval, only the first TFTs are turned on. In the second interval, all the TFTs are turned on. After the second interval, only the third TFTs are turned on to write voltage values of different gray scales in the first and second sub-pixels for recognizing an intermediate value.

Description

박막트랜지스터 액정표시장치의 화소 구동 회로{CIRCUIT OF DRIVING PIXEL THIN FLIM TRANSISTOR LIQUID DISPLAY}Pixel driving circuit for thin film transistor liquid crystal display device {CIRCUIT OF DRIVING PIXEL THIN FLIM TRANSISTOR LIQUID DISPLAY}

본 발명은 박막트랜지스터 액정표시장치(Thin Flim Transistor LiquidDisplay: TFT-LCD)의 화소 구동 회로에 관한 것으로, 특히 TFT-LCD의 한 화소를 2개의 서브 화소로 분할하고 각각의 서브 화소에 서로 다른 신호를 써넣음으로써, 드라이브 IC에서 지원하는 계조보다 한 단계 또는 그 이상의 계조 구현이 가능하도록 한 TFT-LCD의 화소 구동 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel driving circuit of a thin film transistor liquid crystal display (TFT-LCD). In particular, one pixel of a TFT-LCD is divided into two sub-pixels, and a different signal is applied to each sub-pixel. By writing, the present invention relates to a pixel driving circuit of a TFT-LCD that enables one or more levels of gradation to be implemented than those supported by the drive IC.

도 1은 종래 기술에 따른 TFT-LCD의 화소를 나타낸 구성도이다.1 is a block diagram showing a pixel of a TFT-LCD according to the prior art.

도시된 바와 같이, 종래의 TFT-LCD는 다수개의 게이트 라인(2)과 다수개의 데이타 라인(3)이 일정한 간격을 갖고 수직으로 교차하며 형성되고, 상기 게이트 라인(2)과 데이타 라인(3)에 의해 매트릭스 형태를 갖는 다수개의 사각형의 빈공간에 1개의 화소(1)가 각각 형성된다(도 1에서는 1개의 화소만을 도시함).As shown, a conventional TFT-LCD is formed by vertically crossing a plurality of gate lines 2 and a plurality of data lines 3 at regular intervals, and the gate line 2 and the data line 3. By this, one pixel 1 is formed in each of a plurality of rectangular empty spaces having a matrix form (only one pixel is shown in FIG. 1).

그리고, 상기 게이트 라인(2) 위에 게이트 전극(5b)이 형성되고, 상기 데이타 라인(3) 위에 소오스 전극(5a)이 형성되며, 상기 화소(1) 위에 드레인 전극(5c)이 형성된 TFT 트랜지스터(5)를 구비한다. 또한, 상기 화소(1)와 데이타 라인(3) 아래에는 공통전극 라인(4)이 상기 게이트 라인(2)과 평행하게 형성되어 있다.In addition, a TFT transistor includes a gate electrode 5b formed on the gate line 2, a source electrode 5a formed on the data line 3, and a drain electrode 5c formed on the pixel 1. 5). In addition, a common electrode line 4 is formed parallel to the gate line 2 under the pixel 1 and the data line 3.

상기 TFT 트랜지스터(5)는 다수개의 게이트 라인 중에 자신의 게이트가 형성된 게이트 라인이 액티브될 때 턴-온되어 상기 데이타 라인(3)으로 전송된 데이타 신호를 화소(1)에 전달한다. 이때, 데이타 신호는 사용된 드라이브 IC의 종류에 따라 6비트의 경우 64개, 8비트의 경우 256개의 서로 다른 전압 레벨을 가질 수 있다.The TFT transistor 5 is turned on when the gate line of which its gate is formed among the plurality of gate lines is activated, and transfers the data signal transmitted to the data line 3 to the pixel 1. In this case, the data signals may have 64 different voltage levels depending on the type of drive IC used, and 256 different voltage levels for 8 bits.

게이트 라인(n)이 오프(off) 상태로 전환된 후에는 다음 라인의 게이트 라인(n+1)이 온(on) 상태로 되어 순차적으로 데이타 신호를 써넣도록 되어 있다.After the gate line n is turned off, the gate line n + 1 of the next line is turned on to write data signals sequentially.

도 2는 종래 기술에 따른 TFT-LCD의 구동 파형을 나타낸 것이다.2 shows a driving waveform of a TFT-LCD according to the prior art.

게이트 라인이 '하이' 상태일 때 TFT 트랜지스터가 턴-온되어 데이타 라인으로 전송된 데이타 신호를 화소로 전송하게 된다.When the gate line is 'high', the TFT transistor is turned on to transmit the data signal transmitted to the data line to the pixel.

그러나, 이와 같이 구성된 종래의 TFT-LCD의 구동회로에 있어서는, 색표현과 계조 구현을 위하여 한 화소가 R,G,B로 나뉘어져 있으며, 6비트 또는 8비트의 드라이브 IC를 사용하여, 6비트의 경우 64개(26)의 계조가 구현되며, 8비트의 경우 256개(28)의 계조가 표현된다. 세밀한 색구현을 위해서는 8비트 또는 그 이상의 데이타가 필요한데, 8비트 드라이브 IC는 6비트 드라이브 IC에 비해 가격이 비싸고, 8비트 이상의 드라이브 IC는 아직 개발되어 있지 않아 8비트 이상을 지원하는 영상을 표현할 수 없는 문제점이 있었다.However, in the driving circuit of the conventional TFT-LCD configured as described above, one pixel is divided into R, G, and B for color expression and gradation, and a six-bit or eight-bit drive IC is used to In the case of 64 (2 6 ) gray scales, 256 (2 8 ) gray scales are represented in the case of 8 bits. 8-bit or more data is required for detailed color realization. 8-bit drive ICs are more expensive than 6-bit drive ICs, and more than 8-bit drive ICs have not been developed yet. There was no problem.

따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 TFT-LCD의 한 화소를 2개의 서브 화소로 분할하고 각각의 서브 화소에 서로 다른 신호를 써넣음으로써, 드라이브 IC에서 지원하는 계조보다 한 단계 또는 그 이상의 계조 구현이 가능하도록 한 TFT-LCD의 화소 구동 회로를 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to support a drive IC by dividing one pixel of a TFT-LCD into two sub-pixels and writing a different signal to each sub-pixel. The present invention provides a pixel driving circuit of a TFT-LCD that enables one or more levels of gradation to be implemented.

도 1은 종래 기술에 따른 TFT-LCD의 화소 구동 회로를 나타낸 구성도1 is a block diagram illustrating a pixel driving circuit of a TFT-LCD according to the related art.

도 2는 종래 기술에 따른 TFT-LCD의 화소 구동 신호의 파형도2 is a waveform diagram of a pixel driving signal of a TFT-LCD according to the prior art;

도 3은 본 발명에 의한 TFT-LCD의 화소 구동 회로를 나타낸 구성도3 is a block diagram showing a pixel driving circuit of a TFT-LCD according to the present invention;

도 4는 본 발명에 의한 TFT-LCD의 화소 구동 신호의 파형도4 is a waveform diagram of a pixel drive signal of a TFT-LCD according to the present invention;

도 5는 본 발명에 의한 TFT-LCD의 화소 구동 회로의 등가 회로도5 is an equivalent circuit diagram of a pixel driving circuit of a TFT-LCD according to the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

10 : 제 1 서브 화소12 : 제 2 서브 화소10: first sub pixel 12: second sub pixel

20, 22 : 게이트 라인30 : 데이타 라인20, 22: gate line 30: data line

40 : 공통전극 라인50 : 제 1 TFT 트랜지스터40 common electrode line 50 first TFT transistor

52 : 제 2 TFT 트랜지스터54 : 제 3 TFT 트랜지스터52: second TFT transistor 54: third TFT transistor

상기 목적을 달성하기 위한 본 발명에 의한 TFT-LCD의 화소 구동 회로는,The pixel drive circuit of the TFT-LCD according to the present invention for achieving the above object,

다수개의 게이트 라인과 다수개의 데이타 라인에 의해 형성된 화소 영역에각각 형성된 2개의 제 1 및 제 2 서브 화소와,Two first and second sub-pixels each formed in a pixel region formed by a plurality of gate lines and a plurality of data lines,

상기 다수개의 게이트 라인 중 제 1 게이트 라인의 신호에 의해 상기 제 1 서브 화소로 상기 데이타 라인을 통해 전송된 데이타 신호를 전송하는 제 1 TFT 트랜지스터와,A first TFT transistor for transmitting a data signal transmitted through the data line to the first sub pixel by a signal of a first gate line among the plurality of gate lines;

상기 제 1 게이트 라인의 신호에 의해 상기 제 2 서브 화소로 상기 데이타 라인을 통해 전송된 데이타 신호를 전송하는 제 2 TFT 트랜지스터와,A second TFT transistor for transmitting a data signal transmitted through the data line to the second sub pixel by a signal of the first gate line;

상기 제 1 및 제 2 서브 화소로 제 2 게이트 라인의 신호에 의해 공통전극라인을 통해 전송된 공통전압을 공급하는 제 3 TFT 트랜지스터를 구비하며,A third TFT transistor configured to supply a common voltage transmitted through a common electrode line by a signal of a second gate line to the first and second sub pixels,

상기 게이트 라인의 신호는 제 1 및 제 2 구간을 갖는 계단형 펄스신호를 가지며, 상기 제 1 구간에서는 상기 제 1 TFT 트랜지스터만 턴-온되고, 상기 제 2 구간에서는 상기 제 1, 제 2 및 제 3 TFT 트랜지스터가 모두 턴-온되며, 상기 제 2 구간 이후에는 상기 제 3 TFT 트랜지스터만 턴-온되어, 상기 제 1 및 제 2 서브 화소에 서로 다른 계조의 전압값을 기입하여 그 중간값을 인식하도록 하는 것을 특징으로 한다.The gate line signal has a stepped pulse signal having first and second periods, only the first TFT transistor is turned on in the first period, and the first, second and second periods in the second period. All of the three TFT transistors are turned on, and after the second period, only the third TFT transistor is turned on to write voltage values of different gray levels in the first and second sub-pixels to recognize the intermediate values. It is characterized by that.

이하, 첨부된 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 5는 본 발명에 의한 TFT-LCD의 화소 구동 회로의 구성을 나타낸 평면도이다.Fig. 5 is a plan view showing the structure of a pixel driving circuit of a TFT-LCD according to the present invention.

상기 TFT-LCD는 도시된 바와 같이, 다수개의 게이트 라인(20)과 다수개의 데이타 라인(30)이 일정한 간격을 갖고 수직으로 교차하며 형성되고, 상기 게이트 라인(20)과 데이타 라인(30)에 의해 매트릭스 형태를 갖는 다수개의 사각형의 빈공간에 1개의 화소가 각각 형성된다(도 3에서는 1개의 화소만을 도시함). 이때, 1개의 화소에는 2개의 제 1 및 제 2 서브 화소(10)(12)를 구비한다.As illustrated, the TFT-LCD is formed by vertically crossing a plurality of gate lines 20 and a plurality of data lines 30 at regular intervals, and forming a plurality of gate lines 20 and data lines 30 on the gate lines 20 and data lines 30. As a result, one pixel is formed in each of a plurality of rectangular empty spaces having a matrix form (only one pixel is shown in FIG. 3). At this time, one pixel includes two first and second sub-pixels 10 and 12.

그리고, 상기 게이트 라인(20) 위에 게이트 전극(50b)이 형성되고, 상기 데이타 라인(30) 위에 소오스 전극(50a)이 형성되며, 상기 제 1 서브 화소(10) 위에 드레인 전극(50c)이 형성된 제 1 TFT 트랜지스터(50)와, 상기 게이트 라인(20) 위에 게이트 전극(52b)이 형성되고, 상기 데이타 라인(30) 위에 소오스 전극(52a)이 형성되며, 상기 제 2 서브 화소(12) 위에 드레인 전극(52c)이 형성된 제 2 TFT 트랜지스터(52)와, 상기 게이트 라인(20) 위에 게이트 전극(54b)이 형성되고 소오스 및 드레인 전극(54a)(54c)이 상기 제 1 및 제 2 서브 화소(10)(12)에 형성된 제 3 TFT 트랜지스터(54)를 구비한다.A gate electrode 50b is formed on the gate line 20, a source electrode 50a is formed on the data line 30, and a drain electrode 50c is formed on the first sub pixel 10. A gate electrode 52b is formed on the first TFT transistor 50 and the gate line 20, and a source electrode 52a is formed on the data line 30, and on the second sub pixel 12. A second TFT transistor 52 having a drain electrode 52c formed thereon, a gate electrode 54b formed on the gate line 20, and source and drain electrodes 54a and 54c formed in the first and second subpixels. A third TFT transistor 54 formed at (10) 12 is provided.

또한, 상기 제 1 서브 화소(10)와 데이타 라인(30) 아래에 공통전극 라인(40)이 상기 게이트 라인(20)과 평행하게 형성된다.In addition, a common electrode line 40 is formed parallel to the gate line 20 under the first sub pixel 10 and the data line 30.

상기 구성을 갖는 본 발명의 TFT-LCD의 화소 구동 회로의 동작을 도 4에 도시된 구동 파형을 참조하여 설명하기로 한다.The operation of the pixel driving circuit of the TFT-LCD of the present invention having the above configuration will be described with reference to the driving waveform shown in FIG.

상기 제 1 TFT 트랜지스터(50)는 종래의 일반적인 TFT-LCD의 화소에 설치된 TFT 트랜지스터와 동일하게 구동되어 사용된 디바이스 IC의 종류에 따라 6비트 또는 8비트의 서로 다른 전압으로 도 4에서 나타낸 T1의 시간 동안 충전되게 된다. 즉, 상기 제 1 TFT 트랜지스터(50)는 다수개의 게이트 라인 중에 자신의 게이트가 형성된 게이트 라인이 액티브될 때 턴-온되어 상기 데이타 라인(30)으로 전송된 데이타 신호를 제 1 서브 화소(10)에 전달한다. 이때, 데이타 신호는 사용된 드라이브 IC의 종류에 따라 6비트의 경우 64개, 8비트의 경우 256개의 서로 다른 전압 레벨을 가질 수 있다.The first TFT transistor 50 is driven in the same manner as a TFT transistor installed in a pixel of a conventional general TFT-LCD, and the voltage of T1 shown in FIG. It will be charged for hours. That is, the first TFT transistor 50 is turned on when the gate line having its gate formed among the plurality of gate lines is activated, and transmits the data signal transmitted to the data line 30 to the first sub pixel 10. To pass on. In this case, the data signals may have 64 different voltage levels depending on the type of drive IC used, and 256 different voltage levels for 8 bits.

그 다음, T2의 시간동안은 게이트 라인(22)과 게이트 라인(22)이 동시에 온(on) 전압이 되어 제 2 및 제 3 트랜지스터(52)(54)가 함께 턴-온(turn-on) 상태가 되어 제 2 서브 화소(12)에 신호를 인가하게 된다. 이 기간동안은 표현하고자 하는 계조에 따라 몇단계 높거나 낮은 단계의 계조전압을 인가하게 되어, 제 1 및 제 2 서브 화소(10)(12)에 서로 다른 전압레벨을 인가할 수 있다.Then, during the time T2, the gate line 22 and the gate line 22 are simultaneously turned on so that the second and third transistors 52 and 54 are turned on together. In this state, a signal is applied to the second sub-pixel 12. During this period, a gradation voltage of several steps is applied according to the gradation to be expressed, and different voltage levels may be applied to the first and second sub-pixels 10 and 12.

T2 시간 후에는 제 1 및 제 2 트랜지스터(50)(52)가 오프(off) 상태이고, 제 3 트랜지스터(54)가 온(on) 상태가 되며, 제 2 서브 화소(12)의 공통 전극(40)이 플로팅(floating) 상태가 되어 제 2 서브 화소(12)의 충전 상태는 변하지 않는다.After the time T2, the first and second transistors 50 and 52 are turned off, the third transistor 54 is turned on, and the common electrode of the second sub-pixel 12 ( 40 is in a floating state so that the charging state of the second sub-pixel 12 does not change.

이와 같은 구동방식을 이용하여 가령 드라이브 IC가 지원하는 계조 단계가 m, m+1, m+2,......일 때, 제 1 서브 화소에는 m, 제 2 서브 화소에는 m+1을 인가하여 사람이 인식하는 계조 간계는 m 단계와 m+1 단계 사이값이 되어 1비트 높은 계조의 색표현이 가능하다.By using such a driving method, for example, when the gradation level supported by the drive IC is m, m + 1, m + 2, ..., m is the first sub pixel and m is the second sub pixel. The gradation interval recognized by the human being by applying the value becomes a value between the m level and the m + 1 level, so that the color expression of the gradation that is one bit higher is possible.

따라서, 6비트 드라이브 IC를 사용한 경우 7비트의 계조 표현이 가능해 지며, 8비트 드라이브 IC를 사용한 경우 9비트의 계조표현이 가능하다.Therefore, 7-bit gradation can be expressed when 6-bit drive IC is used, and 9-bit gradation can be expressed when 8-bit drive IC is used.

도 5는 본 발명에 의한 TFT-LCD의 화소 구동 회로의 등가 회로도이다.5 is an equivalent circuit diagram of a pixel driving circuit of a TFT-LCD according to the present invention.

본 발명을 구현하기 위해, TFT-LCD 제조공정에서 추가되는 공정이 없어 비용상승이 없으며, 타이밍 컨트롤러에서 T2의 시간동안 다른 전압을 인가할 수 있도록설계 변경이 필요하다.In order to implement the present invention, there is no additional cost in the TFT-LCD manufacturing process, and there is no cost increase, and a design change is required so that a different voltage can be applied during the time of T2 in the timing controller.

이상에서 설명한 바와 같이, 본 발명에 의한 TFT-LCD의 화소 구동 회로에 의하면, TFT-LCD의 한 화소를 2개의 서브 화소로 분할하고 각각의 서브 화소에 서로 다른 신호를 써넣음으로써, 드라이브 IC에서 지원하는 계조보다 한 단계 또는 그 이상의 계조 구현이 가능하다.As described above, according to the pixel driving circuit of the TFT-LCD according to the present invention, in a drive IC by dividing one pixel of the TFT-LCD into two sub-pixels and writing a different signal to each sub-pixel. It is possible to implement one or more levels of gray levels than the ones supported.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (3)

박막트랜지스터 액정표시장치의 화소 구동 회로에 있어서,In a pixel driving circuit of a thin film transistor liquid crystal display device, 다수개의 게이트 라인과 다수개의 데이타 라인에 의해 형성된 화소 영역에 각각 형성된 2개의 제 1 및 제 2 서브 화소와,Two first and second sub-pixels each formed in a pixel region formed by a plurality of gate lines and a plurality of data lines; 상기 다수개의 게이트 라인 중 제 1 게이트 라인의 신호에 의해 상기 제 1 서브 화소로 상기 데이타 라인을 통해 전송된 데이타 신호를 전송하는 제 1 TFT 트랜지스터와,A first TFT transistor for transmitting a data signal transmitted through the data line to the first sub pixel by a signal of a first gate line among the plurality of gate lines; 상기 제 1 게이트 라인의 신호에 의해 상기 제 2 서브 화소로 상기 데이타 라인을 통해 전송된 데이타 신호를 전송하는 제 2 TFT 트랜지스터와,A second TFT transistor for transmitting a data signal transmitted through the data line to the second sub pixel by a signal of the first gate line; 상기 제 1 및 제 2 서브 화소로 제 2 게이트 라인의 신호에 의해 공통전극라인을 통해 전송된 공통전압을 공급하는 제 3 TFT 트랜지스터를 구비하며,A third TFT transistor configured to supply a common voltage transmitted through a common electrode line by a signal of a second gate line to the first and second sub pixels, 상기 게이트 라인의 신호는 제 1 및 제 2 구간을 갖는 계단형 펄스신호를 가지며, 상기 제 1 구간에서는 상기 제 1 TFT 트랜지스터만 턴-온되고, 상기 제 2 구간에서는 상기 제 1, 제 2 및 제 3 TFT 트랜지스터가 모두 턴-온되며, 상기 제 2 구간 이후에는 상기 제 3 TFT 트랜지스터만 턴-온되어, 상기 제 1 및 제 2 서브 화소에 서로 다른 계조의 전압값을 기입하여 그 중간값을 인식하도록 하는 것을 특징으로 하는 박막트랜지스터 액정표시장치의 화소 구동 회로.The gate line signal has a stepped pulse signal having first and second periods, only the first TFT transistor is turned on in the first period, and the first, second and second periods in the second period. All of the three TFT transistors are turned on, and after the second period, only the third TFT transistor is turned on to write voltage values of different gray levels in the first and second sub-pixels to recognize the intermediate values. A pixel driving circuit of a thin film transistor liquid crystal display device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 제 1 TFT 트랜지스터는,The first TFT transistor, 상기 제 1 게이트 라인 위에 게이트 전극이 형성되고, 상기 데이타 라인 위에 소오스 전극이 형성되며, 상기 제 1 서브 화소 위에 드레인 전극이 형성되며,A gate electrode is formed on the first gate line, a source electrode is formed on the data line, a drain electrode is formed on the first sub pixel, 상기 제 2 TFT 트랜지스터는,The second TFT transistor, 상기 제 1 게이트 라인 위에 게이트 전극이 형성되고, 상기 데이타 라인 위에 소오스 전극이 형성되며, 상기 제 2 서브 화소 위에 드레인 전극이 형성되며,A gate electrode is formed on the first gate line, a source electrode is formed on the data line, a drain electrode is formed on the second sub pixel, 상기 제 3 TFT 트랜지스터는,The third TFT transistor, 상기 제 2 게이트 라인 위에 게이트 전극이 형성되고 소오스 및 드레인 전극이 상기 제 1 및 제 2 서브 화소에 형성된 것을 특징으로 하는 박막트랜지스터 액정표시장치의 화소 구동 회로.And a source electrode and a drain electrode are formed on the first and second sub-pixels, wherein the gate electrode is formed on the second gate line. 제 1 항에 있어서,The method of claim 1, 상기 공통전극라인은 제 1 서브 화소와 상기 데이타 라인 아래에 상기 게이트 라인과 평행하게 형성된 것을 특징으로 하는 박막트랜지스터 액정표시장치의 화소 구동 회로.And the common electrode line is formed in parallel with the gate line under the first sub pixel and the data line.
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KR100717190B1 (en) * 2005-01-24 2007-05-11 비오이 하이디스 테크놀로지 주식회사 Liquid crystal display device and method for manufacturing thereof
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US8194199B2 (en) 2004-12-02 2012-06-05 Samsung Electronics Co., Ltd. Liquid crystal display device having a ratio of liquid crystal capacitances equal to a ratio of parasitic capacitances
US8570264B2 (en) 2005-02-11 2013-10-29 Samsung Display Co., Ltd. Liquid crystal display apparatus with wide viewing angle
US8810606B2 (en) 2004-11-12 2014-08-19 Samsung Display Co., Ltd. Display device and driving method thereof
US9311877B2 (en) 2009-11-17 2016-04-12 Samsung Display Co., Ltd. Liquid crystal display having high and low luminances alternatively represented
WO2017041427A1 (en) * 2015-09-08 2017-03-16 京东方科技集团股份有限公司 Sub-pixel unit, array substrate and display apparatus
US9885931B2 (en) 2015-09-08 2018-02-06 Boe Technology Group Co., Ltd. Sub-pixel unit, array substrate and display device

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JPH1068931A (en) * 1996-08-28 1998-03-10 Sharp Corp Active matrix type liquid crystal display device

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US8810606B2 (en) 2004-11-12 2014-08-19 Samsung Display Co., Ltd. Display device and driving method thereof
US9058787B2 (en) 2004-11-12 2015-06-16 Samsung Display Co., Ltd. Display device and driving method thereof
US9390669B2 (en) 2004-11-12 2016-07-12 Samsung Display Co., Ltd. Display device and driving method thereof
US8194199B2 (en) 2004-12-02 2012-06-05 Samsung Electronics Co., Ltd. Liquid crystal display device having a ratio of liquid crystal capacitances equal to a ratio of parasitic capacitances
US7973899B2 (en) 2004-12-03 2011-07-05 Samsung Electronics Co., Ltd. Thin film transistor array panel with capacitive coupling between adjacent pixel areas
KR100717190B1 (en) * 2005-01-24 2007-05-11 비오이 하이디스 테크놀로지 주식회사 Liquid crystal display device and method for manufacturing thereof
US8570264B2 (en) 2005-02-11 2013-10-29 Samsung Display Co., Ltd. Liquid crystal display apparatus with wide viewing angle
US9311877B2 (en) 2009-11-17 2016-04-12 Samsung Display Co., Ltd. Liquid crystal display having high and low luminances alternatively represented
US9514698B2 (en) 2009-11-17 2016-12-06 Samsung Display Co., Ltd. Liquid crystal display having high and low luminances alternatively represented
WO2017041427A1 (en) * 2015-09-08 2017-03-16 京东方科技集团股份有限公司 Sub-pixel unit, array substrate and display apparatus
US9885931B2 (en) 2015-09-08 2018-02-06 Boe Technology Group Co., Ltd. Sub-pixel unit, array substrate and display device

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