KR20030059950A - Method for manufacturing split gate flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a split gate flash memory device is provided to be capable of uniformly conserving the line width of a select gate electrode by using an oxide pattern having a uniform thickness. CONSTITUTION: A floating gate electrode(104a), a pair of spacers(108), a source region(110), and a source line(112) are sequentially formed on a semiconductor substrate(100). After sequentially forming a gate oxide layer(114), a select gate conductive layer(116), an anti-reflective coating, and a silicon nitride layer on the resultant structure, a CMP(Chemical Mechanical Polishing) process is carried out on the resultant structure for exposing the surface of the source line. Then, residual anti-reflective coating is selectively removed. An oxide pattern(132) is selectively formed on the resultant structure by carrying out a thermal oxidation process at the resultant structure. Then, a select gate electrode is completed by etching the select gate conductive layer using the oxide pattern as an etching mask.

Description

Method for manufacturing split gate flash memory device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a split gate flash memory device.

In general, a flash memory device is a device manufactured utilizing the advantages of EPROM having a program and erase characteristics and EEPROM having a program and erase characteristics. The flash memory device realizes a bit storage state as one transistor, and is a memory device that can be electrically programmed and erased.

The most common form of such a flash memory device is a structure having a double polysilicon gate electrode called a split gate. 1A to 1H, a conventional method of manufacturing a split gate flash memory device will be described. In this drawing, only the memory cell region of the flash memory device is shown.

First, referring to FIG. 1A, the first gate oxide film 12 and the floating gate conductive layer 14 are sequentially deposited on the semiconductor substrate 10. Thereafter, a silicon nitride film is formed over the floating gate conductive layer 14, and then the silicon nitride film is patterned to expose the source predetermined region of the flash memory device, thereby forming the silicon nitride film pattern 16. The silicon oxide film for the spacer is deposited on the resultant of the semiconductor substrate 10, and then anisotropic blanket etching is performed to form the first spacer 18 on both sidewalls of the silicon nitride film pattern 16. Using the first spacer 18 as a mask, the exposed floating gate conductive layer 14 and the first gate oxide film 12 are etched to expose the source predetermined region. Next, the source region 20 is formed by implanting impurities of a type opposite to the substrate into the exposed semiconductor substrate 10 region, that is, the source predetermined region. A polysilicon film is deposited on the resultant semiconductor substrate 10 so that the space above the source region 20 is sufficiently filled, and then etched back to form a source line 22 in contact with the source region 20.

Referring to FIG. 1B, the silicon nitride film pattern 16 is removed with a phosphoric acid solution. Next, the floating gate conductive layer 14 and the first gate oxide film 12 are etched using the spacer 18 as a mask to form the floating gate electrode 14a.

Next, as shown in FIG. 1C, the second gate oxide layer 23 and the select layer conductive layer 24 are sequentially deposited on the resultant of the semiconductor substrate 10. Subsequently, the antireflection film 26 and the hard mask oxide film 28 are laminated on the select gate conductive layer 24. Here, the anti-reflection film 26 and the hard mask oxide film 28 are for forming the gate electrode of the logic circuit formed in the peripheral region of the flash memory device.

As shown in FIG. 1D, the first silicon nitride film 30 is deposited on the hard mask oxide film 28, and the adhesion oxide film 32 is deposited on the first silicon nitride film 30. At this time, the adhesion oxide film 32 is a film for improving the adhesion characteristics of the photoresist pattern (not shown) and the first silicon nitride film 30 during the patterning process using the photoresist.

Next, as shown in FIG. 1E, a photoresist pattern (not shown) is formed on the adhesion oxide film 32 so that the cell region is exposed. At this time, the adhesion of the first silicon nitride film 30 to the photoresist pattern is facilitated by the adhesion oxide film 32. Thereafter, the adhesion oxide film 32 of the exposed cell region is removed by a wet etching method.

As shown in FIG. 1F, the photoresist pattern (not shown) is removed in a known manner. Next, the exposed first silicon nitride film 30 in the cell region is removed in a known manner. At this time, since the adhesion oxide film 32 is not removed on the first silicon nitride film 30 in the peripheral region where the logic circuit is formed, the first silicon nitride film 30 in the peripheral region by the adhesion oxide film 32. Will remain. Then, the hard mask oxide film 28 and the anti-reflection film 26 in the cell region are removed in a known manner. At this time, similarly, the hard mask oxide film 28 and the reflective film 26 remain on the peripheral region without being etched.

Thereafter, as shown in FIG. 1F, a second silicon nitride film 34 is deposited on the entire surface of the semiconductor substrate 10. At this time, by the deposition of the second silicon nitride film 34, the step difference between the cell region and the peripheral region becomes almost similar.

Next, as shown in FIG. 1G, chemical mechanical polishing is performed to expose the source line 22 surface. Accordingly, the select gate conductive layer 29 is disposed on both sides of the spacer. Thereafter, the resultant polished semiconductor substrate 10 is thermally oxidized to form a thermal oxide film 36 on the conductive layer 29 and the source line 20 for the select gate.

Thereafter, as shown in FIG. 1H, the remaining second silicon nitride film 34 is removed in a known manner. Next, using the thermal oxide film 36 as a mask, the select gate conductive layer 29 and the second gate oxide film 23 are patterned to form the select gate electrode 24a. At this time, during the etching process for forming the select gate electrode 24a, the thermal oxide film 36 is simultaneously removed.

Thereafter, second spacers 38 are formed on both side walls of the select gate electrode 24a. Then, the impurity is injected into both sides of the second spacer 38 to form the drain region 40, thereby completing the split gate flash memory device.

However, the conventional split gate flash memory device is as follows.

As described above, the select gate electrode 24a of the split gate flash memory element is defined by the thermal oxide film 36 formed on the polished surface. However, since the thermal oxide film 36 is not formed to have a uniform thickness, when the select gate electrode 24a is etched using the thermal oxide film 36, as shown in FIG. 2, the select gate electrode ( The line width of 24a) is not constant.

In this way, if the line width of the select gate electrode 24a is not constant, the channel length of the flash memory device is variable, and device characteristics cannot be secured.

Accordingly, an object of the present invention is to provide a method of manufacturing a split gate flash memory device capable of keeping the line width of the select gate electrode constant.

1A to 1H are cross-sectional views of respective processes for explaining a method of manufacturing a conventional split gate flash memory device.

2 is a plan view of a split gate formed by the prior art.

3A to 3K are cross-sectional views of respective processes for explaining a method of manufacturing a split gate flash memory device according to an exemplary embodiment of the present invention.

4 is a plan view of a split gate electrode according to the present invention.

(Explanation of symbols for the main parts of the drawing)

100-semiconductor substrate 104a-floating gate electrode

108-first spacer 110-source region

112- source line 116a- select gate electrode

126-Second antireflection film 128-Second nitride film

132-oxide pattern 136-drain region

Other objects and novel features thereof, together with the objects of the present invention, will be apparent from the description and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative features is briefly described as follows.

A method of manufacturing a split gate flash memory device according to an embodiment of the present invention includes a pair of floating gate electrodes on a semiconductor substrate including a cell region where a memory cell is to be formed and a peripheral region where a logic circuit is to be formed. Form a spacer. Next, a source region is formed in the semiconductor substrate between the spacers, and a source line is formed in contact with the source region in the space between the spacers. Thereafter, a gate oxide film is formed over the semiconductor substrate including the spacer and the source line, and a conductive layer for a select gate is formed over the gate oxide film. An anti-reflection film is formed on the conductive layer for the select gate, and a silicon nitride film is deposited on the conductive layer for the select gate. Thereafter, the silicon nitride film, the antireflection film, and the conductive layer for the select gate are chemically mechanically polished so as to expose the surface of the source line, and the antireflective layers on both sidewalls of the select gate conductive layer are selectively removed. Subsequently, the resultant semiconductor substrate is thermally oxidized to form an oxide pattern on the sidewalls, the top surface, and the source line surface of the conductive layer for the select gate, and the conductive layer for the select gate is etched using the oxide pattern as a mask. The select gate electrode is formed.

Here, the step of forming the spacer is as follows. First, a floating gate oxide film is formed on the semiconductor substrate, and then a conductive layer for floating electrodes is formed on the floating gate oxide film. Subsequently, a silicon nitride film is formed on the conductive layer for the floating electrode, and the silicon nitride film is etched to expose a source predetermined region. Then, spacers are formed on both sidewalls of the silicon nitride film, the silicon nitride film is removed, and the floating gate conductive layer and the floating gate oxide film are patterned using the spacer as a mask to include a floating gate electrode. Form a spacer.

In this case, the conductive layer for the floating gate is a doped polysilicon film.

In addition, the source line is formed by forming a doped polysilicon film to sufficiently fill the space between the spacers, and by etching back the doped polysilicon film to expose the surface of the spacer.

In addition, the following steps can be performed between the step of forming the conductive layer for the select gate and the step of forming the anti-reflection film. That is, first, an antireflection film is formed on the conductive layer for the select gate, a hard mask oxide film is formed on the antireflection film, and a silicon nitride film is formed on the hard mask oxide film. Subsequently, an adhesion oxide film is formed on the silicon nitride film, a photoresist pattern is formed to expose the cell region, and then the adhesion oxide film of the exposed cell region is patterned using the photoresist pattern as a mask. Subsequently, the photoresist pattern is removed, and the exposed silicon nitride film of the cell region is etched using the adhesive oxide film remaining in the peripheral region as a mask. Then, the hard mask oxide film and the prevention film of the exposed cell region are removed.

In this case, the select gate conductive layer may be formed of a doped polysilicon film, and the anti-reflection film may be formed of a SiON film.

In addition, the anti-reflection film on the sidewall of the conductive layer for the select gate may be selectively removed by etching the resultant of the semiconductor substrate with a silicon oxide etching solution.

After forming the select gate electrode, a spacer may be formed on both sidewalls of the select gate electrode, and a drain region may be formed on the semiconductor substrate on both sides of the spacer of the select gate electrode.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

3A to 3K are cross-sectional views of respective processes for explaining a method of manufacturing a split gate flash memory device according to an exemplary embodiment of the present invention, and FIG. 4 is a plan view of the split gate electrode according to the present invention.

First, referring to FIG. 3A, the first gate oxide layer 102 and the floating gate conductive layer 104 are sequentially deposited on the semiconductor substrate 100. Here, the first gate oxide layer 102 may be a thermal oxide layer, and the conductive layer 104 for the floating gate may be a doped polysilicon layer. Thereafter, a silicon nitride film is formed on the floating gate conductive layer 104 as a lift-off mask. Next, the silicon nitride film is patterned so that the source predetermined region of the flash memory device is exposed to form the silicon nitride film pattern 106. An insulating layer for a spacer, for example, a silicon oxide layer is deposited on the resultant of the semiconductor substrate 100, and then anisotropic blanket is etched to form first spacers 108 on both sidewalls of the silicon nitride layer pattern 106. In this case, the first spacer 108 provides insulation between the select gate electrode and the floating gate electrode to be formed later. Thereafter, the exposed floating conductive layer 104 and the first gate oxide film 102 are etched using the first spacer 108 as a mask to expose the source predetermined region.

Next, the source region 110 is formed by implanting impurities of a type opposite to that of the substrate into the exposed region of the semiconductor substrate 100. Subsequently, a polysilicon film is deposited on the semiconductor substrate 100 so that the space above the source region 110 is sufficiently filled, and then etched back to form a source line 112 in contact with the source region 110. .

Thereafter, referring to FIG. 3B, the silicon nitride film pattern 106 is removed by a known method, for example, a phosphoric acid (PH ₃ ) solution. Next, the floating gate conductive layer 104 and the first gate oxide film 102 are etched using the first spacer 108 as a mask to form the floating gate electrode 104a. Here, the outer portion of the floating gate electrode 104a exposed to the outside is partially oxidized.

As illustrated in FIG. 3C, the second gate oxide layer 114 and the conductive layer 116 for the select gate are sequentially deposited on the semiconductor substrate 100 on which the floating gate electrode 104a is formed. Here, the second gate oxide layer 114 may be a thermal oxide layer, and the conductive layer 24 for the select gate may be a doped polysilicon layer. The first anti-reflection film 118 and the hard mask oxide film 120 are deposited on the select gate conductive layer 24. Here, the first anti-reflection film 118 and the hard mask oxide film 120 are formed to form a logic circuit region formed in the peripheral region of the flash memory device. In this case, the first anti-reflection film 118 may be a silicon nitride oxide film (SiON) or a silicon nitride film (SiN) film.

As shown in FIG. 3D, the first silicon nitride film 122 is deposited on the hard mask oxide film 120, and the adhesion oxide film 124 is deposited on the first silicon nitride film 30. At this time, the adhesion oxide film 124 is a film for improving the adhesion characteristics of the photoresist pattern (not shown) and the first silicon nitride film 122 during the patterning process using a photoresist.

Next, as shown in FIG. 3E, a photoresist pattern (not shown) is formed on the adhesion oxide film 122 so that the cell region is exposed. At this time, the adhesion between the first silicon nitride film 122 and the photoresist pattern is facilitated by the adhesion oxide film 122. Thereafter, the adhesion oxide film 122 of the exposed cell region is removed by a wet etching method.

Then, as shown in FIG. 3F, the photoresist pattern (not shown) is removed in a known manner. Next, using the adhesion oxide film 124 remaining in the peripheral region as a mask, the exposed first silicon nitride film 122 in the cell region is removed in a known manner. Then, the hard mask oxide film 120 and the first antireflection film 118 in the cell region are removed. At this time, since the etching mask ratio of the hard mask oxide film 120 and the first anti-reflection film 118 are similar, they can be removed at the same time, and the adhesive oxide film 124 of the peripheral region formed of a material similar to that of the hard mask oxide film is also removed at the same time. do. As a result, the conductive layer 116 for the select gate is exposed. Thereafter, a second anti-reflection film 126 is deposited on the conductive layer 116 for the select gate. In this case, the second antireflection film 126 is formed of a film having a similar selectivity to the silicon oxide film and the silicon nitride film, for example, silicon nitride oxide (SiON) while preventing diffuse reflection. Next, a second silicon nitride film 128 is deposited to a sufficient thickness on the second anti-reflection film 126. In this case, the second silicon nitride film 128 is a film provided to alleviate the step difference between the cell region and the peripheral region before the subsequent CMP process.

Thereafter, as illustrated in FIG. 3G, the second silicon nitride film 128, the second antireflection film 126, and the conductive layer 116 for the select gate are chemically mechanically polished so that the surface of the source line 112 is exposed.

Next, referring to FIG. 3H, when the resultant of the semiconductor substrate 100 is etched by the silicon oxide film etchant, only the second anti-reflection film 126 on the sidewall of the conductive layer 116 for the select gate is selectively removed. Here, reference numeral 130 denotes a space from which the second anti-reflection film 126 is removed.

As illustrated in FIG. 3I, the resultant of the semiconductor substrate 100 is oxidized to form an oxide film pattern 132. Here, the oxide film pattern 132 is formed on the resultant surface of the polysilicon film, that is, the surface of the conductive layer 116 for the select gate, both side walls, and the surface of the source line 112.

Then, as in FIG. 3J, the remaining second silicon nitride film 128 is wet etched away in a known manner. At this time, the remaining second anti-reflection film 126 having similar etching selectivity to that of silicon nitride is also removed. Thereafter, using the oxide film pattern 132 as a mask, the lower select gate conductive layer 116 and the second gate oxide film 114 are patterned to form the select gate electrode 116a. In this case, since the oxide film pattern 132 extends to the sidewall of the select gate conductive layer 116, the select gate electrode 116a may be formed with a uniform line width. Here, in the etching process for forming the select gate electrode 116a, the oxide layer pattern 132 is simultaneously removed.

Next, as shown in FIG. 3K, the second spacer 134 is formed on both sidewalls of the select gate electrode 116a in a known manner. Thereafter, impurities of a type opposite to the substrate are implanted into the outer wall of the second spacer 134 to form the drain region 136. Thus, the split gate flash memory device is completed.

According to the present embodiment, by forming the oxide film pattern so as to extend to the sidewall of the conductive layer for the select gate, and patterning the conductive layer for the select gate using the pattern, the select gate electrode having a uniform line width as shown in FIG. Can be obtained.

As described above in detail, according to the present invention, the second anti-reflection film is formed before forming the second silicon nitride film for reducing the step difference between the cell region and the peripheral region before the CMP process. Thereafter, the second anti-reflection film on the sidewall of the select gate conductive layer is selectively removed, and then an oxide film pattern is formed on the sidewall and the top surface of the select gate conductive layer and the source line. Thereafter, the select gate electrode is formed using this oxide film pattern. At this time, an oxide film pattern having a uniform thickness is formed on the sidewalls of the select layer conductive layer, so that the select gate electrode having a constant line width can be formed. Accordingly, the channel length of the flash memory device is made constant, thereby improving device characteristics.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (10)

Providing a semiconductor substrate comprising a cell region in which a memory cell is to be formed and a peripheral region in which a logic circuit is to be formed; Forming a pair of spacers formed on the cell region of the semiconductor substrate and including a floating gate electrode therein; Forming a source region in the semiconductor substrate between the spacers; Forming a source line in contact with the source region in a space between the spacers; Forming a gate oxide layer on the semiconductor substrate including the spacer and the source line; Forming a conductive layer for a select gate on the gate oxide layer; Forming an anti-reflection film on the conductive layer for the select gate; Depositing a silicon nitride film on the conductive layer for the select gate; Chemical mechanical polishing the silicon nitride film, the antireflection film, and the conductive layer for the select gate to expose the surface of the source line; Selectively removing the anti-reflection film on both sidewalls of the conductive layer for the select gate; Thermally oxidizing the resultant of the semiconductor substrate to form an oxide layer pattern on the sidewalls, the top surface, and the source line surface of the conductive layer for the select gate; And And forming a select gate electrode by etching the conductive layer for the select gate using the oxide layer pattern as a mask. The method of claim 1, Forming the spacers, Forming a floating gate oxide layer on the semiconductor substrate; Forming a conductive layer for a floating electrode on the floating gate oxide layer; Forming a silicon nitride film on the conductive layer for the floating electrode; Etching the silicon nitride layer to expose a source predetermined region; Forming spacers on both sidewalls of the silicon nitride film; Removing the silicon nitride film; And And forming a spacer including a floating gate electrode by patterning the conductive layer for floating gate and the floating gate oxide film using the spacer as a mask. The method of claim 2, And the conductive layer for floating gate is a doped polysilicon layer. The method of claim 1, Forming the source line, Forming a doped polysilicon film such that the space between the spacers is sufficiently filled; And And etching back the doped polysilicon layer to expose the spacer surface. The method of claim 1, Between forming the conductive layer for the select gate and forming the anti-reflection film, Forming an anti-reflection film on the conductive layer for the select gate; Forming an oxide film for a hard mask on the anti-reflection film; Forming a silicon nitride film on the oxide film for hard mask; Forming an adhesion oxide film on the silicon nitride film; Forming a photoresist pattern to expose the cell region; Patterning the adhesion oxide film of the exposed cell region using the photoresist pattern as a mask; Removing the photoresist pattern; Etching the exposed silicon nitride film of the cell region using the adhesive oxide film remaining in the peripheral region as a mask; And removing the hard mask oxide layer and the barrier layer of the exposed cell region. The method of claim 1, And the conductive layer for the select gate is a doped polysilicon film. The method of claim 1, The anti-reflection film is a method of manufacturing a split gate flash memory device, characterized in that the etch selectivity is similar to that of the silicon oxide film and the silicon nitride film while preventing diffuse reflection. The method of claim 7, wherein The anti-reflection film is a silicon nitride oxide (SiON) manufacturing method of a split gate flash memory device. The method according to claim 1 or 7, Selectively removing the anti-reflection film, And etching the resultant of the semiconductor substrate with a silicon oxide etch solution. The method of claim 1, After forming the select gate electrode, Forming spacers on both sidewalls of the select gate electrode; And And forming a drain region in the semiconductor substrate on both sides of the spacer of the select gate electrode.