KR20030059456A - Method for forming metal line in semiconductor device - Google Patents
Method for forming metal line in semiconductor device Download PDFInfo
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- KR20030059456A KR20030059456A KR1020010088318A KR20010088318A KR20030059456A KR 20030059456 A KR20030059456 A KR 20030059456A KR 1020010088318 A KR1020010088318 A KR 1020010088318A KR 20010088318 A KR20010088318 A KR 20010088318A KR 20030059456 A KR20030059456 A KR 20030059456A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는 구리금속에 티타늄 이온을 주입하여 우수한 특성을 갖는 구리금속배선을 형성하는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly to a method for forming a metal wiring of a semiconductor device to form a copper metal wiring having excellent characteristics by injecting titanium ions into the copper metal.
종래 기술에 따른 반도체 소자의 금속배선 형성방법에 있어서는, 텅스텐과알루미늄 합금을 금속배선으로 사용하는 것이 일반적이다.In the metal wiring formation method of the semiconductor element of the prior art, it is common to use tungsten and an aluminum alloy as metal wiring.
그러나, 최근 반도체 소자의 고집적화 경향에 따라 선폭의 미세화에 의해서 소자의 동작 때문에 금속배선내의 전류밀도가 높아지고, 이에 따라 일렉트로 마이그레이션(electro migration) 현상이 두드러졌다.However, in recent years, with the tendency of high integration of semiconductor devices, the current density in the metal wiring is increased due to the operation of the devices due to the miniaturization of the line width, and thus, the electro migration phenomenon has been remarkable.
또한, 금속배선과 이를 보호하기 위한 절연막의 열팽창계수가 달라서 금속배선에 인장력이 가해져서 생기는 크리프(creep) 파괴인 스트레스 마이그레이션(stress migration) 현상이 배선의 미세화로 인해 더욱 두드려졌다.In addition, stress migration, a creep failure caused by the application of a tensile force to the metal wiring due to different thermal expansion coefficients of the metal wiring and the insulating film for protecting the same, has been further exacerbated by the miniaturization of the wiring.
이에 따라, 기존의 금속배선으로 사용되는 텅스텐과 알루미늄 합금은 큰 비저항과 일렉트로 마이그레이션(electro migration)이나 스트레스 마이그레이션(stress migration)으로 인해 신뢰성이 저하되었다. 따라서, 텅스텐과 알루미늄 합금을 대신하여 비저항이 작고 신뢰성이 우수한 구리가 금속배선 재료로 등장하게 되었다.As a result, the tungsten and aluminum alloys used in the existing metal wirings are degraded due to large resistivity, electro migration, or stress migration. Therefore, copper having a low specific resistance and excellent reliability has emerged as a metal wiring material in place of tungsten and aluminum alloys.
특히, 구리합금은 순수한 구리에 비해 비저항이 상대적으로 다소 크지만 배선의 신뢰성과 내식성이 우수하여 반도체 소자의 금속배선으로 이용된다.In particular, although copper alloy has a relatively large specific resistance compared to pure copper, it is used as a metal wiring of a semiconductor device because of excellent wiring reliability and corrosion resistance.
그러나, 종래 기술에 따른 반도체 소자의 금속배선 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the metal wiring formation method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서, 구리합금 박막은 원하는 조성의 구리합금 타겟(target) 제조후 스퍼터링(sputtering) 방식으로 형성된다. 그러나, 스퍼터링 방식은 비아홀(via hole) 크기가 감소하고 에스펙트비(aspect ratio)가 큰 비아홀에서는스텝 커버리지(step coverage)가 불량하여 충분한 매립을 할 수 없다.In the prior art, a copper alloy thin film is formed by sputtering after fabrication of a copper alloy target of a desired composition. However, in the sputtering method, the via hole size is reduced and the via hole having a large aspect ratio is poor in step coverage, and thus sufficient filling is not possible.
이와 같이, 충분한 매립을 할 수 없으므로 비아저항 증가, 구리 플러그의 단락, 반도체 소자의 동작속도 저하, 신뢰성 열화, 수율 감소 등의 여러 문제점이 발생한다.As such, since sufficient filling is not possible, various problems, such as increase in via resistance, short circuit of a copper plug, lowering of operating speed of a semiconductor device, deterioration of reliability, and decrease in yield, occur.
이에, 본 발명은 상기 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 구리배선에 티타늄 이온을 주입하여 비저항을 증가시키지 않으면서 금속배선의 신뢰성 및 내식성을 향상시키는 반도체 소자의 금속배선 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to inject the titanium ions into the copper wiring to improve the reliability and corrosion resistance of the metal wiring without increasing the specific resistance of the metal of the semiconductor device The present invention provides a wiring forming method.
도 1 내지 도 6은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도.1 to 6 are cross-sectional views for each process for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10: 반도체 기판20: 하부 금속배선10: semiconductor substrate 20: lower metal wiring
30: 캡핑막40: 절연막30: capping film 40: insulating film
50: 비아홀60: 트렌치50: via hole 60: trench
70: 배리어막80: 구리층70: barrier film 80: copper layer
80a: 구리배선90: 확산방지막80a: copper wiring 90: diffusion barrier
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성방법은, 반도체 기판상에 하부금속배선과 절연막을 형성하는 단계; 상기 절연막을 선택적으로 제거하여 비아홀과 트렌치를 형성하는 단계; 상기 비아홀과 트렌치를 포함한 상기 절연막상에 배리어막과 구리층을 형성하는 단계; 상기 구리층에 티타늄 원자를 이온 주입하고 열처리하는 단계; 상기 구리층을 선택적으로 제거하여 상기 트렌치와 비아홀을 매립하는 구리합금배선을 형성하는 단계; 및 상기 구리합금배선을 포함한 상기 절연막상에 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 한다.Method of forming a metal wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a lower metal wiring and an insulating film on a semiconductor substrate; Selectively removing the insulating layer to form via holes and trenches; Forming a barrier layer and a copper layer on the insulating layer including the via hole and the trench; Ion implanting and heat treating titanium atoms into the copper layer; Selectively removing the copper layer to form a copper alloy wire filling the trench and the via hole; And forming a diffusion barrier on the insulating film including the copper alloy wirings.
이하, 본 발명에 따른 반도체 소자의 금속배선 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도이다.1 to 6 are cross-sectional views for each process for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 금속배선 형성방법은, 도 1에 도시된 바와 같이, 반도체 기판(10)상에 하부금속배선(20)을 형성한 다음, 상기 하부금속배선(20)을 포함한 상기 반도체 기판(10) 전면에 캡핑막(30)을 증착한다. 그다음, 상기 캡핑막(30) 전면상에 절연막(40)을 형성하는데, 상기 절연막(40)은 상층 및 하층간의 캐패시턴스(capacitance)를 줄이기 위해 실리콘 산화막 또는 저유전율 절연막으로 형성한다. 이때, 상기 하부금속배선(20)은 알루미늄이나 구리를 사용하여 형성한다.In the method for forming metal wirings of a semiconductor device according to the present invention, as shown in FIG. 1, after forming the lower metal wirings 20 on the semiconductor substrate 10, the semiconductor including the lower metal wirings 20 is formed. The capping film 30 is deposited on the entire surface of the substrate 10. Next, an insulating film 40 is formed on the entire surface of the capping film 30, and the insulating film 40 is formed of a silicon oxide film or a low dielectric constant insulating film in order to reduce capacitance between upper and lower layers. In this case, the lower metal wiring 20 is formed using aluminum or copper.
그다음, 도 2에 도시된 바와 같이, 듀얼 다마신(dual damascene) 방식으로 상기 절연막(40)을 상기 하부금속배선(20) 표면 일부가 노출되도록 선택적으로 제거하여 비아홀(50)과 트렌치(60)를 형성한다.Next, as shown in FIG. 2, the insulating film 40 is selectively removed to expose a portion of the surface of the lower metal wiring 20 by a dual damascene method, so that the via hole 50 and the trench 60 are exposed. To form.
이어서, 도 3에 도시된 바와 같이, 상기 노출된 하부금속배선(20) 표면을 세정한다. 상기 세정 방식은 상기 하부금속배선(20)의 재질에 따라 달라지는바, 상기 하부금속배선(20)을 알루미늄으로 형성하였으면 고주파 스퍼터링(RF sputtering) 방식을 이용하고, 상기 하부금속배선(20)을 구리로 형성하였으면 수소환원 세정 방식을 사용한다.Subsequently, as shown in FIG. 3, the exposed lower metal interconnection 20 surface is cleaned. The cleaning method is different depending on the material of the lower metal wiring 20. If the lower metal wiring 20 is formed of aluminum, a high frequency sputtering method is used, and the lower metal wiring 20 is copper. When formed with a hydrogen reduction cleaning method is used.
상기 세정공정을 완료한 후, 상기 하부금속배선(20) 표면과 상기 비아홀(50) 내표면 및 트렌치(60) 내표면을 포함한 상기 절연막(40) 전면상에 배리어막(70)을 형성한다. 이때, 상기 배리어막(70) 형성은 스퍼터링 방식을 사용하는데, 일반적인 스퍼터링 방식보다는 IMP(ionized metal plasma) 스퍼터링 방식을 사용하는 것이스텝 커버리지를 향상시키는데 유리하다.After the cleaning process is completed, a barrier layer 70 is formed on the entire surface of the insulating film 40 including the lower metal wiring 20 surface, the inner surface of the via hole 50 and the inner surface of the trench 60. In this case, the barrier layer 70 is formed using a sputtering method, and it is advantageous to use an ionized metal plasma (IMP) sputtering method rather than a general sputtering method to improve step coverage.
그런다음, 상기 배리어막(7)이 형성된 비아홀(50) 및 트렌치(60)를 매립하기에 충분한 두께를 가지도록 구리층(8)을 형성한다. 상기 구리층(80)은 화학기상증착법(CVD) 또는 전해도금 방식으로 약 2.000Å 내지 3,000Å 정도 두께로 증착한다.Then, the copper layer 8 is formed to have a thickness sufficient to fill the via hole 50 and the trench 60 in which the barrier film 7 is formed. The copper layer 80 is deposited to a thickness of about 2.000 kPa to 3,000 kPa by chemical vapor deposition (CVD) or electroplating.
이어서, 도 4에 도시된 바와 같이, 상기 구리층(80) 상면에 고에너지 이온 주입 방식으로 티타늄 원자를 이온 주입한다. 이때, 상기 구리층(80) 내부로 주입된 티타늄 원자는 그 함유량이 약 1.5% 내지 2% 정도로 하는 것이 구리의 비저항을 크게 증가시키지 않으면서 구리배선의 신뢰성과 내식성을 크게 증가시킬 수 있으므로 바람직하다.Subsequently, as shown in FIG. 4, titanium atoms are ion implanted into the upper surface of the copper layer 80 by a high energy ion implantation method. At this time, the titanium atom injected into the copper layer 80 is preferably about 1.5% to 2% because it can greatly increase the reliability and corrosion resistance of the copper wiring without significantly increasing the specific resistance of copper. .
상기 이온주입 공정후 상기 기판(10)을 오븐(oven)이나 노(furnace)에서 약 350℃ 내지 500℃ 정도의 온도에서 열처리를 진행한다. 상기 열처리로 인하여 상기 구리층(80) 내로 주입된 티타늄 원자는 더욱 균일하게 분포되고, 또한 구리결정립 크기가 켜져서 셀프 어닐(self anneal)에 의한 CMP 공정시 구리의 제거 속도 증가를 방지할 수 있다.After the ion implantation process, the substrate 10 is heat-treated at an temperature of about 350 ° C. to 500 ° C. in an oven or a furnace. The titanium atoms injected into the copper layer 80 due to the heat treatment are more uniformly distributed, and the size of the copper grains is turned on, thereby preventing an increase in the removal rate of copper during the CMP process by self anneal. .
그다음, 도 5에 도시된 바와 같이, 화학적 기계적 연마공정으로 상기 절연막(40) 표면이 노출되도록 상기 구리층(80)을 제거한다. 그결과, 상기 트렌치(60) 및 비아홀(50) 내에 구리합금배선(80a)이 형성된다.Next, as shown in FIG. 5, the copper layer 80 is removed to expose the surface of the insulating film 40 by a chemical mechanical polishing process. As a result, a copper alloy wiring 80a is formed in the trench 60 and the via hole 50.
이어서, 도 6에 도시된 바와 같이, 확산계수가 큰 구리가 외부로 확산하는 것을 방지하기 위하여 상기 구리합금배선(80a)을 포함한 상기 절연막(40) 전면상에실리콘나이트라이드(SiN) 등으로 확산방지막(90)을 형성한다.Next, as shown in FIG. 6, in order to prevent diffusion of copper having a large diffusion coefficient to the outside, silicon nitride (SiN) or the like is diffused on the entire surface of the insulating film 40 including the copper alloy wiring 80a. The prevention film 90 is formed.
상기 공정을 반복하여 진행하면 다층의 금속배선을 형성할 수 있다.By repeating the above process, a multilayer metal wiring can be formed.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 금속배선 형성방법은 다음과 같은 효과가 있다As described above, the metallization method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 비아매립이 우수한 CVD 방식이나 전해도금법을 사용하여 비아홀 내부에 키 홀(key hole)이나 보이드(void) 없는 구리합금배선을 얻을 수 있어 우수한 일렉트로 마이그레이션(electro migration)이나 스트레스 마이그레이션(stress migration) 특성을 가지게 되어, 결과적으로 소자의 신뢰성을 향상시킬 수 있다.In the present invention, a copper alloy wiring without key holes or voids can be obtained inside the via hole by using a CVD method or an electroplating method with excellent via filling, and thus excellent electro migration or stress migration ( stress migration) characteristics, resulting in improved device reliability.
또한, 티타늄을 1.5% 내지 2% 함유하여 순수 구리보다 금속배선의 비저항을 증가시키지 않으면서 배선의 신뢰성 및 내식성을 향상시킬 수 있으며, 소자의 동작속도을 향상시킬 수 있다.In addition, by containing 1.5% to 2% of titanium, the reliability and corrosion resistance of the wiring can be improved without increasing the specific resistance of the metal wiring than pure copper, and the operating speed of the device can be improved.
Claims (5)
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| KR1020010088318A KR20030059456A (en) | 2001-12-29 | 2001-12-29 | Method for forming metal line in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101030526B1 (en) * | 2004-03-16 | 2011-04-21 | 엘지디스플레이 주식회사 | Method for Forming Line of Liquid Crystal Display Device and method of Manufacturing Liquid Crystal Using the same |
| CN114664732A (en) * | 2022-05-25 | 2022-06-24 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
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2001
- 2001-12-29 KR KR1020010088318A patent/KR20030059456A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101030526B1 (en) * | 2004-03-16 | 2011-04-21 | 엘지디스플레이 주식회사 | Method for Forming Line of Liquid Crystal Display Device and method of Manufacturing Liquid Crystal Using the same |
| CN114664732A (en) * | 2022-05-25 | 2022-06-24 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
| CN114664732B (en) * | 2022-05-25 | 2022-09-16 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
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