KR20030059438A - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- KR20030059438A KR20030059438A KR1020010088299A KR20010088299A KR20030059438A KR 20030059438 A KR20030059438 A KR 20030059438A KR 1020010088299 A KR1020010088299 A KR 1020010088299A KR 20010088299 A KR20010088299 A KR 20010088299A KR 20030059438 A KR20030059438 A KR 20030059438A
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- gate electrode
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 트랜지스터 및 그 형성 방법에 관한 것으로서, 특히 GIDL 전류(Gate Induced Drain Leakage Current)를 감소시켜 소자 특성을 향상시킨 트랜지스터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method of forming the same, and more particularly, to a transistor having a reduced GIDL current (Gate Induced Drain Leakage Current) to improve device characteristics and a method of manufacturing the same.
MOSFET는 게이트 전압에 따라서 소스에서 드레인으로의 전류가 온(on)되거나 오프(off)가 되는데, 이상적인 MOSFET가 아닌 실제의 MOSFET에서는 게이트에 MOSFET를 오프로 만드는 전압이 인가되더라도 전류가 흐르게 되는데, 이러한 전류를 GIDL 전류라 한다. 이러한 GIDL 전류는 반도체 소자의 리프레시 특성을 열화시키는 문제점이 있다. 이러한 문제점을 도 1을 참조하여 상세히 설명하면 다음과 같다.The MOSFET turns on or off from source to drain depending on the gate voltage. In a real MOSFET that is not an ideal MOSFET, current flows even if a voltage is applied to the gate to turn off the MOSFET. The current is called GIDL current. Such a GIDL current has a problem of degrading the refresh characteristics of the semiconductor device. This problem is described in detail with reference to FIG. 1 as follows.
도 1은 GIDL 전류를 설명하기 위한 종래 기술에 따른 트랜지스터의 단면도이다. 도 1을 참조하면, 게이트 전극(30)에 0V가 인가되는 경우, 게이트(30)와 드레인(50) 간의 전압 차이에 의하여 도 1의 화살표와 같이 전기장이 형성된다. 상기 전기장은 측벽 스페이서(60) 하부의 소오스/드레인 영역(50)에서 밴드-투-밴드 터널링(band-to-band tunneling)을 발생시키며, 이로 인한 전자-홀 쌍에서 전자는 드레인(50)을 통하여 방전되며, 홀은 반도체 기판(10)을 통하여 방전된다. 이러한 전자-홀의 이동에 의하여 누설 전류, 즉 GIDL 전류가 발생하게 된다. 이러한 GIDL 전류에 의하여 셀 캐패시터에 저장된 전하가 방전되며, 셀 트랜지스터의 리프레시 특성이 열화된다.1 is a cross-sectional view of a transistor according to the prior art for explaining a GIDL current. Referring to FIG. 1, when 0 V is applied to the gate electrode 30, an electric field is formed as shown by the arrow of FIG. 1 due to the voltage difference between the gate 30 and the drain 50. The electric field causes band-to-band tunneling in the source / drain region 50 under the sidewall spacer 60, whereby electrons in the electron-hole pairs drain the drain 50. Discharge through the semiconductor substrate 10. The movement of the electron-holes causes leakage current, that is, GIDL current. The charge stored in the cell capacitor is discharged by the GIDL current, and the refresh characteristic of the cell transistor is deteriorated.
본 발명은 이러한 문제를 해결하기 위해 절연막과 도전체의 적층 구조로 형성된 측벽 스페이서를 구비함으로써 GIDL 전류를 감소시켜 소자 특성이 향상된 트랜지스터 및 그 제조 방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION In order to solve this problem, an object of the present invention is to provide a transistor having a sidewall spacer formed of a stacked structure of an insulating film and a conductor, thereby reducing a GIDL current and improving device characteristics and a method of manufacturing the same.
도 1은 GIDL 전류를 설명하기 위한 종래 기술에 따른 트랜지스터의 단면도.1 is a cross-sectional view of a transistor according to the prior art for explaining a GIDL current.
도 2는 본 발명에 따른 트랜지스터의 단면도.2 is a cross-sectional view of a transistor according to the present invention.
도 3a 내지 도 3e는 본 발명에 따른 트랜지스터의 제조 공정을 도시한 공정도.3A to 3E are process diagrams illustrating a manufacturing process of the transistor according to the present invention.
본 발명에 따른 반도체 소자 제조 방법은 반도체 기판의 상부에 게이트 산화막 및 폴리실리콘막의 적층 구조를 형성하고 상기 적층 구조를 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 반도체 기판 상에 소오스/드레인 영역을 형성하는 단계 및 상기 게이트 전극의 측벽에 측벽 절연막 및 도전체 스페이서를 형성하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device according to the present invention includes forming a stacked structure of a gate oxide film and a polysilicon film on a semiconductor substrate, and patterning the stacked structure to form a gate electrode, and forming a source electrode on the semiconductor substrate on both sides of the gate electrode. Forming a drain region and forming a sidewall insulating film and a conductor spacer on sidewalls of the gate electrode.
또한 본 발명에 따른 반도체 소자는 반도체 기판과, 상기 반도체 기판의 상부에 위치하며, 게이트 산화막 및 폴리실리콘막의 적층 구조로 형성된 게이트 전극과, 상기 게이트 전극의 양측의 반도체 기판 상에 형성된 소오스/드레인 영역과, 상기 게이트 전극의 측벽에 형성된 소정 두께의 측벽 절연막 및 상기 측벽 절연막의 상부에 형성된 도전체 스페이서를 포함하는 것을 특징으로 한다.In addition, a semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate, a stacked structure of a gate oxide film and a polysilicon film, and a source / drain region formed on a semiconductor substrate on both sides of the gate electrode. And a sidewall insulating film having a predetermined thickness formed on the sidewall of the gate electrode and a conductor spacer formed on the sidewall insulating film.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 2는 본 발명에 따른 트랜지스터의 단면도이다. 도 2를 참조하여 본 발명에 따른 트랜지스터의 구조를 설명하면, 반도체 기판(100)의 상부에 게이트 산화막 및 폴리실리콘막의 적층 구조로 이루어진 게이트 전극(400)이 형성되어 있으며, 게이트 전극(400)의 양측의 반도체 기판(100)에는 소오스(500) 및 드레인(600)이 형성되어 있다. 그리고 게이트 전극(400)의 측벽에는 소정 두께의 측벽 절연막(700)이 형성되어 있으며, 측벽 절연막(700)의 상부에는 도전체 스페이서(900)가 형성되어 있다.2 is a cross-sectional view of a transistor according to the present invention. Referring to FIG. 2, a structure of a transistor according to the present invention will be described. A gate electrode 400 having a stacked structure of a gate oxide film and a polysilicon film is formed on the semiconductor substrate 100, and the gate electrode 400 is formed. The source 500 and the drain 600 are formed in both semiconductor substrates 100. A sidewall insulating film 700 having a predetermined thickness is formed on the sidewall of the gate electrode 400, and a conductor spacer 900 is formed on the sidewall insulating film 700.
도 3a 내지 도 3e는 본 발명에 따른 트랜지스터의 제조 공정을 도시한 공정도이다. 도 3a 내지 도 3e를 참조하여 본 발명에 따른 트랜지스터의 제조 공정을 설명하면 다음과 같다.3A to 3E are flowcharts illustrating a manufacturing process of a transistor according to the present invention. Referring to FIGS. 3A to 3E, a transistor manufacturing process according to the present invention will be described.
반도체 기판(100)의 상부에 게이트 산화막(200) 및 폴리실리콘막(300)의 적층 구조를 형성하고 상기 적층 구조를 패터닝하여 게이트 전극(400)을 형성한다(도 3a 참조). 다음에는, 게이트 전극(400) 양측의 반도체 기판(100) 상에 소오스/드레인 영역(500, 600)을 이온 주입 공정에 의하여 형성한다(도 3b 참조).A stacked structure of the gate oxide film 200 and the polysilicon film 300 is formed on the semiconductor substrate 100, and the stacked structure is patterned to form the gate electrode 400 (see FIG. 3A). Next, source / drain regions 500 and 600 are formed on the semiconductor substrate 100 on both sides of the gate electrode 400 by an ion implantation process (see FIG. 3B).
다음에는 게이트 전극(400)의 측벽에 측벽 절연막(700) 및 도전체 스페이서(900)를 형성한다(도 3c 내지 도 3e 참조). 측벽 절연막(700)은 반도체 기판(100)의 전면에 소정 두께의 절연물(미도시)을 도포하고 이를 식각하여 형성한다. 식각 공정은 건식 또는 습식 방식일 수 있다. 측벽 절연막(700)의 형성 후에 반도체 기판(100)의 전면에 도전층(800)을 형성하고 도전층(800)을 식각하여 도전체 스페이서(900)를 형성한다. 측벽 절연막(700) 및 도전체 스페이서(900)는 소정 두께의 절연물(미도시)을 도포하고 상기 구조물의 상부에 도전층(800)을 형성한 후 상기 절연물 및 도전층(800)을 식각하여 형성할 수도 있다. 이 경우, 도전체 스페이서(900)에 전압을 인가할 수 있도록 도전체 스페이서(900)와 상부의 금속 배선(미도시)과의 연결을 필요로 하므로, 이를 회로적으로 구현하여야 한다.Next, a sidewall insulating film 700 and a conductor spacer 900 are formed on sidewalls of the gate electrode 400 (see FIGS. 3C to 3E). The sidewall insulating layer 700 is formed by coating an insulating material (not shown) having a predetermined thickness on the entire surface of the semiconductor substrate 100 and etching the same. The etching process can be dry or wet. After the sidewall insulating layer 700 is formed, the conductive layer 800 is formed on the entire surface of the semiconductor substrate 100, and the conductive layer 800 is etched to form the conductor spacer 900. The sidewall insulating film 700 and the conductor spacer 900 are formed by coating an insulating material (not shown) having a predetermined thickness, forming a conductive layer 800 on the structure, and then etching the insulating material and the conductive layer 800. You may. In this case, since the connection between the conductor spacer 900 and the upper metal wiring (not shown) is required to apply a voltage to the conductor spacer 900, it must be implemented in a circuit.
본 발명에 따른 트랜지스터의 동작 원리를 설명하면 다음과 같다. 도전체 스페이서(900)에 전압을 인가하면, 하부의 드레인 영역(600)에 전압을 인가하면, 게이트 전극(400)과 드레인 영역(600) 간의 전위차에 의하여 밴드-투-밴드 터널링이 발생하게 되는데, 이때 도전체 스페이서(900)와 드레인 영역(600)에 동일한 전압을 인가하면 드레인 영역(600)에서 밴드-투-밴드 터널링이 발생하는 영역이 게이트 전극(400)의 가장자리만으로 한정되기 때문에 GIDL 전류가 감소하게 된다. 따라서 셀 트랜지스터의 리프레시 특성 열화를 효과적으로 억제할 수 있다.Referring to the operation principle of the transistor according to the present invention. When a voltage is applied to the conductor spacer 900, band-to-band tunneling occurs due to a potential difference between the gate electrode 400 and the drain region 600 when a voltage is applied to the lower drain region 600. In this case, when the same voltage is applied to the conductor spacer 900 and the drain region 600, the region where band-to-band tunneling occurs in the drain region 600 is limited to only the edge of the gate electrode 400. Will decrease. Therefore, the degradation of the refresh characteristics of the cell transistor can be effectively suppressed.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자 및 그 제조 방법은절연막과 도전체의 적층 구조로 이루어진 스페이서를 형성함으로써 GIDL 전류를 감소시켜 소자 특성이 열화되는 것을 방지하는 효과가 있다.As described above, the semiconductor device and the method of manufacturing the same according to the present invention have an effect of preventing the deterioration of device characteristics by reducing the GIDL current by forming a spacer having a laminated structure of an insulating film and a conductor.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1020010088299A KR20030059438A (en) | 2001-12-29 | 2001-12-29 | Semiconductor device and method of fabricating the same |
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| KR1020010088299A KR20030059438A (en) | 2001-12-29 | 2001-12-29 | Semiconductor device and method of fabricating the same |
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| KR20030059438A true KR20030059438A (en) | 2003-07-10 |
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| KR1020010088299A KR20030059438A (en) | 2001-12-29 | 2001-12-29 | Semiconductor device and method of fabricating the same |
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