KR100300057B1 - Manufacturing method for semiconductor memory - Google Patents
Manufacturing method for semiconductor memory Download PDFInfo
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- KR100300057B1 KR100300057B1 KR1019980051332A KR19980051332A KR100300057B1 KR 100300057 B1 KR100300057 B1 KR 100300057B1 KR 1019980051332 A KR1019980051332 A KR 1019980051332A KR 19980051332 A KR19980051332 A KR 19980051332A KR 100300057 B1 KR100300057 B1 KR 100300057B1
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- oxide film
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- peripheral circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Abstract
본 발명은 반도체 메모리 제조방법에 관한 것으로, 종래 반도체 메모리 제조방법은 셀영역과 주변회로영역에 습식분위기에서 증착한 게이트산화막 또는 질화막이 포함된 게이트산화막을 공통으로 형성하여, 메모리의 리프레시 특성이 저하되거나, 주변회로의 신뢰성이 저하되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판을 메모리셀이 제조될 셀영역과 메모리의 주변회로가 형성될 주변회로영역으로 분할하고, 그 셀영역에 모스 트랜지스터와 커패시터를 포함하는 셀구조를 형성하고, 주변회로영역에 필요한 단위소자를 제조하는 반도체 메모리 제조방법에 있어서, 상기 셀영역의 상부에는 습식 분위기에서 게이트산화막을 형성하며, 주변회로영역에서는 질소가 포함된 게이트산화막을 형성하여 반도체 메모리의 리프레시특성의 저하를 방지하고, 주변회로의 신뢰성을 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory. In the related art, a method of manufacturing a semiconductor memory has a gate oxide film including a gate oxide film or a nitride film deposited in a wet atmosphere in a cell region and a peripheral circuit region in common, thereby reducing the refresh characteristics of the memory. Or, there was a problem that the reliability of the peripheral circuit is lowered. In view of the above problems, the present invention divides a substrate into a cell region where a memory cell is to be manufactured and a peripheral circuit region where a peripheral circuit of the memory is to be formed, and forms a cell structure including a MOS transistor and a capacitor in the cell region, A semiconductor memory manufacturing method for manufacturing a unit device required for a circuit region, wherein the gate oxide film is formed in a wet atmosphere on the cell region, and the gate oxide film containing nitrogen is formed in the peripheral circuit region to improve refresh characteristics of the semiconductor memory. There is an effect of preventing the degradation and improving the reliability of the peripheral circuit.
Description
본 발명은 반도체 메모리 제조방법에 관한 것으로, 특히 셀영역의 게이트산화막을 습식 분위기(WET AMBIENT)에서 형성하고, 주변회로영역의 게이트산화막을 질소가 포함된 산화막으로 형성함으로써, 반도체 메모리의 특성을 향상시키는데 적당하도록 한 반도체 메모리 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory. In particular, the gate oxide film of the cell region is formed in a wet atmosphere, and the gate oxide film of the peripheral circuit region is formed of an oxide film containing nitrogen, thereby improving the characteristics of the semiconductor memory. The present invention relates to a method of manufacturing a semiconductor memory, which is suitable for use.
일반적으로, 반도체 소자의 집적도가 향상되면서 발생하는 단채널효과(short channel effect)의 영향을 줄이기 위해 모스 트랜지스터의 게이트산화막을 점차로 얇게 형성하는 추세에 있으나, 이는 게이트산화막의 신뢰성이 저하되는 결과를 낳게 되었으며, 이를 방지하기 위해 질소가 포함된 게이트산화막을 이용하여 일정한 두께 이상의 게이트산화막을 형성하면서도, 단채널효과의 영향을 줄일 수 있게 되었다. 그러나, 이와 같이 질소가 포함된 게이트산화막을 사용하여 메모리셀에 포함되는 모스 트랜지스터의 게이트산화막을 형성하는 경우 문턱전압 조절용 이온의 양을 증가시켜야 하므로 메모리의 리프레시 특성이 저하되며, 이와 같은 게이트산화막을 구비하는 종래 반도체 메모리 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, the gate oxide film of the MOS transistor is gradually formed to reduce the influence of the short channel effect caused by the increase in the degree of integration of the semiconductor device, but this results in a decrease in the reliability of the gate oxide film. In order to prevent this, while forming a gate oxide film having a predetermined thickness or more using a gate oxide film containing nitrogen, the effect of the short channel effect can be reduced. However, when the gate oxide film of the MOS transistor included in the memory cell is formed by using the gate oxide film containing nitrogen as described above, the amount of ions for adjusting the threshold voltage needs to be increased, thereby reducing the refresh characteristics of the memory. Referring to the accompanying drawings, a conventional semiconductor memory manufacturing method is provided in detail as follows.
도1은 종래 반도체 메모리에서 셀영역과 주변회로영역에 게이트를 형성한 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(도면미도시)을 증착하여 소자형성영역(active)을 정의한 다음, 게이트산화막(2)을 습식증착하고, 그 게이트산화막(2)의 상부에 다결정실리콘을 증착하고, 패터닝하여 게이트전극(3)을 형성하는 과정을 포함하여 구성된다.FIG. 1 is a cross-sectional view of a gate formed in a cell region and a peripheral circuit region in a conventional semiconductor memory. As shown in FIG. 1, a field oxide film (not shown) is deposited on an upper portion of a substrate 1 to form an active device formation region. After the definition, the gate oxide film 2 is wet-deposited, polycrystalline silicon is deposited on the gate oxide film 2, and patterned to form the gate electrode 3.
상기와 같이 게이트산화막(2)을 습식(wet ambient)에서 산화막을 증착하여 사용하는 경우에는 상기 설명한 바와 같이 소자의 크기가 작아지면서 단채널효과의 보완을 위해 게이트산화막의 두께를 얇게 하는 경우, 셀영역(10)에 형성된 게이트산화막(2)에는 별다른 문제가 없으나, 주변회로영역(20)에 형성된 게이트산화막(2)을 그 신뢰성이 저하된다.As described above, in the case of using the oxide film deposited in wet (wet ambient) as described above, the size of the device is reduced as described above, and the thickness of the gate oxide film is reduced to compensate for the short channel effect. The gate oxide film 2 formed in the region 10 has no problem, but the reliability of the gate oxide film 2 formed in the peripheral circuit region 20 is reduced.
또한, 도2는 종래 반도체 메모리의 다른 실시예도로서, 이에 도시한 바와 같이 셀영역(10)과 주변회로영역(20)의 상부에 산화막을 증착하고, 질소분위기에서 어닐링하여 질소가 포함된 게이트산화막(4)을 형성하는 단계와; 상기 질소가 포함된 게이트산화막(4)의 상부에 다결정실리콘을 증착하고 패터닝하여 게이트전극(3)을 형성하는 단계를 포함하여 구성한다.FIG. 2 is another embodiment of a conventional semiconductor memory, in which an oxide film is deposited on the cell region 10 and the peripheral circuit region 20, and annealed in a nitrogen atmosphere to form a gate oxide film containing nitrogen. (4) forming; And depositing and patterning polycrystalline silicon on the gate oxide film 4 including nitrogen to form the gate electrode 3.
즉, 도1의 습식 게이트산화막의 문제점을 보완하기 위해 상기 질소가 포함된 게이트산화막(4)을 형성하여 기판(1)과의 계면 특성을 향상시켜 신뢰성을 유지할 수 있게 된다. 그러나, 상기와 같이 질소가 포함된 게이트산화막(4)을 사용할 경우, 고정전하(fixed charge)가 증가하여, 단채널효과의 영향이 증대하게 되어 이를 방지하기 위해 문턱전압조절용 이온주입 도즈량을 증가시키게 되어, 셀영역(10)에서 리프레시 특성이 저하된다. 즉, 문턱전압 조절용 이온주입 증가에의해 소스와 드레인의 계면에서 전계의 증가에 의해 노드 누설전류가 증가하게 되어 메모리를 제조한 후 리프레시 타임을 단축할 수 밖에 없다.That is, in order to compensate for the problem of the wet gate oxide film of FIG. 1, the gate oxide film 4 including the nitrogen may be formed to improve the interface characteristics with the substrate 1 to maintain reliability. However, in the case of using the gate oxide film 4 containing nitrogen as described above, the fixed charge is increased, thereby increasing the influence of the short channel effect, thereby increasing the amount of ion implantation dose for controlling the threshold voltage. As a result, the refresh characteristic is degraded in the cell region 10. That is, the node leakage current increases due to the increase of the electric field at the interface between the source and the drain due to the increase of the ion implantation for controlling the threshold voltage, which inevitably shortens the refresh time after fabricating the memory.
상기한 바와 같이 종래 반도체 메모리 제조방법은 셀영역과 주변회로영역에 질소가 포함된 게이트산화막을 형성할 경우, 고정전하가 증가하여 단채널효과가 증가하게 되며, 이를 방지하기 위해 문턱전압 조절용 이온을 증가시킴으로써, 메모리셀의 리프레시 특성이 저하되는 문제점이 있었으며, 상기 셀영역과 주변회로영역에 순수한 산화막을 사용하여 게이트산화막을 형성할 경우, 주변회로영역의 모스 트랜지스터에서 단채널효과의 방지를 위해 게이트산화막의 두께가 얇아져 그 신뢰성이 저하되는 문제점이 있었다.As described above, in the conventional semiconductor memory manufacturing method, when the gate oxide film including nitrogen is formed in the cell region and the peripheral circuit region, the fixed charge increases to increase the short channel effect. As a result, the refresh characteristics of the memory cell are deteriorated. When the gate oxide film is formed using the pure oxide film in the cell region and the peripheral circuit region, the gate transistor is prevented in the MOS transistor in the peripheral circuit region. There has been a problem that the thickness of the oxide film becomes thin and the reliability thereof decreases.
이와 같은 문제점을 감안한 본 발명은 셀영역과 주변회로영역에 각기 다른 특성의 게이트산화막을 형성하는 반도체 메모리 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor memory in which a gate oxide film having different characteristics is formed in a cell region and a peripheral circuit region.
도1은 종래 반도체 메모리의 일실시 단면도.1 is a cross-sectional view of one embodiment of a conventional semiconductor memory.
도2는 종래 반도체 메모리의 다른 실시 단면도.2 is a cross-sectional view of another embodiment of a conventional semiconductor memory.
도3a 내지 도3c는 본 발명 반도체 메모리의 제조공정 수순단면도.3A to 3C are cross-sectional views of a manufacturing process of the semiconductor memory of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:게이트산화막1: Substrate 2: Gate Oxide
3:게이트전극 4:질소가 포함된 게이트산화막3: gate electrode 4: gate oxide film containing nitrogen
상기와 같은 목적은 기판을 메모리셀이 제조될 셀영역과 메모리의 주변회로가 형성될 주변회로영역으로 분할하고, 그 셀영역에 모스 트랜지스터와 커패시터를 포함하는 셀구조를 형성하고, 주변회로영역에 필요한 단위소자를 제조하는 반도체 메모리 제조방법에 있어서, 상기 셀영역의 상부에는 습식 분위기에서 게이트산화막을 형성하며, 주변회로영역에서는 질소가 포함된 게이트산화막을 형성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The object is to divide the substrate into a cell region where a memory cell is to be manufactured and a peripheral circuit region where a peripheral circuit of the memory is to be formed, and to form a cell structure including a MOS transistor and a capacitor in the cell region, In the semiconductor memory manufacturing method for manufacturing the required unit device, the gate oxide film is formed on the upper part of the cell region in a wet atmosphere, the peripheral circuit region is achieved by forming a gate oxide film containing nitrogen, the present invention When described in detail with reference to the accompanying drawings as follows.
도3a 내지 도3d는 본 발명 반도체 메모리의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(도면미도시)을 증착하여, 셀영역(10)과 주변회로영역(20)을 정의한 후, 상기 셀영역(10)의 상부에 포토레지스트(PR1) 패턴을 형성하고, 기판(1)이 노출된 주변회로영역(20)의 상부에 산화막을 증착한 다음, 질소 분위기에서 어닐링하여 질소가 포함된 게이트산화막(4)을 형성하는 단계(도3a)와; 상기 셀영역(10)의 상부에 형성된 포토레지스트(PR1) 패턴을 제거하고, 다시 상기 주변회로영역(20)의 질소가 포함된 게이트산화막(4)의 상부에 포토레지스트(PR2) 패턴을 형성하고, 습식 분위기에서 게이트산화막(4)을 증착하여 상기 셀영역(10)의 상부에 게이트산화막(2)을 형성하는 단계(도3b)와; 상기 포토레지스트(PR2) 패턴을 제거하고, 다결정실리콘을 상기 게이트산화막(2)과 질소가 포함된 게이트산화막(4)의 상부에 증착하고, 패터닝하여 게이트전극(3)을 형성하는 단계(도3c)를 포함하여 구성된다.3A to 3D are schematic cross-sectional views of a manufacturing process of a semiconductor memory of the present invention. As shown in FIG. 20), a photoresist PR1 pattern is formed on the cell region 10, an oxide film is deposited on the peripheral circuit region 20 where the substrate 1 is exposed, and then, in a nitrogen atmosphere. Annealing to form a gate oxide film 4 containing nitrogen (FIG. 3A); The photoresist PR1 pattern formed on the cell region 10 is removed, and the photoresist PR2 pattern is formed on the gate oxide film 4 containing nitrogen in the peripheral circuit region 20. Depositing a gate oxide film 4 in a wet atmosphere to form a gate oxide film 2 on the cell region 10 (FIG. 3B); Removing the photoresist (PR2) pattern, depositing polycrystalline silicon on top of the gate oxide film (2) and the gate oxide film (4) containing nitrogen, and patterning the gate electrode (3) (Fig. 3c). It is configured to include).
이하, 상기와 같은 본 발명 반도체 메모리 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the semiconductor memory of the present invention as described above will be described in more detail.
먼저, 도3a에 도시한 바와 같이 기판(1)의 상부에 필드산화막을 증착하여 메모리셀을 제조할 셀영역(10)과 메모리의 주변회로를 제조할 주변회로영역(20)을 구분하고, 각각의 영역(10,20)에서 소자형성영역을 설정한다.First, as shown in FIG. 3A, a field oxide film is deposited on the substrate 1 to distinguish a cell region 10 for manufacturing a memory cell and a peripheral circuit region 20 for manufacturing a peripheral circuit of the memory, respectively. In the regions 10 and 20 of FIG.
그 다음, 상기 셀영역(10)과 주변회로영역(20)의 상부에 포토레지스트(PR1)를 도포하고, 노광 및 패턴을 형성하여 상기 셀영역(10)의 상부에만 선택적으로 위치하는 포토레지스트(PR1) 패턴을 형성한다.Next, the photoresist PR1 is coated on the cell region 10 and the peripheral circuit region 20, and an exposure and a pattern are formed to selectively position the photoresist only on the cell region 10. PR1) form a pattern.
그 다음, 상기 주변회로영역(20)의 기판(1)에 게이트산화막을 형성하고, 질소분위기에서 어닐링하여 질소가 포함된 게이트산화막(4)을 형성한다.Next, a gate oxide film is formed on the substrate 1 of the peripheral circuit region 20 and annealed in a nitrogen atmosphere to form a gate oxide film 4 containing nitrogen.
그 다음, 도3b에 도시한 바와 같이 상기 포토레지스트(PR1) 패턴을 제거하고, 포토레지스트(PR2)를 도포하고 노광 및 현상하여 상기 주변회로영역(20)의 질소가 포함된 게이트산화막(4)의 상부에 위치하는 포토레지스트(PR2) 패턴을 형성한다.Next, as shown in FIG. 3B, the photoresist PR1 pattern is removed, the photoresist PR2 is coated, exposed and developed to form a gate oxide film 4 including nitrogen in the peripheral circuit region 20. A photoresist PR2 pattern is formed on the upper portion of the substrate.
그 다음, 상기 셀영역(10)의 기판(1) 상에 습식 분위기에서 게이트산화막(2)을 증착한다.Next, the gate oxide film 2 is deposited on the substrate 1 of the cell region 10 in a wet atmosphere.
그 다음, 도3c에 도시한 바와 같이 상기 포토레지스트(PR2) 패턴을 제거한 후, 상기 노출된 게이트산화막(2)과 질소가 포함된 게이트산화막(4)의 상부전면에 다결정실리콘을 증착하고, 패터닝하여 주변회로영역(20)과 셀영역(10)에 게이트전극(3)을 형성한다.Next, as shown in FIG. 3C, after the photoresist PR2 pattern is removed, polycrystalline silicon is deposited on the upper surface of the exposed gate oxide film 2 and the gate oxide film 4 containing nitrogen, and then patterned. The gate electrode 3 is formed in the peripheral circuit region 20 and the cell region 10.
상기한 바와 같이 본 발명 반도체 메모리 제조방법은 셀영역에 위치하는 게이트산화막을 습식 분위기에서 형성하고, 주변회로영역의 게이트산화막을 질소가 포함된 형태로 제조하여 반도체 메모리의 리프레시특성의 저하를 방지함과 아울러주변회로영역의 단위소자에 대한 신뢰성을 향상시키는 효과가 있다.As described above, the method of manufacturing a semiconductor memory of the present invention forms a gate oxide film located in a cell region in a wet atmosphere, and prepares a gate oxide film in a peripheral circuit region in the form of nitrogen to prevent deterioration of refresh characteristics of the semiconductor memory. In addition, there is an effect of improving the reliability of the unit device in the peripheral circuit area.
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