KR20030058771A - A method of liquid crystal display device - Google Patents

Abstract

PURPOSE: A method for manufacturing a liquid crystal display is provided to prevent under-etching or over-etching of source and drain electrodes, and a semiconductor layer by preventing under ashing or over ashing of a photoresist layer. CONSTITUTION: A gate insulating layer(103), a semiconductor layer(105a), and a metal layer(107a) are accumulated on a substrate(101) where a gate electrode(102) is formed. A first photoresist layer is formed on the metal layer. A second photoresist layer is formed, having an ashing rate slower than an ashing rate of the second photoresist layer. First and second photoresist patterns(109,115) including a half-tone photoresist layer formed at a gate area are formed by using a diffraction mask. The meal layer and the semiconductor layer are etched by using the photoresist patterns. The half-tone photoresist layer is removed. Source and drain electrodes of the gate area and an impurity layer of the semiconductor layer are etched by using the photoresist patterns.

Description

Liquid crystal display device manufacturing method {A METHOD OF LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device. In particular, in a method for manufacturing a liquid crystal display device using a 4-mask, at least two layers having different acing ratios of photoresist applied to form a semiconductor layer and a source / drain electrode of a thin film transistor. The present invention relates to a method for manufacturing a liquid crystal display device capable of preventing the deterioration of the characteristics of a thin film transistor due to the under-aging or over-aging of a photoresist.

Liquid crystal display devices are flat panel display devices, which are mainly applied to portable electronic devices such as notebook computers, PDAs, and mobile phones, as well as high-definition television (HDTV), The range of applications is gradually increasing, such as digital televisions and thin wall-mounted televisions. In general, many kinds of devices such as plasma display panel (PDP), vacuum fluorescent display (VFD) and field emission display (FED) are actively researched as flat panel display devices. The LCD is mainly employed because of advantages such as ease of use, high definition, and the like.

LCD is a device for displaying information on the screen using the refractive anisotropy of the liquid crystal. Typically, the liquid crystal is injected between the lower substrate on which the driving element is formed and the upper substrate on which the color filter is formed to form a liquid crystal layer, and the information is displayed by controlling the amount of light passing through the liquid crystal layer by driving the liquid crystal molecules by the driving element. Done. Various liquid crystal display devices exist, but recently, TFT LCDs employing thin film transistors have been mainly used as driving devices.

TFTs are formed in each of a number of pixels of the liquid crystal display element to independently control the pixels. Such TFT LCDs are mainly manufactured by a complicated process such as a photolithography process using a mask. Therefore, how to simplify the complex process is a major factor for lowering the manufacturing cost of the LCD and increasing the yield, many efforts are made for the process simplification.

The first TFT LCDs were mainly manufactured using 8-masks, but as a result of much research to reduce the number of processes, 7-masks, 6-masks, and 5-masks have gradually been used, and recently, TFTs using 4-masks have been used. LCD is being manufactured.

1 shows a manufacturing process of a TFT LCD using the above-mentioned 4-mask. Referring to the drawings will be described a TFT LCD manufacturing method as follows.

First, as shown in FIG. 1A, a gate electrode 2 made of metal is formed on a transparent first substrate 1 such as glass. The gate electrode 2 is formed by forming a metal layer over the entire substrate 1, applying a photoresist thereon, developing using a first mask, and applying an etchant. As described above, the gate insulating layer 3, the semiconductor layer 5a, and the metal layer 7a are sequentially stacked on the first substrate 1 on which the gate electrode 2 is formed.

Subsequently, as shown in FIG. 1B, after the photoresist layer 9a is applied on the metal layer 7a, the diffraction mask 10 (second mask) is positioned on the photoresist layer 9a. Irradiate light such as ultraviolet rays. The diffraction mask 10 is made of opaque blocking part 10a for blocking the irradiated light, transparent part of the transmissive part 10b for transmitting the irradiated material to the substrate 1, and a slit having a predetermined interval It consists of a slit portion (10c) for adjusting the intensity of the light transmitted to the substrate (1). As shown in the figure, the slit portion 10c is formed with a gate region corresponding to the gate electrode 2 formed on the substrate 1, and the blocking portion 10a is formed on both sides of the slit portion 10c. A TFT is formed by the process, and the transmissive portion 10b is formed in the display portion region where an image is to be displayed.

As described above, the photoresist layer 9a corresponding to the transmissive portion 10b of the diffraction mask 10 is completely formed by applying light to the photoresist layer 9a using the diffraction mask 10 and then acting a developer. Since part of the photoresist layer 9a of the slit portion 10c is removed and part of the slit portion 10c is removed, a photoresist pattern 9 as shown in FIG. 1C is formed on the metal layer 7a. At this time, since the photoresist layer in the region corresponding to the blocking portion 10a is not removed by the developer, the thickness originally deposited is maintained as it is, but the region (gate region) corresponding to the slit portion 10c is in the photoresist. Only part of the layer is removed. Typically, about half of the photoresist layer is removed by the slit portion 10c. The remaining photoresist layer is called a half-tone photoresist layer.

Thereafter, as shown in FIG. 1D, wet etching is performed by an etchant while the part of the metal layer 7a (TFT region) is blocked by the photoresist pattern 9. As the metal layer 7a is etched, a source / drain electrode 7 is formed under the photoresist pattern 9. Subsequently, the semiconductor layer 5a on the substrate 1 on which the source / drain electrodes 7 are formed is dry etched to form the semiconductor layer 5 under the source / drain electrodes 7. At this time, although not shown in the drawing, an ohmic contact layer having a predetermined thickness in which impurities are added is formed on the semiconductor layer 5 in contact with the source / drain electrode 7.

Thereafter, the photoresist pattern 9 is ashed by plasma treatment. As a result, a part of the photoresist pattern 9 is removed. At this time, since the degree of ashing of the photoresist pattern 9 is set to be larger than the thickness of the halftone photoresist layer in the gate region, the halftone photoresist layer is completely removed by the ashing, and as a result, The source / drain electrodes 7 are exposed to the outside.

As shown in FIG. 1 (f), an etchant is applied to the exposed source / drain electrodes 7 to completely remove the metal of the corresponding region, and subsequently a dry etching process is performed to perform the semiconductor layer of the gate region. The ohmic contact layer formed in (5) is removed. As described above, the TFT is formed by removing the source / drain electrode 7 and the ohmic contact layer in the gate region. A passivation layer 11 is laminated on the TFT over the entire substrate 1. A contact hole 12 using a third mask is formed in the protective layer 11. When the pixel electrode 13 made of a transparent material such as indium tin oxide (ITO) is formed on the passivation layer 11 (using a fourth mask), the pixel electrode 13 is formed through the contact hole 12. The source / drain electrodes 7 are electrically connected.

As described above, the TFT array substrate of the LCD is completed by using the 4-mask. As shown in Fig. 1 (g), the completed TFT array substrate is bonded to the color filter substrate 20 having the color filter layer 22 and the black matrix 24 formed thereon, and the liquid crystal 30 is injected into the LCD. To complete. In this case, a spacer 32 is positioned between the TFT array substrate and the color filter substrate to maintain a constant cell gap of the LCD.

In the LCD process using the four-mask as described above, because the process is simple, not only the manufacturing cost is reduced, but also the yield can be improved. However, such a four-mask process has a fatal problem of degrading the characteristics of the TFT, which will be described below.

In the acing process shown in FIG. 1E, the halftone photoresist layer is completely removed by dry etching using plasma to expose the metal layer to the outside. Since the photoresist layer is removed at a constant ashing ratio, the halftone photoresist layer can be completely removed by performing the acing process for a set time. However, the ashing ratio of the photoresist layer during the acing process is sensitively changed depending on the internal process conditions or the external environment. Accordingly, even when acing is performed for a predetermined time, the halftone photoresist layer may be under ashed or over ashed.

FIG. 2A is a diagram illustrating a case in which the halftone photoresist layer is under-acedated. As shown in the figure, the photoresist 8 remains on the source / drain electrodes 7 of the gate region when the halftone photoresist layer is under-acedated. Since the remaining photoresist 8 blocks the etchant during the etching process, when the source / drain electrodes 7 of the gate region are etched, the metal layer of the corresponding region is under-etched, thereby reducing the etching. As shown in FIG. 9, some metal layers 10 remain and the ohmic contact layers below them are not removed. Therefore, the source / drain electrodes 7 are shorted by the metal layer 10 and the underlying ohmic contact layer, which causes a fatal defect in the TFT.

When the halftone photoresist layer is over-acesed, as shown in Fig. 3A, the photoresist layer 9 on both sides of the gate region is excessively ashed. When the halftone photoresist layer is over-acesed, it means that the ashing time is set longer than the set time, or the ashing ratio of the photoresist layer is increased due to the internal conditions or the external environment. Thus, as shown in the figure, the halftone photoresist layer of the gate region is completely removed, but the photoresist layer 9 on both sides is excessively aceed, leaving only the photoresist layer 9 having a thickness smaller than the desired thickness. Will be. If an etchant is applied while the source / drain electrode 7 is blocked by the photoresist layer 9, the photoresist layer 9 may not completely block the etchant, resulting in the source / drain electrode In addition to the fact that (7) is not etched correctly, the channel region of the TFT is overetched during the subsequent process of removing the ohmic contact layer, which causes a problem that the characteristics of the TFT are degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In manufacturing a liquid crystal display device using a 4-mask, the photoresist layer used to form a source / drain electrode and a semiconductor layer of a thin film transistor has a double asing ratio. An object of the present invention is to provide a method for manufacturing a thin film transistor of a liquid crystal display device, which can prevent the under-resistance and over-aging of the photoresist by forming a layer, thereby preventing the deterioration of characteristics of the thin film transistor.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device to which the thin film transistor manufacturing method is applied.

In order to achieve the above object, the liquid crystal display device manufacturing method according to the present invention comprises the steps of forming a gate electrode on a substrate, forming a gate insulating layer, a semiconductor layer and a first metal layer on the gate electrode, Forming a photoresist layer having different acing ratios on the one metal layer, and patterning the photoresist layer using a diffraction mask and patterning the first region where the channel is formed and the thicker than the first region to form a source / drain region. Forming a second region to be formed, etching the first metal layer using the patterned photoresist layer, acing processing the photoresist layer of the second region where the channel is formed, and Continuously etching the first metal layer and the semiconductor layer exposed by the ashing process, and forming a protective layer including contact holes over the entire substrate; And forming a pixel electrode in contact with the first metal layer through the contact hole.

Since the halftone photoresist layer formed in the gate region is mainly composed of a first photoresist layer having a fast acing ratio, even if the halftone photoresist layer is removed during acing, only a small amount of the second photoresist layer is applied. Is removed and removed. Accordingly, by sufficiently setting the halftone acing time, it is possible to prevent under acing from occurring, and also to prevent over acing from occurring due to the slow acing ratio of the second photoresist.

1 is a view showing a manufacturing method of a conventional liquid crystal display device using a 4-mask.

Fig. 2 is a diagram showing a state when the photoresist is under-acedated.

3 is a view showing a state when the photoresist is over-acedated.

4 is a view showing a method of manufacturing a liquid crystal display device using a 4-mask according to the present invention.

** Explanation of symbols for main parts of drawings **

101 substrate 103 gate insulating layer

105: semiconductor layer 107: source / drain electrodes

109,115 photoresist pattern 110 diffraction mask

111: protective layer 112: contact hole

113: pixel electrode

The present invention provides a method for manufacturing a 4-TFT liquid crystal display device. In particular, in the present invention, a photoresist layer composed of at least double layers is formed to form a TFT, and the photoprocess of the TFT is performed. The double photoresist layer has different acing ratios. In particular, the lower photoresist layer has a faster acing ratio, so that a photoresist layer having a faster acing ratio in the gate region exists as a halftone photoresist layer when developing the photoresist layer by diffraction exposure using a diffraction mask. Do it. In this case, since the photoresist layer in which the fast ashing photoresist layer and the slow ashing photoresist layer are laminated on both sides of the gate region is formed, the halftone photoresist layer of the gate region is faster during the acing process. Develop.

As a result, the halftone photoresist layer can be completely removed without excessive acing of the photoresist layer formed on both sides of the gate region by making the ace time of the halftone photoresist layer larger than the set original time. It is possible to prevent under acing. As described above, by preventing undercing or overaging of the photoresist layer, it is possible to prevent deterioration of characteristics of the thin film transistor generated by underetching or overetching of the semiconductor layer and the source / drain electrodes.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a view showing a method for manufacturing a liquid crystal display device according to the present invention. First, as shown in FIG. 4A, a metal such as Al, an Al alloy, or Cu is laminated on a transparent first substrate 101 such as glass, and then etched using a first mask to etch the gate electrode 101. To form. Subsequently, a gate insulating layer 103 such as SiNx or SiOx is formed over the entire substrate 101 on which the gate electrode 102 is formed, an amorphous semiconductor layer 105a doped with impurity ions (n ⁺ ions), Cr, The metal layer 107a made of Mo, Al, Al alloy or Cu is sequentially stacked, and the first photoresist layer 109a and the second photoresist layer 115a are laminated thereon.

The first photoresist layer 109a and the second photoresist layer 115a are mainly stacked by a spin coating method or a screen printing method. First, the first photoresist layer 109a Is applied on the metal layer 107a and then cured, and then the second photoresist layer 115a is applied on the cured first photoresist layer 109a and then cured. In this case, the first photoresist layer 109a and the second photoresist layer 115a may be sequentially applied and then cured at once.

The first photoresist layer 109a is made of a material having an ashing rate that is relatively slower than that of the second photoresist layer 115a. In this case, if the ashing ratio of the first photoresist layer 109a is faster than that of the second photoresist layer 115a, it may be possible to have any ashing ratio.

As described above, as shown in FIG. 4A on the substrate 101 on which the first photoresist layer 109a and the second photoresist layer 115a are formed, the diffraction mask 110 (during a 4-mask process). In the state where the second mask) is placed, light such as ultraviolet rays is irradiated. The diffraction mask 110 is made of an opaque blocking portion (110a) for blocking the irradiated light, the transparent portion made of a transmissive portion (110b) for transmitting the irradiated material to the substrate 101, and a slit having a predetermined interval The slit part 110c which adjusts the intensity of the light transmitted to the board | substrate 101 is comprised. Since the slit part 110c is composed of a set number of slits having a predetermined interval, the photoresist layers 109a and 115a can be irradiated with light having a desired intensity by adjusting the interval and the number of the slits.

Subsequently, a developer is applied to the first photoresist layer 109a and the second photoresist layer 115a irradiated with light through the diffraction mask 110, so that the first photoresist layer 109a and the second photoresist layer. When 115a is developed, all of the first photoresist layer 109a and the second photoresist layer 115a corresponding to the transmission portion 110b of the diffraction mask 110 are removed and the photoresist layer of the slit portion 110c is removed. Since portions of 109a and 115a are removed, a photoresist pattern 109 having a structure as shown in FIG. 1C is formed on the metal layer 107a. At this time, since the first photoresist layer 109a and the second photoresist layer 115a in the region corresponding to the blocking portion 110a are not removed by the developer, the first stacked thickness is maintained as it is. In addition, although some or all of the second photoresist layer 115a is removed from the slit 110c, the first photoresist layer 109a may not be removed at all or only a part of the second photoresist layer 115a may be removed. That is, the halftone photoresist layer may be purely made of the first photoresist layer 109a, or may be made of the first photoresist layer 109a and the second photoresist layer 115a.

The configuration of the halftone photoresist layer may be arbitrarily determined by appropriately adjusting the number and slit interval of the slit portion 110c. In the present invention, the slit interval and the number of the slit portion 110c are adjusted so that the second photoresist layer 115a in the gate region is completely removed and a part of the first photoresist pattern 109 is removed. The halftone photoresist layer in the region was made of only the first photoresist pattern 109 having a faster etching rate.

As described above, as the etchant is applied to the metal layer 107a while the metal layer 107a is blocked by the photoresist patterns 109 and 115, the metal layer 107a in the region excluding the photoresist patterns 109 and 115 is etched. A source / drain electrode 107 is formed below the photoresist patterns 109 and 115, and the semiconductor layer 105a is dry-etched. As shown in FIG. 4 (d), the source / drain electrode 107 is formed. The semiconductor layer 105 is formed below.

Thereafter, as shown in FIG. 4E, the photoresist patterns 109 and 115 are ashed using plasma. As a result, the halftone photoresist layer (ie, the first photoresist pattern of the gate region) formed in the gate region is removed to expose the source / drain electrodes 107 of the gate region to the outside. Meanwhile, when the halftone photoresist layer is removed, part of the second photoresist pattern 115 formed on both sides thereof is also removed. However, since the ashing ratio of the second photoresist pattern 115 is smaller than the ashing ratio of the first photoresist pattern 109, the amount of removal of the second photoresist pattern 115 is reduced by the first photoresist pattern ( It becomes relatively small compared with 109). For example, the thickness of the first photoresist pattern 109 remaining as a halftone photoresist layer assuming that the acing ratio of the first photoresist pattern 109 and the second photoresist pattern 115 is about 1: 2. Assuming that is about 4000 microseconds, only about 2000 microseconds of the second photoresist pattern 115 are removed while the first photoresist pattern 109 is completely removed. Accordingly, the first photoresist pattern 109 and the second photoresist pattern 115 on both sides of the gate region may be sufficiently etched when etching the source / drain electrodes 107 of the subsequent gate region. Will remain thick.

Accordingly, even when the ashing of the first photoresist pattern 109 is set to be longer than the original set acing time (set according to the ashing ratio) in order to prevent under ashing of the halftone photoresist layer. The first photoresist pattern 109 and the second photoresist pattern 115 formed on both sides of the photoresist layer maintain a sufficient thickness to perform an etching blocking function. It is possible to prevent the earrings.

In addition, even when the ashing time of the halftone photoresist layer is set too long, since the second photoresist pattern 115 is ashed at a slower ratio than the first photoresist pattern 109, the halftone photoresist layer The first photoresist pattern 109 and the second photoresist pattern 115 on both sides maintain a sufficient etching blocking thickness.

As a result, by forming the photoresist layer in duplicate, it is possible to prevent under-assessment and over-assessment of the photoresist layer. As a result, the semiconductor layer can be prevented from being under-etched or over-etched, resulting in deterioration of TFT characteristics. You will not.

Subsequently, as illustrated in FIG. 4F, an etchant is applied to the exposed source / drain electrodes 107 to completely remove metals in the gate region, and then a dry etching process is performed to perform the dry etching process. TFTs are formed by removing the ohmic contact layer formed on the substrate. After the protective layer 111 is stacked over the entire substrate 101 on the TFT, a contact hole 112 is formed using a third mask. A pixel electrode 113 made of a transparent material such as ITO is formed on the passivation layer 111 by using a fourth mask, and the pixel electrode 113 is a source / drain electrode 107 through a contact hole 112. Is electrically connected to the.

Although not shown in the drawings, a liquid crystal display device can be fabricated by bonding the TFT array substrate on which TFTs are formed and the color filter substrate on which color filters are formed, and injecting and sealing liquid crystals therebetween.

As described above, in the present invention, the photoresist layer used to form the thin film transistor is composed of two layers having different etching ratios, and the photoresist layers of the two layers are developed by using a diffraction mask to the gate region during acing. It is possible to prevent the photoresist layer from remaining. Therefore, underetching or overetching does not occur during the etching of the source / drain electrodes and the semiconductor layer, thereby preventing the characteristics of the thin film transistor from deteriorating. The ashing ratio of the lower photoresist layer is made of a faster material than the etching ratio of the upper photoresist layer, and the ashing ratios of the upper and upper photoresist layers may be any ashing ratio without being limited. It is of course also possible to form three or more layers having different acing ratios without forming the photoresist layer in two layers.

Using the basic concept of the present invention, such as the use of a photoresist layer having a different acing ratio, anyone in the technical field to which the present invention belongs can easily devise other embodiments or modifications of the present invention. However, these other embodiments or modifications will naturally be included in the scope of the present invention.

As described above, in the present invention, a photoresist layer used in forming a source / drain electrode and a semiconductor layer in a liquid crystal display device manufacturing process may include a first photoresist having a fast ashing ratio and a second photoresist layer having a slow acing ratio. By forming a double layer of, an under acing or an over acing is prevented from occurring in the photoresist layer of the gate region. Therefore, the occurrence of underetching or overetching of the source / drain electrodes and the semiconductor layer caused by the under-assessment and over-assessment of the photoresist layer is prevented, thereby preventing the deterioration of the characteristics of the thin film transistor of the liquid crystal display device. It becomes possible.

Claims (5)

Forming a gate electrode on the substrate; Forming a gate insulating layer, a semiconductor layer, and a first metal layer on the gate electrode; Forming a photoresist layer having a different ashing ratio on the first metal layer; Patterning the photoresist layer using a diffraction mask to form a first region in which a channel is formed and a second region in which a source / drain region is formed thicker than the first region; Etching the first metal layer using the patterned photoresist layer; Acing the photoresist layer of the second region where the channel is formed; Continuously etching the first metal layer and the semiconductor layer exposed by the ashing process; Forming a protective layer having contact holes throughout the substrate; And forming a pixel electrode in contact with the first metal layer through the contact hole. The method of claim 1, wherein the photoresist layer, A first photoresist layer having a predetermined acing ratio; And And a second photoresist layer having a faster acing ratio than the first photoresist layer. The method of claim 1, wherein the diffraction mask, A slit portion configured to have a slit having a predetermined interval, the slit portion for controlling the intensity of light irradiated to the first photoresist layer and the second photoresist layer in the gate region; A blocking unit which is opaque and blocks light irradiated to the first photoresist layer and the second photoresist layer on both sides of the gate region; And The transparent method is characterized in that consisting of a transmission portion for transmitting the light to the first photoresist layer and the second photoresist layer. The method of claim 1, wherein the ashing of the photoresist layer is performed by dry etching using plasma. Sequentially stacking a gate insulating layer, a semiconductor, and a metal layer over the entire substrate on which the gate electrode is formed; Forming a first photoresist layer on the metal layer; Forming a second photoresist layer on the first photoresist layer, the second photoresist layer having an acing ratio slower than that of the first photoresist layer; Forming a photoresist pattern including a halftone photoresist layer formed in the gate region using a diffraction mask; Etching the metal layer and the semiconductor using the photoresist pattern; Removing the halftone photoresist layer; And And etching the source / drain electrodes of the gate region and the impurity layer of the semiconductor layer by using the photoresist pattern from which the halftone photoresist layer has been removed.