KR20030058035A - Fabricating method for semiconductor device - Google Patents
Fabricating method for semiconductor device Download PDFInfo
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- KR20030058035A KR20030058035A KR1020010088187A KR20010088187A KR20030058035A KR 20030058035 A KR20030058035 A KR 20030058035A KR 1020010088187 A KR1020010088187 A KR 1020010088187A KR 20010088187 A KR20010088187 A KR 20010088187A KR 20030058035 A KR20030058035 A KR 20030058035A
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- tungsten film
- semiconductor device
- manufacturing
- vapor deposition
- mechanical polishing
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 53
- 239000010937 tungsten Substances 0.000 claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 230000003746 surface roughness Effects 0.000 claims abstract description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 15
- 238000007517 polishing process Methods 0.000 claims description 11
- 239000002002 slurry Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000007800 oxidant agent Substances 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 239000003292 glue Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 텅스텐막의 표면을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)방법으로 소정 두께 제거하여 표면 거칠기를 개선함으로써 후속 공정을 용이하게 하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a semiconductor that facilitates a subsequent process by removing a predetermined thickness of a surface of a tungsten film by chemical mechanical polishing (hereinafter referred to as CMP) to improve surface roughness. It relates to a method for manufacturing a device.
소자가 고집적화 및 고속화 되어감에 따라 배선의 선폭 및 간격이 감소되어 사진공정 시 마스크들 간에 정확하고 엄격한 정렬이 요구되어 공정 여유도가 감소되고, 저저항의 배선 재료가 요구되고 있다.As devices become more integrated and faster, line widths and spacing of wirings are reduced, so that accurate and strict alignment between masks is required in the photolithography process, so that process margins are reduced, and low resistance wiring materials are required.
상기 저저항의 배선 재료로서 텅스텐막이 사용되고 있으며, 상기 텅스텐막은 화학기상증착(chemical vapor deposition, 이하 CVD 라 함)방법 또는 물리기상증착(physical vapor deposition, 이하 PVD라 함)방법으로 형성할 수 있다.A tungsten film is used as the low resistance wiring material, and the tungsten film can be formed by chemical vapor deposition (hereinafter referred to as CVD) or physical vapor deposition (hereinafter referred to as PVD).
상기 CVD방법으로 형성된 텅스텐막은 스텝 커버리지(step coverage)는 우수하나, PVD방법으로 형성된 텅스텐막에 비하여 그 표면의 거칠기가 매우 열악하다.The tungsten film formed by the CVD method has excellent step coverage, but the surface roughness of the tungsten film formed by the PVD method is very poor.
또한, PVD방법으로 형성된 텅스텐막은 표면의 거칠기가 우수한 반면에 스텝 커버리지가 열악하여 콘택과 배선을 동시에 형성하는 배선 공정에는 사용할 수 없다.In addition, the tungsten film formed by the PVD method is excellent in surface roughness but poor in step coverage and cannot be used in a wiring process for simultaneously forming a contact and wiring.
따라서, 상기 CVD방법으로 콘택 매립을 실시하고, PVD방법으로 배선을 형성하는 방법이 사용되고 있다.Therefore, a method of filling a contact by the CVD method and forming a wiring by the PVD method is used.
그러나, 상기와 같은 종래기술에 따른 반도체소자의 제조방법은, CVD방법으로 텅스텐막을 형성하는 경우 그 표면의 거칠기가 매우 열악하여 0.10㎛ 이하의 선폭을 갖도록 사진공정을 실시하는 경우 텅스텐막 표면의 거칠기에 의한 난반사에 의해 패턴의 재현성이 저하되고, 그에 따른 소자의 특성 및 신뢰성이 저하되는 문제점이 있다.However, in the method of manufacturing a semiconductor device according to the prior art as described above, when the tungsten film is formed by the CVD method, the surface roughness is very poor, and the surface roughness of the tungsten film is performed when the photographing process is performed to have a line width of 0.10 μm or less. There is a problem that the reproducibility of the pattern is lowered due to the diffuse reflection caused by the reflection, thereby degrading the characteristics and the reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 텅스텐막을 증착하고, 상기 텅스텐막 표면을 CMP방법으로 소정 두께 제거하여 표면의 거칠기를 개선함으로써 후속 사진공정을 용이하게 하여 패턴의 재현성을 향상시키고 그에 따른 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by depositing a tungsten film, by removing a predetermined thickness of the surface of the tungsten film by improving the roughness of the surface by facilitating subsequent photographic process to improve the reproducibility of the pattern It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the characteristics and reliability of the device.
도 1 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.
도 2a 는 본 발명에 따른 반도체소자의 제조방법에서 화학기상증착방법으로 텅스텐막을 형성한 후 표면의 거칠기를 나타내는 사진.Figure 2a is a photograph showing the surface roughness after forming a tungsten film by the chemical vapor deposition method in the method of manufacturing a semiconductor device according to the present invention.
도 2b 는 본 발명에 따른 반도체소자의 제조방법에서 화학기상증착방법으로 텅스텐막을 형성한 후 화학적 기계적 연마방법으로 표면의 거칠기가 제거된 것을 나타내는 사진.Figure 2b is a photograph showing that the surface roughness is removed by the chemical mechanical polishing method after forming a tungsten film by the chemical vapor deposition method in the method of manufacturing a semiconductor device according to the present invention.
도 3a 는 본 발명에 따른 반도체소자의 제조방법에서 물리기상증착방법으로 텅스텐막을 형성한 후 표면의 거칠기를 나타내는 사진.Figure 3a is a photograph showing the surface roughness after forming a tungsten film by a physical vapor deposition method in the method of manufacturing a semiconductor device according to the present invention.
도 3b 는 본 발명에 따른 반도체소자의 제조방법에서 물리기상증착방법으로 텅스텐막을 형성한 후 화학적 기계적 연마방법으로 표면의 거칠기가 제거된 것을 나타내는 사진.Figure 3b is a photograph showing that the surface roughness is removed by a chemical mechanical polishing method after forming a tungsten film by physical vapor deposition method in the method of manufacturing a semiconductor device according to the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11 : 반도체기판 13 : 층간절연막11 semiconductor substrate 13 interlayer insulating film
15 : TiN막 17 : 텅스텐막15 TiN film 17 Tungsten film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
반도체기판 상부에 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a contact hole on the semiconductor substrate;
전체표면 상부에 접착층인 TiN막을 형성하는 공정과,Forming a TiN film as an adhesive layer on the entire surface,
상기 TiN막 상부에 텅스텐막을 형성하는 공정과,Forming a tungsten film on the TiN film;
상기 텅스텐막의 표면을 화학적 기계적 연마공정으로 소정 두께 제거하여 표면의 거칠기를 제거하는 공정과,Removing the surface roughness by removing the surface of the tungsten film by a chemical mechanical polishing process;
상기 TiN막은 화학기상증착방법 또는 물리기상증착방법으로 100 ∼ 400Å 두께 형성되는 것과,The TiN film is formed by the chemical vapor deposition method or physical vapor deposition method of 100 ~ 400Å thickness,
상기 텅스텐막은 화학기상증착방법, 물리기상증착방법 또는 원자층증착방법으로 형성되는 것과,The tungsten film is formed by a chemical vapor deposition method, a physical vapor deposition method or an atomic layer deposition method,
상기 텅스텐막은 WF6, SiH4및 H2혼합기체 또는 WF6와 H2혼합기체를 이용하는 화학기상증착방법으로 형성되는 것과,The tungsten film is formed by a chemical vapor deposition method using a WF 6 , SiH 4 and H 2 mixed gas or a WF 6 and H 2 mixed gas,
상기 텅스텐막은 타겟(target)의 10 ∼ 20% 두껍게 형성되는 것과,The tungsten film is formed to be 10 to 20% thick of the target (target),
상기 화학적 기계적 연마공정은 상기 텅스텐막 증착 두께의 0 ∼ 20%를 제거하는 터치 폴리싱으로 실시되는 것과,The chemical mechanical polishing process is performed by touch polishing to remove 0 to 20% of the thickness of the tungsten film deposition,
상기 화학적 기계적 연마공정은 산도가 pH 2∼ 7인 슬러리를 이용하여 실시되는 것과,The chemical mechanical polishing process is carried out using a slurry having an acidity of pH 2-7,
상기 화학적 기계적 연마공정은 산화제로 2 ∼ 6vol%의 H2O2가 함유된 슬러리를 이용하여 실시되는 것과,The chemical mechanical polishing process is carried out using a slurry containing 2 to 6vol% H 2 O 2 as an oxidizing agent,
상기 화학적 기계적 연마공정은 연마제로 SiO2, CeO2또는 Al2O3가 함유된 슬러리를 이용하여 실시되는 것을 포함하는 것을 특징으로 한다.The chemical mechanical polishing process may be performed using a slurry containing SiO 2 , CeO 2 or Al 2 O 3 as an abrasive.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11) 상부에 콘택홀이 구비되는 층간절연막(13)을 형성한다.First, an interlayer insulating film 13 having a contact hole is formed on the semiconductor substrate 11.
다음, 전체표면 상부에 접착층인 TiN막(15)을 소정 두께 증착한다. 이때, 상기 TiN막(15)은 상기 층간절연막(13)과 후속공정으로 형성되는 텅스텐막 간의 접착 특성을 향상시키기 위하여 CVD방법 또는 PVD방법으로 100 ∼ 400Å 두께 형성된다.Next, a TiN film 15, which is an adhesive layer, is deposited on the entire surface. At this time, the TiN film 15 is formed to have a thickness of 100 to 400 kPa by the CVD method or the PVD method in order to improve the adhesive property between the interlayer insulating film 13 and the tungsten film formed by a subsequent process.
그 다음, 상기 TiN막(15) 상부에 텅스텐막(17)을 형성한다. 이때, 상기 텅스텐막(17)은 CVD방법, PVD방법 또는 원자층증착(atomic layer deposition, ALD)방법으로 형성되고, 타겟(target)의 10 ∼ 20% 두껍게 형성된다. 여기서, 상기 텅스텐막을 CVD방법으로 증착하는 경우 WF6, SiH4및 H2혼합기체 또는 WF6와 H2혼합기체를 이용하여 형성한다.Next, a tungsten film 17 is formed on the TiN film 15. In this case, the tungsten film 17 is formed by a CVD method, a PVD method or an atomic layer deposition (ALD) method, and is formed to be 10 to 20% thick of a target. Here, when the tungsten film is deposited by CVD, it is formed using a mixed gas of WF 6 , SiH 4 and H 2, or a mixed gas of WF 6 and H 2 .
다음, 상기 텅스텐막(17)의 표면을 CMP공정으로 소정 두께 제거하여 표면 거칠기를 제거한다. 이때, 상기 CMP공정은 상기 텅스텐막(17) 증착 두께의 0 ∼ 20%를 제거하도록 실시된다.Next, the surface of the tungsten film 17 is removed by a predetermined thickness by a CMP process to remove surface roughness. In this case, the CMP process is performed to remove 0 to 20% of the thickness of the tungsten film 17 deposited.
여기서, 상기 텅스텐막(17)의 표면 일부만 제거하는 CMP공정은 산도가 pH 2∼ 7이고, 산화제로 2 ∼ 6vol%의 H2O2가 함유되어 있으며, 연마제로 SiO2, CeO2또는 Al2O3가 함유된 슬러리를 이용하여 실시된다. (도 1 참조)Here, the CMP process of removing only part of the surface of the tungsten film 17 has an acidity of pH 2 to 7, contains 2 to 6 vol% of H 2 O 2 as an oxidizing agent, and SiO 2 , CeO 2 or Al 2 as an abrasive. It is carried out using a slurry containing O 3 . (See Figure 1)
도 2a 및 도 2b 는 텅스텐막을 CVD방법으로 증착한 후 CMP공정을 실시한 경우 실험 결과를 나타내는 사진이고, 도 3a 및 도 3b 는 텅스텐막을 PVD방법으로 증착한 후 CMP공정을 실시한 경우 실험 결과를 나타내는 사진이다.2A and 2B are photographs showing experimental results when the CMP process was carried out after the deposition of the tungsten film by the CVD method, and FIGS. 3A and 3B are photographs showing the experimental results when the CMP process was performed after the tungsten film was deposited by the PVD method. to be.
도 2a 는 CVD방법으로 증착된 텅스텐막의 표면 거칠기를 AFM(atomic force microscope)로 촬영한 사진이다. 이때, 상기 텅스텐막은 5000Å 두께로 증착된 것이고, 텅스텐막 표면의 거칠기의 피크(pick)와 밸리(valley) 간의 거리는 1700Å이며, 그 평균치(root mean squared value)는 250Å이다.2A is a photograph of the surface roughness of the tungsten film deposited by the CVD method with an atomic force microscope (AFM). At this time, the tungsten film is deposited with a thickness of 5000 kPa, the distance between the pick and the valley of the roughness of the surface of the tungsten film is 1700 kPa, the root mean squared value is 250 kPa.
도 2b 는 도 2a 의 텅스텐막 표면을 CMP공정으로 소정 두께 제거하여 표면의거칠기를 제거한 것을 나타내는 사진으로서, 피크와 밸리 간의 거리는 140Å이며, 그 평균치는 15Å으로 텅스텐막 표면의 거칠기가 개선된 것을 알 수 있다.FIG. 2B is a photograph showing that the surface of the tungsten film of FIG. 2A is removed by a predetermined thickness to remove the roughness of the surface. The distance between the peak and the valley is 140 mm, and the average value is 15 mm, indicating that the surface roughness of the tungsten film is improved. Can be.
여기서, 상기 CMP공정은 Lam Teres 장비를 이용하고, 해드 압력(head pressure)는 3psi, 벨트 스피드(belt speed)는 400fpm, 슬러리(slurry)는 4vol%의 H2O2를 함유하는 Cabot SS-W2000 및 패드는 IC-1000을 이용하는 조건으로 실시된 것이다.Here, the CMP process using a Lam Teres equipment, head pressure (head pressure) 3psi, belt speed (belt speed) 400fpm, slurry (slurry) containing 4vol% H 2 O 2 Cabot SS-W2000 And the pad was carried out under the condition of using IC-1000.
상기 CMP공정 후 NH4OH와 HF를 이용한 포스트 세정공정을 실시한다.After the CMP process, a post-cleaning process using NH 4 OH and HF is performed.
도 3a 는 PVD방법으로 증착된 텅스텐막의 표면 거칠기를 AFM으로 촬영한 사진이다. 이때, 상기 텅스텐막은 3000Å 두께로 증착된 것이고, 텅스텐막 표면의 거칠기의 피크와 밸리 간의 거리는 150Å이며, 그 평균치는 14Å이다.3A is a photograph taken by AFM of the surface roughness of the tungsten film deposited by the PVD method. At this time, the tungsten film was deposited with a thickness of 3000 GPa, the distance between the peak and valley of the roughness of the surface of the tungsten film was 150 GPa, and the average value was 14 GPa.
도 3b 는 도 3a 의 텅스텐막 표면을 CMP공정으로 소정 두께 제거하여 표면의 거칠기를 제거한 것을 나타내는 사진으로서, 피크와 밸리 간의 거리는 100Å이며, 그 평균치는 8Å으로 텅스텐막 표면의 거칠기가 개선된 것을 알 수 있다. 상기 CMP공정은 상술된 조건과 같은 조건으로 실시되었다.FIG. 3B is a photograph showing that the surface of the tungsten film of FIG. 3A is removed by a predetermined thickness by a CMP process, and the surface roughness is removed. The distance between the peak and the valley is 100 microns, and the average value is 8 microns. Can be. The CMP process was carried out under the same conditions as described above.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 텅스텐막을 증착하고, 상기 텅스텐막 표면 일부를 화학적 기계적 연마(chemical mechanical polishing)공정으로 제거하여 텅스텐막의 표면 거칠기를 제거함으로써 텅스텐막 표면 거칠기에 의한 난반사를 감소시켜 후속공정을 용이하게 하고, 특히표면 거칠기가 열악한 화학기상증착방법으로 형성된 텅스텐막만을 사용하여 미세한 선폭을 갖는 배선을 형성할 수 있으므로 공정을 단순하게 하고 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the surface roughness of the tungsten film is removed by depositing a tungsten film and removing a part of the surface of the tungsten film by a chemical mechanical polishing process. Reduces diffuse reflection due to simplification of the subsequent process, and since the wiring having a fine line width can be formed only by using a tungsten film formed by a chemical vapor deposition method having a poor surface roughness, the process is simplified and the integration of semiconductor devices is high accordingly. There is an advantage to this end.
Claims (9)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09326392A (en) * | 1996-06-04 | 1997-12-16 | Nec Corp | Method of polishing multilayer wiring |
| KR19980063840A (en) * | 1996-12-06 | 1998-10-07 | 가네꼬히사시 | How to Form a Buried Plug and Interconnect |
| KR19990001543A (en) * | 1997-06-16 | 1999-01-15 | 윤종용 | Flattening method of tungsten film using chemical mechanical polishing process |
| KR0172042B1 (en) * | 1995-12-12 | 1999-03-30 | 김주용 | Method of manufacturing tungsten plug of semiconductor device |
| US6107193A (en) * | 1997-12-19 | 2000-08-22 | Mosel Vitelic Inc. | Completely removal of TiN residue on dual damascence process |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0172042B1 (en) * | 1995-12-12 | 1999-03-30 | 김주용 | Method of manufacturing tungsten plug of semiconductor device |
| JPH09326392A (en) * | 1996-06-04 | 1997-12-16 | Nec Corp | Method of polishing multilayer wiring |
| KR19980063840A (en) * | 1996-12-06 | 1998-10-07 | 가네꼬히사시 | How to Form a Buried Plug and Interconnect |
| KR19990001543A (en) * | 1997-06-16 | 1999-01-15 | 윤종용 | Flattening method of tungsten film using chemical mechanical polishing process |
| US6107193A (en) * | 1997-12-19 | 2000-08-22 | Mosel Vitelic Inc. | Completely removal of TiN residue on dual damascence process |
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