KR20030057898A - Method of forming a contact in a semiconductor device - Google Patents
Method of forming a contact in a semiconductor device Download PDFInfo
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- KR20030057898A KR20030057898A KR1020010088001A KR20010088001A KR20030057898A KR 20030057898 A KR20030057898 A KR 20030057898A KR 1020010088001 A KR1020010088001 A KR 1020010088001A KR 20010088001 A KR20010088001 A KR 20010088001A KR 20030057898 A KR20030057898 A KR 20030057898A
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 124
- 238000005530 etching Methods 0.000 claims abstract description 57
- 239000007769 metal material Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000001052 transient effect Effects 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910021645 metal ion Inorganic materials 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 claims 1
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 14
- 230000001965 increasing effect Effects 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
Description
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 특히 콘택 마스크층을 이용하여 콘택홀을 형성함에 있어, 콘택 마스크층으로 일렉트론 서페이스 챠징(electron surface charging)이 발생하지 않는 금속계 물질층을 사용하여 양호한 형상(profile)의 콘택홀을 얻을 수 있을 뿐만 아니라, 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and in particular, in forming a contact hole using a contact mask layer, it is preferable to use a metal material layer that does not generate electron surface charging as a contact mask layer. The present invention relates to a method for forming a contact for a semiconductor device capable of obtaining a contact hole of a profile and improving the electrical characteristics of the device.
일반적으로, 반도체 소자를 제조함에 있어, 단위 소자를 전기적으로 연결시키거나 상부 도전층 및 하부 도전층을 전기적으로 상호 연결시키기 위하여 콘택 공정을 실시하고 있다. 콘택 공정을 통해 절연층을 식각하여 형성되는 콘택홀의 형상은 반도체 소자가 고집적화되어 감에 따라 매우 중요하다. 즉, 콘택홀 형상이 나쁠 경우 콘택 저항의 증가를 초래하여 소자의 수율 및 신뢰성을 저하시키게 된다.In general, in manufacturing a semiconductor device, a contact process is performed to electrically connect the unit devices or to electrically interconnect the upper conductive layer and the lower conductive layer. The shape of the contact hole formed by etching the insulating layer through the contact process is very important as the semiconductor device is highly integrated. In other words, if the contact hole shape is bad, the contact resistance is increased to reduce the yield and reliability of the device.
도 1a 내지 도 1c는 종래 반도체 소자의 콘택 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method for forming a contact of a conventional semiconductor device.
도 1a를 참조하면, 하부 소자가 형성된 하지층(11) 상에 층간 절연막(12)을 형성한다. 콘택이 형성될 부분이 개방된(open) 포토레지스트 마스크층(13)을 층간 절연막(12) 상에 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a base layer 11 on which a lower element is formed. A photoresist mask layer 13 is formed on the interlayer insulating film 12 in which a portion where a contact is to be formed is open.
도 1b를 참조하면, 포토레지스트 마스크층(13)을 이용한 콘택 식각 공정으로 층간 절연막(12)의 일부분을 제거하여 하지층(11)이 노출된 콘택홀(14)을 형성한다. 포토레지스트 마스크층(13)은 콘택 식각 공정 동안 일정 두께 제거되어 잔류 마스크층(13a)으로 남게된다.Referring to FIG. 1B, a portion of the interlayer insulating layer 12 is removed by a contact etching process using the photoresist mask layer 13 to form a contact hole 14 through which the underlying layer 11 is exposed. The photoresist mask layer 13 is removed to a certain thickness during the contact etching process to remain as the residual mask layer 13a.
도 1c를 참조하면, 잔류 마스크층(13a)을 포토레지스트 제거 공정을 통해 제거하고, 이로 인하여 콘택홀(14) 형성이 완료된다.Referring to FIG. 1C, the residual mask layer 13a is removed through a photoresist removal process, thereby completing the formation of the contact hole 14.
상기와 같이 포토레지스트를 콘택 마스크층으로 이용할 경우 일렉트론 쉐딩 이펙트(electron shading effect)에 의한 하부 소자의 마이크로트렌칭(microtrenching) 현상과 플라즈마 인듀스드-챠징 데미지(plasma induced-charging damage)로 인하여 콘택홀(14)의 형상이 나쁘게 될 뿐만 아니라 소자의 전기적 특성 또한 저하시키게 되는데, 이를 설명하면 다음과 같다.When the photoresist is used as the contact mask layer as described above, the contact is caused by the microtrenching phenomenon of the lower element due to the electron shading effect and the plasma induced-charging damage. Not only is the shape of the hole 14 deteriorated, but also the electrical characteristics of the device is reduced, which will be described below.
절연체 물질인 포토레지스트를 콘택 마스크로 이용할 경우, 콘택 식각 공정 진행중의 웨이퍼(Wafer) 기판 주변에는 일렉트론과 이온(Ion)의 이동도(Mobility) 차이에 의하여 쉬드 영역(Sheath Region)이 형성되고, 쉬드(Sheath)내의 일렉트론과 이온의 각 분포(Angular Distribution) 차이는 포토레지스트 마스크층(13) 상부에 일렉트론 서페이스 챠징(Electron Surface Charging)에 의한 네거티브(Negative) 극성의 국부적인 전기장을 형성한다. 이러한 포토레지스트 마스크층(13) 상부의 네거티브 극성 전기장은 일렉트론에게는 전기적 척력을, 이온에게는 전기적 인력을 형성함으로써 이온만이 포토레지스트 마스크층(13)의 개방된 부위를 통과하여 하부 식각층에 도달하게 되는 현상을 일렉트론 쉐딩 이펙트라 하며, 이러한 일렉트론 쉐딩 이펙트는 반도체 소자의 직접도가 증가할수록, 즉, 포토레지스트 마스크층(13)의 개방된 부분의 간격이 좁아질수록, 또한 플라즈마 내부의 일렉트론 온도(Electron Temperature)가 높을수록 그 효과가 증가하게 된다.When using a photoresist, which is an insulator material, as a contact mask, a sheath region is formed around a wafer substrate during a contact etching process due to a difference in mobility between electrons and ions. The difference in the angular distribution of electrons and ions in (Sheath) forms a local electric field of negative polarity due to Electron Surface Charging on the photoresist mask layer 13. The negative polar electric field on the photoresist mask layer 13 forms an electrical repulsive force on the electrons and an electrical attractive force on the ions so that only ions pass through the open portion of the photoresist mask layer 13 to reach the lower etching layer. This phenomenon is referred to as an electron shedding effect, and the electron shedding effect increases as the directivity of the semiconductor device increases, that is, as the gap between the open portions of the photoresist mask layer 13 becomes smaller, and also the electron temperature inside the plasma ( The higher the Electron Temperature, the greater the effect.
플라즈마 내부의 이온/라디컬(Ion/Radical) 입자들의 식각단면 입사밀도가 일정 지역에 집중되게 되어 식각면의 수직방향 식각 속도의 차이가 발생하는 현상을 마이크로트렌칭(Microtrenching) 이라 하는데, 마이크로트렌칭은 이온, 라디컬 간의 충돌, 이온/라디컬과 마스크/식각 측면과의 충돌, 일렉트론 쉐딩 이펙트에 의한 이온 입자의 궤도 변곡 등에 의하여 발생하며, 하부 소자에 물리적 손상(Physical Damage)를 주어 반도체 소자의 특성을 저하 시킨다. 마이크로트렌칭 현상은 패턴 밀도(Pattern Density)와 일렉트론/이온의 온도(Electron/Ion Temperature), 패턴 애스펙트 비(Pattern Aspect Ratio)의 영향을 받는다.Microtrenching is a phenomenon in which the etch cross-section incident density of ion / radical particles in the plasma is concentrated in a certain region, and thus the difference in the vertical etching speed of the etch plane occurs. Wrenching is caused by collisions between ions and radicals, collisions between ions / radicals and masks / etching sides, orbital inflection of ionic particles due to the electron shedding effect, and can cause physical damage to underlying devices. Decreases the properties of The micro trenching phenomenon is influenced by the pattern density, the electron / ion temperature, and the pattern aspect ratio.
포토레지스트 마스크층(13)을 이용한 콘택 식각 공정중 과도 식각 공정시 포토레지스트 마스크층(13) 주변의 일렉트론 쉐딩 이펙트에 의한 콘택 식각 단면에서의 불균일한 이온 전하 축적 현상이 하부 단위소자 주변에 전위차를 형성하여 파울러-노드하임 터널링(Fowler-Nordheim Tunneling) 현상에 의한 하부 단위소자의 전기적 손상이 발생하는 경우를 플라즈마 인듀스드-챠징 데미지(Plasma Induced-Charging Damage)라 한다.During the transient etching process of the contact etching process using the photoresist mask layer 13, an uneven ion charge accumulation phenomenon in the contact etching cross section due to the electron shedding effect around the photoresist mask layer 13 causes a potential difference around the lower unit device. When the electrical damage of the lower unit device due to the Fowler-Nordheim Tunneling phenomenon is formed is called plasma induced-charging damage (Plasma Induced-Charging Damage).
상기한 현상 이외에도 포토레지스트 마스크층(13)과 산화물 계통으로 형성되는 층간 절연막(12)간의 식각 선택 또한 콘택홀(14) 형성에 문제를 유발시킨다. 산화물에 대한 포토레지스트 마스크층의 선택성(PR Mask Selectivity to Oxide)은 주식각층인 산화막의 식각속도와 포토레지스트 마스크층의 식각속도의 비율로서, 깊은 콘택 형성을 위해서는 포토레지스트 마스크층의 두께를 두껍게 해야할 뿐만 아니라 고선택비 특성의 공정조건이 요구된다. 반도체 소자의 집적도의 증가로 콘택의 임계 값(CD)이 감소하는 경우, 노광 공정의 특성상 포토레지스트 마스크층의 두께는 낮아지게 되고, 캐패시터의 용량 확보를 위하여 콘택 깊이는 증가하게 된다.또한 고선택비 콘택 식각 공정은 CD 바이어스(Bias)와 콘택 형상(Contact Profile)등의 타 식각 공정 변수와 연동되어 선택비 증가에 한계가 존재하므로, 새로운 고선택비 식각 공정 가스, 펄스 플라즈마 식각(Pulsed Plasma Etch)등의 새로운 식각 공정 기술 개발이 요구되고 있다.In addition to the above phenomenon, the etching selection between the photoresist mask layer 13 and the interlayer insulating layer 12 formed of an oxide system also causes a problem in forming the contact hole 14. PR Mask Selectivity to Oxide is the ratio of the etch rate of the oxide film, which is the stock layer, to the etch rate of the photoresist mask layer, and the thickness of the photoresist mask layer must be increased for deep contact formation. In addition, high selectivity process conditions are required. When the contact threshold (CD) decreases due to the increase in the degree of integration of the semiconductor device, the thickness of the photoresist mask layer is reduced due to the characteristics of the exposure process, and the contact depth is increased to secure the capacity of the capacitor. Since the non-contact etching process has a limitation in increasing the selectivity in conjunction with other etching process variables such as CD bias and contact profile, a new high selectivity etching process gas and pulsed plasma etching The development of new etching process technology is required.
따라서, 본 발명은 콘택 마스크층을 이용하여 콘택홀을 형성함에 있어, 콘택 마스크층으로 일렉트론 서페이스 챠징이 발생하지 않는 금속계 물질층을 사용하여 양호한 형상의 콘택홀을 얻을 수 있을 뿐만 아니라, 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 콘택 형성 방법을 제공함에 그 목적이 있다.Therefore, in the present invention, in forming the contact hole using the contact mask layer, not only a contact hole having a good shape can be obtained by using a metal material layer which does not generate electrosurface charging as the contact mask layer, but also the electrical It is an object of the present invention to provide a method for forming a contact of a semiconductor device capable of improving characteristics.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법은 단위 소자가 형성된 하지층 상에 층간 절연막을 형성하는 단계; 상기 층간 절연막 상에 금속계 물질층을 형성하는 단계; 상기 금속계 물질층 상에 콘택이 형성될 부분이 개방된 포토레지스트 마스크층을 형성하는 단계; 상기 포토레지스트 마스크층을 이용한 식각 공정으로 상기 금속계 물질층을 식각하여 콘택이 형성될 부분이 개방된 금속계 마스크층을 형성하는 단계; 상기 포토레지스트 마스크층을 제거하는 단계; 상기 금속계 마스크층을 이용한 콘택 식각 공정으로 상기 층간 절연막의 일부분을 제거하여 상기 하지층이 노출된 콘택홀을 형성하는 단계; 및 상기 금속계 마스크층을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method including: forming an interlayer insulating film on a base layer on which a unit device is formed; Forming a metal material layer on the interlayer insulating film; Forming a photoresist mask layer on which the contact is to be formed on the metal material layer; Etching the metal-based material layer by an etching process using the photoresist mask layer to form a metal-based mask layer in which a portion where a contact is to be formed is opened; Removing the photoresist mask layer; Forming a contact hole exposing the underlying layer by removing a portion of the interlayer insulating layer by a contact etching process using the metal mask layer; And removing the metal mask layer.
도 1a 내지 도 1c는 종래 반도체 소자의 콘택 형성 방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 하지층12, 22: 층간 절연막11, 21: base layer 12, 22: interlayer insulating film
13, 23: 포토레지스트 마스크층13a, 23a: 잔류 마스크층13, 23: photoresist mask layer 13a, 23a: residual mask layer
14, 24: 콘택홀200: 금속계 물질층14 and 24: contact hole 200: metal-based material layer
200a: 금속계 마스크층200a: metal mask layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for describing a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 단위 소자가 형성된 하지층(21) 상에 층간 절연막(22)을 형성한다. 층간 절연막(22) 상에 금속계 물질층(200)을 형성한다. 금속계 물질층(200) 상에 콘택이 형성될 부분이 개방된(open) 포토레지스트 마스크층(23)을 형성한다.Referring to FIG. 2A, an interlayer insulating layer 22 is formed on the base layer 21 on which the unit elements are formed. The metal material layer 200 is formed on the interlayer insulating layer 22. A photoresist mask layer 23 is formed on the metal-based material layer 200 to open a portion where a contact is to be formed.
상기에서, 금속계 물질층(200)은 알루미늄, 텅스텐, 코발트 등과 같은 금속계 물질을 화학기상증착법이나 물리기상증착법으로 10 ∼ 10000Å 범위로 증착하여 형성한다.In the above, the metal-based material layer 200 is formed by depositing a metal-based material such as aluminum, tungsten, cobalt, etc. in the range of 10 to 10000 Pa by chemical vapor deposition or physical vapor deposition.
한편, 금속계 물질층(200)과 층간 절연막(22)과의 접촉성을 향상시키기 위하여 금속계 물질층(200)을 형성하기 전에 층간 절연막(22) 상에 Ti와 같은 접착층(glue layer)을 형성할 수도 있다. 금속계 물질층(200)의 금속 이온이 하부층인 층간 절연막(22)으로 확산되는 것을 방지하기 위하여 금속계 물질층(200)을 형성하기 전에 층간 절연막(22) 상에 TiN과 같은 확산 방지층(diffusion barrier layer)을 형성할 수도 있다. 후속 노광 장비의 난반사 문제를 위하여 금속계 물질층(200)을 형성한 후에 TiN과 같은 난반사 방지층을 형성할 수 있다.In order to improve contact between the metal-based material layer 200 and the interlayer insulating film 22, a glue layer such as Ti may be formed on the interlayer insulating film 22 before the metal-based material layer 200 is formed. It may be. In order to prevent the metal ions of the metal-based material layer 200 from being diffused into the lower interlayer insulating film 22, a diffusion barrier layer such as TiN is formed on the interlayer insulating film 22 before the metal-based material layer 200 is formed. ) May be formed. After forming the metal-based material layer 200 for a problem of diffuse reflection of the subsequent exposure equipment, a diffuse reflection prevention layer such as TiN may be formed.
도 2b를 참조하면, 포토레지스트 마스크층(23)을 이용한 식각 공정으로 금속계 물질층(200)의 일부분을 제거하여 콘택이 형성될 부분이 개방된 금속계 마스크층(200a)을 형성한다. 금속계 마스크층(200a)이 패터닝 되는 동안 포토레지스트 마스크층(23)은 일정 두께 제거되어 잔류 마스크층(23a)으로 남게된다.Referring to FIG. 2B, a portion of the metal-based material layer 200 is removed by an etching process using the photoresist mask layer 23 to form a metal mask layer 200a having an open portion where a contact is to be formed. While the metal mask layer 200a is patterned, the photoresist mask layer 23 is removed to a certain thickness to remain as the residual mask layer 23a.
상기에서, 금속계 물질층(200)의 식각 공정은 주 식각 공정과 과도 식각 공정으로 진행하는데, 과도 식각 공정은 주 식각 공정 시간에 대하여 1 ∼ 300％ 범위로 진행한다.In the above, the etching process of the metal-based material layer 200 proceeds to the main etching process and the transient etching process, the excessive etching process proceeds in the range of 1 to 300% with respect to the main etching process time.
도 2c를 참조하면, 잔류 마스크층(23a)을 포토레지스트 제거 공정으로 제거한 후, 금속계 마스크층(200a)을 이용한 콘택 식각 공정으로 층간 절연막(22)의 일부분을 제거하여 하지층(21)이 노출된 콘택홀(24)을 형성한다.Referring to FIG. 2C, after removing the residual mask layer 23a by a photoresist removing process, a portion of the interlayer insulating layer 22 is removed by a contact etching process using the metal mask layer 200a to expose the underlying layer 21. Contact holes 24 are formed.
상기에서, 콘택홀 형성을 위한 콘택 식각 공정은 주 식각 공정과 과도 식각 공정으로 진행하는데, 과도 식각 공정은 주 식각 공정 시간에 대하여 1 ∼ 300％ 범위로 진행한다.In the above, the contact etching process for forming the contact hole proceeds to the main etching process and the transient etching process, the excessive etching process proceeds in the range of 1 to 300% with respect to the main etching process time.
도 2d를 참조하면, 금속계 마스크층(200a)을 제거하고, 이로 인하여 콘택홀(24) 형성이 완료된다.Referring to FIG. 2D, the metal mask layer 200a is removed, thereby completing the formation of the contact hole 24.
상기와 같이 금속계 물질을 콘택 마스크층으로 이용할 경우 일렉트론 쉐딩 이펙트(electron shading effect)가 발생되지 않아 일렉트론 쉐딩 이펙트에 의한 하부 소자의 마이크로트렌칭(microtrenching) 현상과 플라즈마 인듀스드-챠징 데미지(plasma induced-charging damage)의 개선으로 콘택홀(24)의 형상이 양호하게 될 뿐만 아니라 소자의 전기적 특성 또한 증가하게 되는데, 이를 설명하면 다음과 같다.As described above, when the metal material is used as the contact mask layer, the electron shading effect does not occur, and thus, microtrenching and plasma induced-charging damage of the lower device due to the electron shading effect are caused. In addition, the shape of the contact hole 24 is not only improved by improving the charging damage, but also the electrical characteristics of the device are increased.
금속계 마스크층을 이용한 콘택 식각 공정에서 플라즈마 콘택 식각 공정중, 금속계 마스크층에 대한 일렉트론/이온의 챠징 현상은 포토레지스트 마스크층 경우와 같이 서페이스 챠징(Surface Charging) 형태로 발생하는 것이 아니라 전도체 내부의 미세한 포텐셜(Potential) 증가를 유발함으로서 포토레지스트 마스크층의 경우와 같은 일렉트론 쉐딩 이펙트(Electron Shading Effect)는 발생하지 않는다. 그러므로 마이크로트렌칭(Microtrenching) 현상 유발 메커니즘(Mechanism) 중 일렉트론 쉐딩 이펙트에 의한 이온 궤도 변곡 현상이 억제된다.Contact etching process using metal mask layer During the plasma contact etching process, the charging phenomenon of the electrons / ions to the metal mask layer does not occur in the form of surface charging as in the case of the photoresist mask layer. By inducing potential increase, the Electron Shading Effect as in the case of the photoresist mask layer does not occur. Therefore, the ion orbital inflection caused by the electron shedding effect of the microtrenching phenomenon inducing mechanism is suppressed.
포토레지스트 마스크층을 이용하는 금속계 물질층의 식각 공정에서의 일렉트론 쉐딩 이펙트(Electron Shading Effect)는 하부가 절연층이고 금속계 물질층의 두께에 대한 과도 식각만 진행되므로 유의할 수준의 마이크로트렌칭 현상은 발생하지 않는다.In the etching process of the metal material layer using the photoresist mask layer, the electron shading effect has no significant micro-trenching phenomenon because the lower portion is an insulating layer and only the excessive etching of the thickness of the metal material layer is performed. Do not.
기존 포토레지스트 마스크층의 경우, 하부 절연층에 대한 포토레지스트의 저 선택비 특성으로 ∼ 10000Å 두께의 포토레지스트 마스크층을 이용하여 콘택 식각 공정을 진행함으로서 높은 애스펙트 비(Aspect Ratio)에 의한 이온/라디컬(Ion/Radical)의 산란 효과(Scattering Effect)에 의한 마이크로트렌칭의 유발과 반도체 소자의 직접도 증가에 의한 콘택 사이즈(Contact Size)의 감소로 콘택홀 내부로의 원활한 식각제(Etchant) 공급과 방출이 제한되어 식각 정지(Etch Stop)등의 공정 이상이 발생하였으나, 금속계 마스크층의 고선택비 특성으로 애스펙트 비가 감소하여, 마이크로트렌칭 현상의 감소 및 식각 정지 등의 공정 이상에대한 공정 마진이 증가된다. 그리고, 하부 12500Å 절연층에 대한 콘택 식각 공정후 금속계 마스크층의 식각 손실은 발생하지 않는다. 이는 금속계 마스크층이 산화물계 층간 절연막과의 선택비가 무한대에 가까운 것으로 판단된다.In case of the existing photoresist mask layer, the contact etching process is performed using a photoresist mask layer having a thickness of ˜10000 Å with a low selectivity ratio of the photoresist with respect to the lower insulating layer, thereby resulting in a high aspect ratio. Supply of etchant to the inside of the contact hole by the micro trenching by the scattering effect of ion / radical and the decrease of the contact size due to the increase of the directivity of the semiconductor device Due to the limited emission, process abnormalities such as etch stop occurred, but due to the high selectivity characteristics of the metal mask layer, the aspect ratio decreased, resulting in a reduction in micro trenching phenomenon and process margins for process abnormalities such as etch stop. Is increased. The etching loss of the metal mask layer does not occur after the contact etching process with respect to the lower 12500 Å insulating layer. It is determined that the selectivity ratio of the metal mask layer to the oxide-based interlayer insulating film is close to infinity.
콘택 주 식각 공정 완료 후 하부 단위소자가 노출된 상태에서 진행되어 지는 과도 식각 공정중 발생하는 플라즈마 인듀스드-챠징 데미지는 포토레지스트 마스크층의 일렉트론 쉐딩 이펙트에 의한 이온의 하부 단위소자 전하축적 현상과, 식각 공정 장비의 플라즈마 불균일성에 의하여 발생하는데, 금속계 마스크층을 이용한 콘택 식각 공정의 경우에는 상술하였듯이 일렉트론 쉐딩 이펙트가 발생하지 않으므로 일렉트론과 이온 모두 하부 단위소자의 축적 현상에 참여하므로, 하부 단위소자의 전하축적 현상은 플라즈마의 불균일성과 무관하게 일렉트론과 이온 챠징에 의한 전기적 감쇄 효과가 발생하여 플라즈마 인듀스드-챠징 데미지(Plasma Induced-Charging Damage)는 감소하게 된다.Plasma induced-charging damage that occurs during the transient etching process in which the lower unit device is exposed after completion of the contact main etching process is caused by the charge accumulation phenomenon of the lower unit device due to the electron shedding effect of the photoresist mask layer. , Due to the plasma non-uniformity of the etching process equipment. In the case of the contact etching process using the metal mask layer, as described above, since the electron shedding effect does not occur, both electrons and ions participate in the accumulation of the lower unit devices. The charge accumulation phenomenon causes the electrical attenuation effect by the electron and ion charging regardless of the plasma non-uniformity, thereby reducing the plasma induced-charging damage.
상술한 바와 같이, 본 발명에서는 기존 콘택 형성 공정의 절연체 포토레지스트 마스크를 일렉트론 서페이스 챠징이 발생하지 않는 전도체인 금속계 마스크층으로 대체함으로서, 일렉트론 쉐딩 이펙트에 의한 하부소자의 마이크로트렌칭과 플라즈마 인듀스드-챠징 데미지를 개선할 수 있고, 금속계 마스크층의 산화막에 대한 고선택비 특성으로 기존 포토레지스트 마스크층을 이용한 콘택 식각 공정기술의 산화물에 대한 포토레지스트 선택성(PR Selectivity to Oxide) 문제의 해결과 콘택공정의 애스펙트 비를 감소시키는 효과가 있다.As described above, in the present invention, by replacing the insulator photoresist mask of the existing contact forming process with a metal mask layer, which is a conductor that does not generate electrosurface charging, micro-trenching and plasma-induced lower devices by the electro-shedding effect. -The charging damage can be improved, and the high selectivity ratio of the oxide layer of the metal mask layer solves the problem of photoresist selectivity to oxide of the contact etching process technology using the existing photoresist mask layer and contacts. It has the effect of reducing the aspect ratio of the process.
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