KR20030057862A - Method for etching a storage node contact of semiconductor device - Google Patents

Abstract

PURPOSE: A method for etching a storage node contact of a semiconductor memory device is provided to be capable of previously preventing the etching failure of a contact hole by carrying out a multi-step etching process. CONSTITUTION: A bit line pattern and the first interlayer dielectric(30) are formed at the upper portion of a semiconductor substrate(10) having a predetermined lower structure. After forming an etch stop layer(40) on the resultant structure, the second interlayer dielectric(50) is formed on the upper portion of the etch stop layer. The second interlayer dielectric is etched by carrying out an etching process using a contact mask as an etching mask. The etch stop layer and the first interlayer dielectric are etched to a predetermined depth. The first interlayer dielectric is etched for being self-aligned to the bit line pattern.

Description

Method for etching a storage node contact of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a contact etching method for a storage node electrode of a semiconductor memory device capable of preventing etching irregularities of a multilayer interlayer insulating layer for each wafer region.

In order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, since the area of the capacitor decreases rapidly as the integration of semiconductor devices increases, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be further increased.

To this end, a storage node electrode having a three-dimensional structure that can increase an effective area of a capacitor has been applied. However, in the highly integrated semiconductor memory device, since the high aspect ratio and the space margin between the capacitors are smaller, the three-dimensional structure, for example, in the case of manufacturing a cylindrical capacitor, sacrificial insulating film deposition, opening etching, conductive film deposition and etching A sacrificial insulating film removal process is required.

On the other hand, the manufacturing process of the conventional cylindrical or stacked storage node electrode generally forms a contact hole in an interlayer insulating film in a semiconductor substrate, forms a contact by filling a conductive film in the contact hole, forms a sacrificial insulating film thereon, and photographs and etching processes. An opening is formed in the sacrificial insulating film to secure the pattern region of the storage node electrode. Then, a doped polysilicon is deposited as a conductive film over the entire sacrificial insulating film having an opening, and the polysilicon on the surface of the sacrificial insulating film is removed by a chemical mechanical polishing process, followed by a wet etching process to remove the sacrificial insulating film to form a cylinder or a stack. The storage node electrode is formed.

However, the contact for the storage node electrode according to the prior art is multilayered with the first interlayer insulating film, the etch stop film, and the second interlayer insulating film, as shown in FIG. 2, rather than a single interlayer insulating film due to the high integration of the device. In FIG. 2, reference numeral 10 is a semiconductor substrate, 20 is a bit line including a conductive film 22, a hard mask 24, and a spacer 26, 30 is a first interlayer insulating film, 40 is an etch stop film, and 50 is a second. The interlayer insulating film 60 is a photoresist pattern.

Referring to FIG. 2 in more detail, a manufacturing process for a contact for a storage node electrode of the prior art is as follows. A normal wiring process is performed on the semiconductor substrate 10 to form a bit line 20, and thereon, a first interlayer insulating layer 30 is formed on the lower structure of the semiconductor substrate, and the etch stop is nitrided thereon. The film 40 is formed. In addition, a second interlayer insulating layer 50 is deposited on the etch stop layer 40. Next, a photoresist using a contact mask is performed to form a photoresist pattern 60 on the second interlayer insulating film 50.

3A and 3B, the dry etching process using the photoresist pattern 60 is performed to etch the second interlayer insulating film 50, the etch stop layer 40, and the first interlayer insulating film 30. To form (70, 80). Then, the doped polysilicon is buried in the structure in which the contact hole is formed and planarized to form the storage node contact.

As described above, in the prior art, it is more difficult to form the contact hole by etching the second interlayer insulating film, the etch stop film, and the first interlayer insulating film of a multilayer structure than by etching the single interlayer insulating film in one etching apparatus.

3A and 3B illustrate etching steps between wafer regions by a contact etching method for a storage node electrode of a semiconductor memory device according to the related art. Referring to this, in the conventional contact etching method, an etching step occurs between the wafer center area A and the wafer edge area B. FIG. That is, due to the multi-layer structure of the second interlayer insulating film 50, the etch stop film 40, and the first interlayer insulating film 30 and the characteristics of the etching equipment, the etching speed on the wafer edge side drops sharply, resulting in uneven contact hole etching speed between regions. Will cause. As a result, due to the difference in etching speed between the wafer center area A and the wafer edge area B, the contact hole 70 of the wafer center area A is etched up to the first interlayer insulating film 30, but the wafer edge area B is etched. ), The first interlayer insulating film 30 is left without being etched.

Therefore, in the related art, since the contact hole etching process of the second interlayer insulating film 50, the etch stop film 40, and the first interlayer insulating film 30 is performed in one etching process, the wafer center region A and the wafer edge region are processed. Due to the difference in etching speed between (B), the first interlayer insulating film 30 in the wafer edge region B remained in the storage node contact hole without being etched (FIGS. 1A and 1B). The wafer edge insulating film remaining in the storage node contact hole eventually acts as a factor that hinders the electrical characteristics of the device.

An object of the present invention is to etch a wafer center region and an edge region when forming a storage node electrode contact hole in a multilayer structure of a first interlayer insulating film, an etch stop film, and a second interlayer insulating film in order to solve the above problems of the prior art. The present invention provides a contact etching method for a storage node electrode of a semiconductor memory device capable of preventing contact hole etching defects caused by a slow etching speed at a wafer edge by considering a speed difference.

1A and 1B illustrate etching residues generated during etching of a contact for a storage node electrode according to the prior art;

2 is a vertical cross-sectional view of a structure for forming a contact for a storage node electrode of a general semiconductor memory device;

3A and 3B illustrate etching steps between wafer regions by a contact etching method for a storage node electrode of a semiconductor memory device according to the related art;

4A to 4C are views for explaining a contact etching method for a storage node electrode of a semiconductor memory device according to the present invention;

5a to 5c are views showing the contact form for the storage node electrode by the etching process according to the present invention.

* Description of the symbols for the main parts of the drawings *

10 semiconductor substrate 20 bit line

30: first interlayer insulating film 40: etch stop film

50: second interlayer insulating film 60: photoresist pattern

70 ', 80': Wafer center and edge side contact holes

In order to achieve the above object, the present invention provides a method of contact etching an electrode of a storage node of a semiconductor memory device, the method comprising: forming a bit line and a first interlayer dielectric layer on a lower structure of a semiconductor substrate, and stopping the etching on the first interlayer dielectric layer Forming a film, forming a second interlayer insulating film on the etch stop film, etching the second interlayer insulating film by using a contact mask on the second interlayer insulating film, and etching the second interlayer insulating film. Etching the interlayer insulating film to a predetermined depth; etching the first interlayer insulating film so as to self-align to the bit line pattern; and etching the contact hole in which the second interlayer insulating film, the etch stop film, and the first interlayer insulating film are etched. And performing post-treatment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4C are views for explaining a contact etching method for a storage node electrode of a semiconductor memory device according to the present invention.

First, as shown in FIG. 2, a normal wiring process is performed on the semiconductor substrate 10 to form a bit line 20, and a first interlayer insulating layer 30 serving as an insulating layer on the lower structure of the semiconductor substrate is formed thereon. And an etch stop film 40 is formed thereon from nitride. In addition, a second interlayer insulating layer 50 is deposited on the etch stop layer 40. Next, a photoresist using a contact mask is performed to form a photoresist pattern 60 on the second interlayer insulating film 50.

Although the present invention is not shown in the drawings, an anti-reflection film may be further formed on the second interlayer insulating film 50. In this case, when the anti-reflection film is etched using the photoresist pattern 60, for example, the pressure of the reaction chamber should be performed at 100 mTorr or less, the power of the electrode does not exceed 2000W, and the temperature of the electrode is adjusted to 0 ° C. to 80 ° C. In addition, an etching gas obtained by mixing CF 4 and Ar in a ratio of about 1: 2 is used, and the mixing amount of the entire etching gas is within 300 sccm. At this time, if 02 gas is used additionally, O2 gas is within 50sccm.

Then, as shown in FIG. 4A, the dry etching process using the photoresist pattern 60 is performed to etch the second interlayer insulating film 50, and the etch stop layer 40 is used as an etching target. As a result, the etching thickness of the second interlayer insulating layer 50 is substantially the same in the wafer center region A and the wafer edge region B. FIG. For example, in the etching process of the etch stop film 40, the pressure of the reaction chamber proceeds at 80 mTorr or less, and the temperature of the electrode is adjusted to 30 to 80 ° C. without exceeding 2000 W of power. And the etching gas used is C4F8 and CH2F2 can be used in a mixture of about 2: 1 ratio. At this time, the total mixing amount of C4F8 and CH2F2 gas is within 600sccm, and when Ar gas is added, the Ar gas is within 500sccm.

Subsequently, as shown in FIG. 4B, the etch stop layer 40 and the first interlayer insulating layer 30 are etched to a predetermined depth. For example, in the etching process, the pressure of the reaction chamber is performed at 100 mTorr or less, and the temperature of the electrode is adjusted to 30 ° C. to 80 ° C. without exceeding 2000 W of power. The etching gas used here may be CF4 and Ar, wherein CF4 and Ar are mixed at a ratio of about 1: 2 and the total mixing amount is less than 250sccm.

Although not shown in the drawing, the first interlayer insulating layer 30 is etched to self-align the bit line pattern to form the contact holes 70 'and 80' for the storage node electrodes. As described above, since the thickness of the first interlayer insulating film 30 remains uniform in the wafer center region A and the wafer edge region B after the etching stop film 40 is etched, the first interlayer insulating film 30 is removed. When etching to self-align the bit line, the first interlayer insulating layer 30 in the wafer center region A and the wafer edge region B may be uniformly etched.

For example, in the etching process of the first interlayer insulating film 30, the pressure of the reaction chamber is advanced at 80 mTorr or less, and the temperature of the electrode is adjusted to 30 ° C. to 80 ° C. without exceeding 2000 W of power. In addition, the etching gas used may be C4F8 and CH2F2, and the mixture is used in a ratio of about 2: 1, and the total mixing amount of the C4F8 and CH2F2 gas is within 600 sccm. At this time, when mixing the Ar gas to less than 500sccm.

Subsequently, as shown in FIG. 4C, the etching post-treatment is performed on the contact holes 70 'and 80' on which the second interlayer insulating film 50, the etch stop film 40 and the first interlayer insulating film 30 are etched. The first interlayer insulating film 30 remaining in the contact hole 80 'of the wafer edge region B is etched away due to the difference in etching speed between the wafer center region A and the wafer edge region B. .

Finally, the etching post-treatment process proceeds at a pressure of the reaction chamber below 80mTorr, and controls the temperature of the electrode to 30 ℃ ~ 80 ℃ without exceeding the power 1000W. In addition, the etching gas used may be Ar and O 2, and the mixture is used in a ratio of about 1: 2. At this time, the total mixing amount of Ar and O 2 gas is within 400 sccm.

In the manufacturing method of the present invention, in the contact hole etching process of the antireflection film, the second interlayer insulating film 50 to the first interlayer insulating film 30, the pressure of the reaction chamber is 1 mTorr to 1000 mTorr and the RF power is 100 W to 3000 W.

In the etching process and the post-treatment etching process of the anti-reflection film, the anti-etching film 40 and the first interlayer insulating film 30 according to the present invention, an etching gas of CF 4 and Ar is used, wherein the ratio of CF 4: Ar is 1:10. Let it be 10: 1. And when O2 gas is added to this process, the ratio of O2 gas shall be 10%-100% with respect to all CF4 and Ar gas.

In addition, according to the present invention, the process of etching the first interlayer insulating film 30 so as to self-align with the second interlayer insulating film 50 uses an etching gas of CxFy and CH2F2, wherein the ratio of CxFy: CH2F2 is 1:10. Set the ratio to 10: 1 and set the x / y ratio of CxFy to 0.5 to 1. And when O2 gas is added to this process, the ratio of O2 gas shall be 10%-100% with respect to all CxFy and CH2F2 etching gas.

CxFy may be any one of C4F8, C5F8, and C4F6.

In addition, the present invention uses helium (He) gas during the etching process and the post-treatment process of the anti-reflection film, the second interlayer insulating film 50 to the first interlayer insulating film 30, the helium gas is 40 Torr or less. At this time, the helium pressure of the wafer center and the wafer shell are differently adjusted.

As described above, when the second interlayer insulating film 50, the etch stop layer 40, and the first interlayer insulating film 30 are etched in various steps, the etching speed difference between the wafer center region A and the wafer edge region B is different. As a result, since the first interlayer insulating film 30 remaining in the contact hole 80 'of the wafer edge region B can be etched and removed, a good storage node contact hole (as shown in FIGS. 5A to 5C) can be removed. 70 ', 80') profiles.

As described above, the present invention is capable of fully etching the multilayer insulating film and the etch stop film in both the wafer center region and the wafer edge region by implementing the etching conditions of various steps to have a uniform etching rate regardless of the etching rate characteristic of the equipment. have. That is, the present invention proceeds a multi-step etching process in consideration of the difference in etching speed between the wafer center region and the edge region when forming the storage node electrode contact hole in the multilayer structure of the first interlayer insulating film, the etch stop film and the second interlayer insulating film. As a result, contact hole etching defects caused by a lower etching speed at the wafer edge than the wafer center can be prevented in advance, thereby stabilizing electrical characteristics of the semiconductor device and improving semiconductor yield.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (17)

In the contact etching method of the storage node electrode of the semiconductor memory device, Forming a bit line and a first interlayer dielectric layer on a lower structure of the semiconductor substrate; Forming an etch stop layer on the first interlayer insulating layer; Forming a second interlayer insulating layer on the etch stop layer; Etching the second interlayer insulating layer by performing an etching process using a contact mask on the second interlayer insulating layer; Etching the etch stop layer and the first interlayer insulating layer to a predetermined depth; Etching the first interlayer insulating layer so as to self-align with the bit line pattern; And And performing post-etching on the contact holes etched with the second interlayer insulating film, the etch stop film, and the first interlayer insulating film. 2. The method of claim 1, further comprising forming an anti-reflection film on the second interlayer insulating film. The method of claim 2, wherein the anti-reflection film is etched at a pressure of 100 mTorr or less, at an RF power of 2000 W or less, and at 300 sccm in which CF4 and Ar are mixed at an electrode temperature of 0 to 80 ° C in a ratio of 1: 2. A contact etching method for a storage node electrode of a semiconductor memory device, characterized in that it proceeds within the mixed etching gas. 4. The method of claim 3, wherein an O 2 gas is added during the etching process and the O 2 gas is within 50 sccm. 5. The etching process of claim 1, wherein the etching process of the second interlayer dielectric layer comprises mixing C4F8 and CH2F2 in a ratio of 2: 1 at an electrode temperature of 30 ° C. to 80 ° C., at an RF power of 2000 W or less at a pressure of 80 mTorr or less. A contact etching method for a storage node electrode of a semiconductor memory device, characterized in that it proceeds with a mixed etching gas within 600sccm. The method of claim 5, wherein the Ar gas is added during the etching process and the Ar gas is within 500 sccm. The etching process according to claim 1, wherein the etching process of etching the etch stop layer and the first interlayer insulating layer to a predetermined depth comprises: CF4 and an electrode temperature in a range of 30 ° C. to 80 ° C. with RF power of 2000 W or less at a pressure of 100 mTorr or less. A contact etching method for a storage node electrode of a semiconductor memory device, characterized by advancing a mixed etching gas within 250sccm in which Ar is mixed at a ratio of 1: 2. The method of claim 1, wherein the etching process of etching the first interlayer insulating film so as to self-align the bit line pattern comprises C4F8 at an electrode temperature of 30 ° C. to 80 ° C. with an RF power of 2000 W or less at a pressure of 80 mTorr or less. And a etch gas within 600 sccm of CH 2 F 2 mixed at a ratio of 2: 1. The contact etching method for a storage node electrode of a semiconductor memory device. The method of claim 8, wherein the Ar gas is added during the etching process and the Ar gas is within 500 sccm. The method of claim 1, wherein the etching post-treatment is performed within 400 sccm of a mixture of Ar and O2 in a ratio of 1: 2 in an electrode temperature of 30 ° C. to 80 ° C. and an RF power of 1000 W or less at a pressure of 80 mTorr or less. A contact etching method for a storage node electrode of a semiconductor memory device, characterized in that it proceeds with a mixed etching gas. The etching process and the post-treatment etching process of the anti-reflection film, the etch stop film, and the first interlayer insulating film use an etching gas of CF4 and Ar, and the ratio of CF4: Ar is 1:10 to 10: 1. The contact etching method for a storage node electrode of a semiconductor memory device, characterized in that. 12. The method of claim 11, wherein an O2 gas is added during the etching process, and the ratio of the O2 gas is 10% to 100% of the total gas. The method of claim 1, wherein the etching of the first interlayer insulating layer so as to self-align the second interlayer insulating layer is performed using an etching gas of CxFy and CH2F2 and the ratio of CxFy: CH2F2 to 1:10 to 10: 1. A contact etching method for a storage node electrode of a semiconductor memory device, characterized in that the. The method of claim 13, wherein the x / y ratio of CxFy in the etching gas is 0.5 to 1. 15. 15. The method of claim 13, wherein during the etching process, O2 gas is added and the ratio of O2 gas is 10% to 100% of the total etching gas. The contact etching method of claim 2, wherein helium gas is used in the etching process and the post-treatment process of the anti-reflection film, the second interlayer insulating film to the first interlayer insulating film. 17. The method of claim 16, wherein the helium gas is at a pressure of 40 Torr or less, and the helium pressure of the center of the wafer and the outside of the wafer is differently controlled.