KR20030056920A - Method for testing a semiconductor memory device - Google Patents

Abstract

PURPOSE: A test method of a semiconductor memory device is provided to be capable of measuring exactly diverse measurement values by using a dummy cell having same condition to a cell. CONSTITUTION: In a test method of a semiconductor memory device, a dummy cell(305) is connected to dummy bit lines(DBL1,DBL2) by forming a contact in the dummy cell. The dummy bit lines(DBL1,DBL2) are connected to probe pads(308,310), respectively. After performing a desired test to the semiconductor memory device, the test result is measured by using the probe pads(308,310).

Description

Test method of semiconductor memory device {METHOD FOR TESTING A SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor memory device, and more particularly, to a test method for a semiconductor memory device capable of measuring various measurement values for a memory cell under the same conditions as in operation of a memory device.

As the memory process becomes smaller and smaller, the capacitance problem between the parts constituting the memory becomes more serious. Therefore, it is necessary to examine closely the coupling capacitance between the bit line and the bit line, the capacitance of the cell capacitor, and the effect on the bit line when the word line is turned on. However, such a review has not been made so far for cell mats, but is made by measuring a test pattern implemented separately and inferring the actual cell.

1 is a diagram illustrating a conventional semiconductor memory device test method. In FIG. 1, 102 denotes a cell mat and 104 denotes a dummy cell portion. WL indicates a word line, DWL indicates a dummy word line, BL indicates a bit line, DBL indicates a dummy bit line, and CLi indicates a column select signal. As shown in FIG. 1, the test pattern 106 is implemented separately from the cell mat 102. The test pattern 106 is typically designed to be larger than the actual cell for measurement of the test value and is connected to an external test device (not shown) via the pads 108 and 110. In this configuration, a certain test condition is applied, the characteristic value of the test pattern 106 is measured through the pads 108 and 110, and the characteristic of the actual cell is considered in consideration of the test pattern 106 and the size of the actual cell. Infer the value. However, this method is fundamentally inaccurate because it is not done directly to the cell mat.

SUMMARY OF THE INVENTION The present invention has been proposed to solve such a problem, and an object of the present invention is to provide a test method of a semiconductor memory device capable of measuring various measurement values of a memory cell under the same conditions as in operation of a memory device.

1 is a diagram illustrating a conventional semiconductor memory device test method.

2 illustrates a core of a conventional semiconductor memory device.

3 is a configuration diagram of a semiconductor memory device in which a test method according to an embodiment of the present invention is implemented.

4 illustrates a layout of a semiconductor memory device in which a test method according to an embodiment of the present invention is implemented.

In accordance with another aspect of the present invention, a method of testing a semiconductor memory device includes: forming a contact in a dummy cell and connecting the dummy bit line to the dummy bit line, connecting the dummy bit line to a probe pad; And performing a predetermined test on the semiconductor memory device and measuring a test result through the probe pad.

According to another aspect of the present invention, there is provided a method of testing a semiconductor memory device, the method comprising: forming a contact in a dummy cell and connecting the dummy word line to the dummy word line, connecting the dummy word line to a probe pad; And performing a predetermined test on the test pad and measuring a test result through the probe pad.

In addition, the present invention is a semiconductor memory device having a configuration that is easy to test a memory cell, a dummy cell, a dummy bit line connected through the contact with the dummy cell, and a probe pad electrically connected to the dummy bit line It is another feature to provide a pad).

In addition, the present invention is a semiconductor memory device having a configuration that can be easily tested for a memory cell, comprising a dummy cell, a dummy word line connected through contact with the dummy cell, and a probe pad electrically connected to the dummy word line. It is another feature to do.

According to the configuration of the present invention, by performing a number of tests using a dummy cell having almost the same conditions as the actual cell, it is possible to measure various characteristic values for the actual cell very accurately.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

FIG. 2 is a diagram illustrating a core of a conventional semiconductor memory device, in which FIG. 2A is a conventional circuit diagram, FIG. 2B is a three-dimensional diagram of the circuit of FIG. 2A, and FIG. 2C is a layout. As shown in FIG. 2, the cell mat of the semiconductor memory device is provided with a dummy pattern at the periphery so as to match the step between the peripheral circuit and the cell mat. The dummy pattern includes a dummy word line DWL, a dummy bit line DBL, and a dummy cell 202. On the other hand, the real cell 204 has a real word line WL and a real bit line BL. In FIG. 2C, 206 corresponds to a dummy cell and 208 corresponds to an actual cell.

3 is a configuration diagram of a semiconductor memory device in which a test method according to an embodiment of the present invention is implemented. As shown in FIG. 3, the cell mat 302 includes a real cell portion 303 having a real word line WL and a real bit line BL, a dummy word line DWL and a dummy bit line ( Divided into a dummy cell portion 305 having a DBL). The original dummy cell portion 305 is implemented around the actual cell portion 303 to fill the process step between the cell mat 302 and the peripheral circuit (not shown), as described above. In this case, the dummy cell portion 305 is designed on the layout under almost the same conditions as the actual cell portion 303. The data stored in the actual cell portion 303 is output as the data signal DQ via the bit line BL and the multiplexer 306 when the sense amplifier 304 is enabled by activation of the column select signal CLi. do.

As shown in FIG. 3, the dummy cell 305a is electrically connected to the dummy bit line DBL. In an actual process, a contact is formed in the dummy cell 305a and connected to the dummy bit line DBL. In FIG. 3, the dummy bit line DBL2 is electrically connected to the probe pad 308 via the wire 312 and to the probe pad 310 via the wire 314. Although the dummy bit line DBL is electrically connected to the probe pads 308 and 310 in the present embodiment, the dummy word line DWL may be electrically connected to the probe pads 308 and 310 for other purposes. have.

As described above, the dummy cell 305a is electrically connected to the dummy bit line DBL and enters an existing test pattern, for example, an all word line enable pattern, and probe pads 308 and 310. The characteristic value of the actual cell portion 303 is also found by measuring the voltage or current applied to the dummy bit line DBL and finding the characteristic value of the dummy cell portion 305. Another test may be performed while the dummy word line DWL is connected to the probe pads 308 and 310.

FIG. 4 is a diagram illustrating a layout of a semiconductor memory device in which a test method according to an embodiment of the present invention is implemented. 4 illustrates a case in which the dummy word line DWL1 is electrically connected to the pad 408 through the wire 412, and the dummy bit line DBL2 is electrically connected to the pad 410 through the wire 414. . In FIG. 4, 402 denotes a dummy cell, 404 denotes a contact formed between the dummy cell 402 and the dummy bit line DBL2, and 406 denotes an electrical connection between the dummy word line DWL1 and the wire 412. Point out each part. And 416 is a test circuit that implements the entire word line enable pattern.

The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

According to the configuration of the present invention, rather than inferring the actual cell as a measurement value for the test pattern implemented separately as in the prior art, by performing several tests using a dummy cell having almost the same conditions as the actual cell Various characteristic values for a cell can be measured very accurately.

Claims (4)

In the test method of a semiconductor memory device, Forming a contact in the dummy cell and connecting the dummy cell to the dummy bit line; Coupling the dummy bit line to a probe pad; Performing a predetermined test on the semiconductor memory device and measuring a test result through the probe pad Test method characterized in that it comprises. In the test method of a semiconductor memory device, Forming a contact in the dummy cell and connecting the dummy cell to the dummy bit line; Connecting the dummy word line to a probe pad; Performing a predetermined test on the semiconductor memory device and measuring a test result through the probe pad Test method characterized in that it comprises. A semiconductor memory device having a configuration in which a test for a memory cell is easy, With dummy cells, A dummy bit line connected through the contact with the dummy cell; A probe pad electrically connected to the dummy bit line A semiconductor memory device, characterized in that provided. A semiconductor memory device having a configuration in which a test for a memory cell is easy, With dummy cells, A dummy bit line connected through the contact with the dummy cell; A probe pad electrically connected to the dummy word line A semiconductor memory device, characterized in that provided.