KR20030054178A - A method for froming barrier metal layer of semiconductor device - Google Patents
A method for froming barrier metal layer of semiconductor device Download PDFInfo
- Publication number
- KR20030054178A KR20030054178A KR1020010084302A KR20010084302A KR20030054178A KR 20030054178 A KR20030054178 A KR 20030054178A KR 1020010084302 A KR1020010084302 A KR 1020010084302A KR 20010084302 A KR20010084302 A KR 20010084302A KR 20030054178 A KR20030054178 A KR 20030054178A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- metal layer
- thin film
- barrier metal
- metal wiring
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 57
- 239000002184 metal Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000004888 barrier function Effects 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010409 thin film Substances 0.000 claims description 25
- 239000010408 film Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 28
- 239000011229 interlayer Substances 0.000 abstract description 8
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 229910052715 tantalum Inorganic materials 0.000 abstract description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910007991 Si-N Inorganic materials 0.000 description 4
- 229910006294 Si—N Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910008938 W—Si Inorganic materials 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 배리어 금속층 형성방법에 관한 것으로, 특히 구리배선에 대한 우수한 배리어 특성을 갖는 반도체 소자의 배리어 금속층 형성방법에 관한 것이다.The present invention relates to a method of forming a barrier metal layer of a semiconductor device, and more particularly to a method of forming a barrier metal layer of a semiconductor device having excellent barrier properties to copper wiring.
최근까지의 연구결과로 보면 배리어 금속층으로 가능성이 있는 물질들은 Ta, TaN, TiN, WN, W-Si, W-Si-N, Ti-Si-N 등이 있다.Recent studies show that Ta, TaN, TiN, WN, W-Si, W-Si-N, and Ti-Si-N are potential materials for barrier metal layers.
여기서, 스퍼터링(Sputtering)방법의 일종인 IMP(Ionized Metal Plasma)방법으로 Ta을 배리어 금속층으로 사용할 경우, 콘택 하부에 대한 커버리지(coverage)가 우수한 반면에 사이드 커버리지(side coverage)가 미비하여 구리 원자(Cu atom)에 대한 측벽(side wall)쪽으로의 확산(diffusion)에 대해서는 충분한 배리어 역할을 하지 못한다.In this case, when Ta is used as the barrier metal layer by the ionized metal plasma (IMP) method, which is a sputtering method, the coverage of the lower portion of the contact is excellent, but the side coverage is poor. It does not act as a sufficient barrier against diffusion towards the side walls of the Cu atom.
그리고 TaN 박막에 IMP 방법을 사용할 경우, Ta 증착과 동시에 리액티브 나이트로겐 플라즈마(reactive nitrogen plasma)에 의해 나이트라이드가 발생해야하기 때문에 콘택홀 내부에서 바텀 커버리지(bottom coverage) 및 사이드 커버리지(side coverage)가 Ta 박막의 IMP 방법에 비해 불량한 단점이 있다.In the case of using the IMP method for the TaN thin film, since the nitride must be generated by reactive nitrogen plasma at the same time as the Ta deposition, the bottom coverage and the side coverage inside the contact hole are required. There is a disadvantage that is poor compared to the IMP method of Ta thin film.
따라서, 현재는 스텝 커버리지(step coverage)가 우수한 CVD(Chemical Vapor Deposition)방법으로 배리어 금속층을 형성한다.Therefore, the barrier metal layer is currently formed by a chemical vapor deposition (CVD) method having excellent step coverage.
그러나 CVD 방법에 의한 Ta 및 TaN 박막 증착은 전구체(precursor)가 개발되지 못한 실정이고, TiN의 경우 500℃ 이상에서는 구리에 대하여 충분한 배리어 역할을 못하는 것으로 알려져 있다.However, Ta and TaN thin film deposition by the CVD method has not been developed a precursor (precursor), TiN is known to play a sufficient barrier role for copper above 500 ℃.
3상 화합물(W-Si-N), Ti-Si-N 등)에 관한 연구는 현재 스퍼터링 방법으로 연구가 진행중이지만 그러나 콘택 홀 기저부에서의 스텝 커버리지 불량하여 그 한계가 있다.Studies on three-phase compounds (W-Si-N, Ti-Si-N, etc.) are currently being conducted by sputtering methods, but there are limitations due to poor step coverage at the bottom of contact holes.
즉, 상기와 같은 종래의 반도체 소자의 배리어 금속층 형성방법에 있어서는 스텝 커버리지에 관한 문제점이 있었다.That is, in the conventional method for forming a barrier metal layer of a semiconductor device as described above, there is a problem regarding step coverage.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 듀얼 다마신 공정중 비아 식각 후 탄탈류 및 Cu-Rd 합금을 증착하여 구리에 대한 배리어 특성이 우수한 반도체 소자의 배리어 금속층 형성방법를 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a barrier metal layer of a semiconductor device having excellent barrier properties against copper by depositing tantalum and Cu-Rd alloy after via etching during a dual damascene process. There is this.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체 소자의 배리어 금속층 형성방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a barrier metal layer of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 제 1 금속배선11 semiconductor substrate 12 first metal wiring
13 : 제 1 절연막 14 : 층간 절연막13 first insulating film 14 interlayer insulating film
15 : 트랜치 16 : 비아홀15: trench 16: via hole
17 : Ta 박막 18 : Cu-Rd 박막17: Ta thin film 18: Cu-Rd thin film
19 : 배리어 금속층 20 : 제 2 금속배선19 barrier metal layer 20 second metal wiring
21 : 제 2 절연막21: second insulating film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 배리어 금속층 형성방법은 반도체 기판상에 선택적으로 제 1 금속배선을 형성하는 단계와, 상기 결과물 상부에 제 1 절연막과 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막을 소정깊이로 소정부분 식각하여 트랜치를 형성하고, 상기 트랜치내의 상기 제 1 금속배선이 노출이 되도록 상기 제 1, 제 2 절연막을 선택적으로 식각하여 비아홀을 형성하는 단계와, 상기 결과물 상부에 Ta 박막과 Cu-Rd 박막 그리고 제 2 금속배선을 차례로 형성하는 단계를 포함하는 것을 특징으로 한다.The barrier metal layer forming method of the semiconductor device of the present invention for achieving the above object is a step of selectively forming a first metal wiring on the semiconductor substrate, and forming a first insulating film and a second insulating film on the resultant And forming a trench by etching a predetermined portion of the second insulating film to a predetermined depth, and selectively etching the first and second insulating films to expose the first metal wiring in the trench to form a via hole; And sequentially forming a Ta thin film, a Cu—Rd thin film, and a second metal wire on the resultant.
또한, 상기 Ta 박막과 Cu-Rd 박막 형성시 IMP 방법을 이용하는 것이 바람직하다.In addition, it is preferable to use the IMP method when forming the Ta thin film and the Cu—Rd thin film.
또한, 상기 제 2 금속배선은 상기 Ta 박막과 Cu-Rd 박막상에 제 2 금속배선용 금속층을 증착하는 단계와, 상기 결과물에 CMP 방법을 이용하여 상기 트랜치 및 비아홀에 매립되도록 형성하는 단계를 더 포함하는 것이 바람직하다.The second metal wiring may further include depositing a second metal wiring metal layer on the Ta thin film and the Cu-Rd thin film, and forming the second metal wiring to be buried in the trench and the via hole by using the CMP method. It is desirable to.
또한, 상기 제 2 금속배선용 금속층은 전해도금방법 및 CVD 방법을 이용하여 증착하는 것이 바람직하다.In addition, the second metal wiring metal layer is preferably deposited using an electroplating method and a CVD method.
또한, 상기 Cu-Rd 박막의 두께는 500∼1000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said Cu-Rd thin film is 500-1000 kPa.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 배리어 금속층 형성방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of forming a barrier metal layer of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c은 본 발명의 일실시예에 따른 반도체 소자의 배리어 금속층 형성방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a barrier metal layer of a semiconductor device according to an embodiment of the present invention.
도 1a에 도시한 바와 같이 반도체 기판(11)상에 선택적으로 제 1 금속배선(12)을 형성한 후, 상기 제 1 금속배선(12)상에 제 1 절연막(13)과 층간 절연막(14)을 차례로 형성한다.After the first metal wiring 12 is selectively formed on the semiconductor substrate 11 as shown in FIG. 1A, the first insulating film 13 and the interlayer insulating film 14 are formed on the first metal wiring 12. Form in turn.
이어, 상기 층간 절연막(14)을 소정깊이로 소정부분 식각하여 트랜치(15)를 형성한 후, 듀얼 다마신(dual damascene) 공정을 이용하여 상기 트랜치(15)내의 상기 제 1 금속배선(12) 표면이 선택적으로 노출되도록 비아홀(16)을 형성한다.Subsequently, the trench 15 is formed by etching the interlayer insulating layer 14 to a predetermined depth, and then using the dual damascene process, the first metal wiring 12 in the trench 15. Via holes 16 are formed to selectively expose the surface.
도 1b에 도시한 바와 같이 상기 트랜치(15) 및 비아홀(16)을 포함한 상기 층간 절연막(14)상에 Ta 박막(17) 그리고 Cu-Rd 박막(18)을 차례로 증착하여 배리어 금속층(19)을 형성한다. 이때, 상기 Ta 박막(17)과 Cu-Rd 박막(18)은 IMP 방법을 이용하여 증착하고, 상기 Cu-Rd 박막(18)의 두께는 500∼1000Å이다.As shown in FIG. 1B, a Ta thin film 17 and a Cu—Rd thin film 18 are sequentially deposited on the interlayer insulating layer 14 including the trench 15 and the via hole 16 to form a barrier metal layer 19. Form. At this time, the Ta thin film 17 and the Cu-Rd thin film 18 are deposited using the IMP method, and the thickness of the Cu-Rd thin film 18 is 500 to 1000 mW.
여기서, 상기 Rd 박막은 알카리 금속으로서 산화막과의 결합력이 강하므로 층간 절연막(14)과 반응하여 TdO, RdF 등을 형성한다. 따라서, 후 공정에서 형성될 구리배선이 산화막쪽으로 확산하지 못한다.Here, since the Rd thin film is an alkali metal and has a strong bonding force with the oxide film, the Rd thin film reacts with the interlayer insulating film 14 to form TdO, RdF, or the like. Therefore, the copper wiring to be formed in the later process does not diffuse toward the oxide film.
도 1c에 도시한 바와 같이 상기 배리어 금속층(19)상에 제 2 금속배선용 금속층을 증착한 후, CMP 방법을 이용하여 상기 배리어 금속층(19)을 선택적으로 제거함과 동시에 상기 트랜치(15) 및 비아홀(16)에 금속층을 매립하여 제 2 금속배선(20)을 형성한다. 이때, 상기 제 2 금속배선용 금속층은 구리층이고, CVD 또는 전해도금방법으로 증착한다.As illustrated in FIG. 1C, after the second metal wiring metal layer is deposited on the barrier metal layer 19, the trench 15 and the via hole may be selectively removed while the barrier metal layer 19 is selectively removed using the CMP method. A metal layer is embedded in 16 to form a second metal wiring 20. In this case, the second metal wiring metal layer is a copper layer and is deposited by CVD or electroplating.
이어, 상기 결과물 상부에 제 2 절연막(21)을 형성한다.Subsequently, a second insulating layer 21 is formed on the resultant.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 배리어 금속층 형성방법에 의하면, 스퍼터링 장비에서 Ta과 Cu-Rd로 이루어진 우수한 배리어 특성을 갖는 배리어 금속층을 형성하므로 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the method for forming the barrier metal layer of the semiconductor device of the present invention, since the barrier metal layer having excellent barrier properties made of Ta and Cu-Rd is formed in the sputtering equipment, the reliability of the device can be improved.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010084302A KR20030054178A (en) | 2001-12-24 | 2001-12-24 | A method for froming barrier metal layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010084302A KR20030054178A (en) | 2001-12-24 | 2001-12-24 | A method for froming barrier metal layer of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030054178A true KR20030054178A (en) | 2003-07-02 |
Family
ID=32212831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010084302A KR20030054178A (en) | 2001-12-24 | 2001-12-24 | A method for froming barrier metal layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030054178A (en) |
-
2001
- 2001-12-24 KR KR1020010084302A patent/KR20030054178A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20000035374A (en) | Interconnection structure and fabrication process therefor | |
| US20040175926A1 (en) | Method for manufacturing a semiconductor component having a barrier-lined opening | |
| KR20010004719A (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100376873B1 (en) | Conductive line and interconnection thereof in semiconductor devices and fabricating method thereof | |
| JP2004153274A (en) | Damascene interconnection utilizing barrier metal layer deposited with metal carbonyl | |
| KR100407682B1 (en) | A method of forming a metal line in a semiconductor device | |
| US7902065B2 (en) | Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same | |
| KR20040047503A (en) | Method for forming aluminum metal wiring | |
| KR100399909B1 (en) | Method of forming inter-metal dielectric in a semiconductor device | |
| US20070007654A1 (en) | Metal line of semiconductor device and method for forming thereof | |
| KR20030054178A (en) | A method for froming barrier metal layer of semiconductor device | |
| KR100462762B1 (en) | Method for forming copper metal line of semiconductor device | |
| KR100451493B1 (en) | Metal wiring formation method of semiconductor device | |
| US20020081837A1 (en) | Method for fabricating metal conductors and multi-level interconnects in a semiconductor device | |
| KR20070066298A (en) | Metalline of semiconductor device and method of manufacturing the same | |
| KR100909176B1 (en) | Metal wiring formation method of semiconductor device | |
| KR100453182B1 (en) | Method of forming a metal line in semiconductor device | |
| KR100587600B1 (en) | Method for forming metal wiring using dual damascene process | |
| KR100538632B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100571386B1 (en) | Copper wiring of semiconductor device and manufacturing method thereof | |
| KR100891524B1 (en) | Method of manufacturing semiconductor device | |
| KR100924546B1 (en) | Metal line of semiconductor device and method for manufacturing the same | |
| KR20010003788A (en) | Method of forming a Cu wiring in a semiconductor device | |
| KR100571387B1 (en) | Copper wiring manufacturing method of semiconductor device | |
| KR20030000829A (en) | Method for Forming Metal Line of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |