KR20030052465A - Method for fabricating of silicon wafer - Google Patents
Method for fabricating of silicon wafer Download PDFInfo
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- KR20030052465A KR20030052465A KR1020010082441A KR20010082441A KR20030052465A KR 20030052465 A KR20030052465 A KR 20030052465A KR 1020010082441 A KR1020010082441 A KR 1020010082441A KR 20010082441 A KR20010082441 A KR 20010082441A KR 20030052465 A KR20030052465 A KR 20030052465A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 31
- 239000010703 silicon Substances 0.000 title claims abstract description 31
- 238000004140 cleaning Methods 0.000 claims abstract description 32
- 238000007517 polishing process Methods 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 230000007547 defect Effects 0.000 claims abstract description 5
- 238000005498 polishing Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- 239000000356 contaminant Substances 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 238000009966 trimming Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 61
- 238000005406 washing Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007518 final polishing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 실리콘 웨이퍼의 제조방법에 관한 것으로, 특히 실리콘 웨이퍼의 가장자리 연마 공정을 양면 연마 후에 실시하여 고품질의 실리콘 웨이퍼를 생산하는 실리콘 웨이퍼의 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon wafer, and more particularly, to a method of manufacturing a silicon wafer in which the edge polishing process of the silicon wafer is performed after double-side polishing to produce a high quality silicon wafer.
도1은 종래의 실리콘 웨이퍼를 제조하는 방법을 도시한 공정도이다. 도1에 도시된 바와같이, 현재 반도체 소자에 사용되는 300mm 실리콘 웨이퍼의 생산 공정을 상세히 설명하면 다음과 같다.1 is a process chart showing a method of manufacturing a conventional silicon wafer. As shown in FIG. 1, a production process of a 300 mm silicon wafer currently used in a semiconductor device will be described in detail as follows.
먼저 초크랄스키(Czochralski)방법 또는 플롯트존(Float zone) 방법으로 실리콘 단결정 잉곳(ingot)을 형성한 후, 잉곳을 얇게 절단하여 베어 웨이퍼(Bare Wafer)를 형성한 후 가장자리 연삭을 실시한다(S1).First, silicon single crystal ingots are formed by the Czochralski method or the float zone method, and then the ingots are thinly formed to form bare wafers, and then edge grinding is performed (S1). ).
이후 가공공정이 완료된 웨이퍼와 구분하기 위해서 웨이퍼 형상으로 절단된 웨이퍼를 베어 웨이퍼라 하고 가공공정이 완료된 웨이퍼를 실리콘 웨이퍼라 칭한다.Thereafter, in order to distinguish the wafer from which the processing process is completed, the wafer cut into the wafer shape is called a bare wafer, and the wafer on which the processing process is completed is called a silicon wafer.
그리고 베어 웨이퍼의 전, 후면을 평탄화하기 위해서 연삭(Grinding) 공정을 실시한다(S2).Then, a grinding process is performed to planarize the front and rear surfaces of the bare wafer (S2).
이후 베어 웨이퍼의 가장자리의 거칠기를 감소시키기 위해서 가장자리 연마(polishing) 공정을 실시한다(S3).Thereafter, in order to reduce the roughness of the edge of the bare wafer, an edge polishing process is performed (S3).
그런다음 가장자리 연마공정시 발생된 불순물을 제거하기 위해서 제1차 세정을 실시한다(S4). 이때 세정은 SC-1세정액을 이용한 세정, SC-2 세정액을 이용한 세정, 불산 세정액을 이용한 세정의 3단계에 걸쳐 세정을 실시한다.Then, the first cleaning is performed to remove impurities generated during the edge polishing process (S4). At this time, washing is performed in three stages: washing with SC-1 washing liquid, washing with SC-2 washing liquid and washing with hydrofluoric acid washing liquid.
그리고 세정공정 후 베어 웨이퍼 내에 형성되는 결함을 제거하기 위한 열처리를 실시한다(S5).After the cleaning process, a heat treatment for removing defects formed in the bare wafer is performed (S5).
열처리 후 베어 웨이퍼의 양면을 경면화하기 위해서 양면 연마 공정을 실시한다(S6).After the heat treatment, a double-side polishing process is performed to mirror both surfaces of the bare wafer (S6).
이후 양면 연마 공정으로 발생된 불순물을 제거하기 위한 제2차 세정을 실시한다(S7).이때, 세정은 2단계에 걸쳐 실시되는데 먼저 SC-1 세정액으로 세정하고 연속해서 불산 세정액으로 세정을 실시한다.Subsequently, a second cleaning is performed to remove impurities generated by the double-side polishing process (S7). In this case, the cleaning is performed in two stages, which is first washed with an SC-1 cleaning solution and subsequently with a hydrofluoric acid cleaning solution. .
세정공정이 끝난 후, 베어 웨이퍼의 표면의 거칠기를 더욱 감소시키기 위해서 마무리 연마 공정(final polishing)을 실시하여 실리콘 웨이퍼의 제조를 완료한다(S8).After the cleaning process is finished, a final polishing process is performed to further reduce the roughness of the bare wafer surface (S8).
도2는 상기에 기술된 종래 기술로 제조한 실리콘 웨이퍼의 가장자리 사진으로서, 미소거칠기 값이 9.0Å임을 알 수가 있었다.FIG. 2 is an edge photograph of a silicon wafer manufactured according to the prior art described above, and it can be seen that the micro-roughness value is 9.0 kV.
그러나, 상기에 기술된 종래기술에 따른 실리콘 웨이퍼를 제조하는 방법은 가장자리 연마공정 후 양면 연마공정을 진행하기 때문에 이미 가공된 베어 웨이퍼의 가장자리 부분이 양면 연마공정 시 사용되는 캐리어(Carrier)와의 접촉으로 인해 가장자리의 품질이 저하되는 문제점이 있었다.However, since the method for manufacturing a silicon wafer according to the related art described above proceeds with a double-side polishing process after the edge polishing process, the edge portion of the bare wafer that has already been processed is brought into contact with a carrier used during the double-side polishing process. There was a problem that the quality of the edge is degraded.
따라서 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로 실리콘 웨이퍼 가장자리의 미소거칠기를 감소시켜 고품질의 실리콘 웨이퍼를 생산하는 실리콘 웨이퍼의 제조방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method of manufacturing a silicon wafer, which has been proposed to solve the above-described problems of the prior art, thereby producing a high quality silicon wafer by reducing the fine roughness of the silicon wafer edge.
상기한 목적을 달성하기 위한 본 발명에 따른 실리콘 웨이퍼의 제조방법은 실리콘 단결정 잉곳을 얇게 절단하여 형성한 베어 웨이퍼의 가장자리의 형상을 일정하게 하기 위한 가장자리 연삭 공정과, 상기 가장자리 연삭공정 후 베어 웨이퍼의 표면을 평탄화하기 위한 양면 연삭 공정과, 상기 양면 연삭 공정을 실시한 후 상기 베어 웨이퍼를 경면화하기 위한 양면 연마공정과, 상기 양면 연마 공정을 실시한 후 상기 베어 웨이퍼의 표면에 산화막을 형성하기 위한 제1차 세정공정과, 상기 제1차 세정 공정을 실시한 후, 상기 베어 웨이퍼 가장자리의 거칠기 값을 감소시키기 위한 가장자리 연마 공정과, 상기 가장자리 연마 공정을 실시한 후, 상기 베어 웨이퍼의 불순물을 제거하기 위한 제2차 세정공정과, 상기 제2차 세정공정을 실시한 후, 상기 베어 웨이퍼 내부에 형성된 결함을 제거하기 위한 열처리 공정과, 상기 열처리 공정을 실시한 후, 상기 베어 웨이퍼의 척마크를 제거하기 위한 마무리 연마 공정을 포함하여 이루어진다.The method of manufacturing a silicon wafer according to the present invention for achieving the above object is an edge grinding step for making the shape of the edge of the bare wafer formed by thinly cutting the silicon single crystal ingot, and the bare wafer after the edge grinding step A double-sided grinding step for planarizing the surface, a double-sided polishing step for mirroring the bare wafer after the double-sided grinding step, and a first surface for forming an oxide film on the surface of the bare wafer after the double-sided polishing step A second polishing step for removing impurities in the bare wafer after performing the first cleaning step, an edge polishing step for reducing the roughness value of the bare wafer edge after performing the first cleaning step, and the edge polishing step. After performing the secondary washing step and the second washing step, the bare way After performing the heat treatment step, the heat treatment process for removing defects formed therein, comprises a finish polishing step for removing the chuck mark of the bare wafer.
또한, 상기한 제1차 세정공정은 SC-1 세정액을 65 ~ 80 ℃로 유지한 후 4~6분간 세정하여 8~15㎛ 두께의 산화막을 형성하는 것이 바람직하다.In the above-described first cleaning step, the SC-1 cleaning solution is maintained at 65 to 80 ° C., and then washed for 4 to 6 minutes to form an oxide film having a thickness of 8 to 15 μm.
또한, 상기한 마무리 연마공정은 상기 가장자리 연마 공정시 척마크가 형성된 면을 2㎛ 두께 만큼 제거하여 척마크를 제거하는 것이 바람직하다.In addition, the finish polishing process may remove the chuck marks by removing the surface on which the chuck marks are formed by the thickness of 2 μm during the edge polishing process.
도1은 종래기술에 따른 실리콘 웨이퍼의 제조방법을 도시한 공정 흐름도.1 is a process flow diagram illustrating a method of manufacturing a silicon wafer according to the prior art.
도2는 종래기술에 따른 실리콘 웨이퍼 가장자리의 사진.2 is a photograph of a silicon wafer edge in accordance with the prior art;
도3은 본 발명의 실시예에 따른 실리콘 웨이퍼의 제조방법을 도시한 공정 흐름도.3 is a process flow diagram illustrating a method of manufacturing a silicon wafer in accordance with an embodiment of the present invention.
도4는 본 발명에 따른 실리콘 웨이퍼 가장자리의 사진.4 is a photograph of a silicon wafer edge in accordance with the present invention.
이하 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 실리콘 웨이퍼의 제조방법을 개략적으로 도시한 흐름도이다.3 is a flowchart schematically illustrating a method of manufacturing a silicon wafer according to the present invention.
도3에 도시된 바와같이, 초크랄스키 방법 또는 플롯트존 방법으로 실리콘 단결정 잉곳을 성장시킨후, 잉곳을 얇게 절단하여 베어 웨이퍼를 형성하고 베어 웨이퍼의 가장자리이 형상을 일정하게 하기 위해 가장자리 연삭공정을 실시한다(S101).As shown in Fig. 3, after growing the silicon single crystal ingot by the Czochralski method or the plot zone method, the ingot is cut thinly to form a bare wafer, and the edge grinding process is performed to make the edge of the bare wafer constant in shape. (S101).
본 발명에 따른 제조공정이 완료된 웨이퍼와 완료되지 않은 웨이퍼를 구분하기 위해 편의상 본 발명에 따른 제조공정이 완료된 웨이퍼를 실리콘 웨이퍼라 하고 제조공정이 완료되지 않은 웨이퍼를 베어 웨이퍼(bare wafer)라 한다.For the sake of convenience, a wafer in which the manufacturing process according to the present invention is completed is called a silicon wafer, and a wafer in which the manufacturing process is not completed is called a bare wafer for the purpose of distinguishing a wafer from which the manufacturing process according to the present invention is completed.
그리고 베어 웨이퍼의 표면을 평탄화하기 위해서 양면 연삭 공정을 실시한다(S102).In order to planarize the surface of the bare wafer, a double-sided grinding process is performed (S102).
이후 베어 웨이퍼의 표면을 경면화하고 반도체 디바이스가 형성될 면을 형성하기 위해서 양면 연마 공정을 실시한다(S103).After that, the surface of the bare wafer is mirrored and a double-side polishing process is performed to form a surface on which the semiconductor device is to be formed (S103).
양면 연마 공정이 완료된 후, SC-1세정액으로 세정하여 양면 연마 공정 시 발생된 불순물을 제거하고 베어웨이퍼 표면에 산화막을 형성하기 위한 제1차 세정을 실시한다(S104).After the double-side polishing process is completed, washing with SC-1 cleaning solution removes impurities generated during the double-side polishing process and performs primary cleaning to form an oxide film on the bare wafer surface (S104).
상기의 SC-1 세정액은 암모니아(NH4OH)와 과산화수소(H2O2)혼합액으로 암모니아 : 과산화수소를 1:1의 비율로 혼합하여 형성한다.The SC-1 cleaning solution is a mixture of ammonia (NH 4 OH) and hydrogen peroxide (H 2 O 2), which is formed by mixing ammonia: hydrogen peroxide in a ratio of 1: 1.
여기서 제1차 세정은 SC-1 세정액을 65 ~ 80 ℃로 유지한 후 4~6분간 세정하여 8~15 ㎛ 두께의 산화막을 형성한다. 산화막은 SC-1 세정액에 포함된 과산화수소로 인해 형성된다.In the first cleaning, the SC-1 cleaning solution is maintained at 65 to 80 ° C., followed by 4 to 6 minutes to form an oxide film having a thickness of 8 to 15 μm. The oxide film is formed due to the hydrogen peroxide contained in the SC-1 cleaning liquid.
이렇게 형성된 산화막은 베어 웨이퍼의 보호막으로 사용되어 가장자리 연마시 사용되는 슬러리가 베어 웨이퍼의 표면에 흡착되는 것을 방지하고, 가장자리 연마 공정 후 베어 웨이퍼 표면에 얼룩(stain)이 남지 않도록 한다.The oxide film thus formed is used as a protective film of the bare wafer to prevent the slurry used for edge polishing from adsorbing to the surface of the bare wafer, and to prevent stains on the bare wafer surface after the edge polishing process.
또한, 이후 진행되는 가장자리 연마공정에 사용되는 각종 척으로 인해 베어 웨이퍼 의 양면에 척마크가 형성되는 것을 방지할 수 있으며, 후면에 로봇 척마크 및 정렬기 척마크는 미약하게 형성되도록 한다.In addition, the chuck marks can be prevented from being formed on both sides of the bare wafer due to various chucks used in the edge polishing process, and the robot chuck marks and the aligner chuck marks on the rear surface are weakly formed.
그리고 세정공정이 완료되면, 베어 웨이퍼의 가장자리의 거칠기를 감소시키기 위해서 가장자리 연마 공정을 진행한다(S105).When the cleaning process is completed, the edge polishing process is performed to reduce the roughness of the edge of the bare wafer (S105).
가장자리 연마 공정을 실시한 후 베어 웨이퍼를 SC-1세정액으로 세정하고 연속해서 불산 세정액으로 세정하여 가장자리 연마 공정 때 발생된 불순물을 제거하는 제2차 세정공정을 실시한다(S106).After performing the edge polishing step, the bare wafer is cleaned with the SC-1 cleaning solution and subsequently with the hydrofluoric acid cleaning solution to perform the second cleaning step of removing impurities generated during the edge polishing step (S106).
그리고 세정공정이 완료된 베어 웨이퍼에 열처리를 실시하여 베어 웨이퍼내에 형성된 결함을 제거한다(S107).Then, heat treatment is performed on the bare wafer on which the cleaning process is completed to remove defects formed in the bare wafer (S107).
상기 열처리는 실리콘 웨이퍼를 제조하는 공정에서 일반적으로 실시되는 열처리로본 발명에서 그에 대한 상세한 설명은 생략한다.The heat treatment is a heat treatment generally performed in the process of manufacturing a silicon wafer, and a detailed description thereof is omitted in the present invention.
마지막으로 열처리 후 가장자리 연마 공정 시 후면에 미약하게 형성된 로봇 척마크 및 정렬기 척마크를 제거하기 위해서 마무리 연마공정을 실시한다(S108).Finally, in order to remove the robot chuck mark and the aligner chuck mark that are weakly formed on the rear surface during the edge polishing process after the heat treatment, a finish polishing process is performed (S108).
이때 마무리 연마 공정은 로봇 척마크 및 정렬기 척마크가 형성된 면을 2㎛ 두께 만큼 제거하여 로봇 척마크 및 정렬기 척마크가 완전히 제거되도록 하여 실리콘 웨이퍼의 제조를 완료한다.At this time, the finishing polishing process removes the surface on which the robot chuck mark and the aligner chuck mark are formed by 2 μm thickness to completely remove the robot chuck mark and the aligner chuck mark to complete the manufacture of the silicon wafer.
도4는 본 발명에 따른 실시예1에서 가장자리 연마 공정 후 실리콘 웨이퍼의 가장자리부의 사진으로 측정된 미소 거칠기 값이 3.5Å로 도1의 종래에 따른 가장자리 연마 공정 후의 측정값 9.0Å에 비해 현저히 감소된 것을 확인 할 수가 있다.Figure 4 is a fine roughness value measured by a photograph of the edge portion of the silicon wafer after the edge polishing process in Example 1 according to the present invention is 3.5 Å significantly reduced compared to the measured value 9.0 Å after the edge polishing process according to the prior art of FIG. You can check that.
이상에서 설명한 바와 같이 본 발명은 양면 연마공정 후에 가장자리 연마공정을 실시하여 실리콘 웨이퍼를 제조함으로써 실리콘 웨이퍼의 가장자리의 거칠기를 감소시켜 고품질 실리콘 웨이퍼를 제조하며, 세정공정을 간소화하여 생산성을 향상시킨다.As described above, the present invention manufactures a silicon wafer by performing an edge polishing process after a double-side polishing process to reduce the roughness of the edge of the silicon wafer to produce a high quality silicon wafer, and to simplify the cleaning process to improve productivity.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0957586A (en) * | 1995-08-24 | 1997-03-04 | Shin Etsu Handotai Co Ltd | Working method for wafer |
| KR980011977A (en) * | 1996-07-03 | 1998-04-30 | 이창세 | Mirror-polished wafer manufacturing method |
| JP2001015459A (en) * | 1999-06-30 | 2001-01-19 | Mitsubishi Materials Silicon Corp | Manufacture of double-surface polished wafer |
| JP2001203177A (en) * | 2000-01-18 | 2001-07-27 | Hitachi Cable Ltd | Semiconductor wafer |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0957586A (en) * | 1995-08-24 | 1997-03-04 | Shin Etsu Handotai Co Ltd | Working method for wafer |
| KR980011977A (en) * | 1996-07-03 | 1998-04-30 | 이창세 | Mirror-polished wafer manufacturing method |
| JP2001015459A (en) * | 1999-06-30 | 2001-01-19 | Mitsubishi Materials Silicon Corp | Manufacture of double-surface polished wafer |
| JP2001203177A (en) * | 2000-01-18 | 2001-07-27 | Hitachi Cable Ltd | Semiconductor wafer |
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