KR20030051047A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR20030051047A KR20030051047A KR1020010081945A KR20010081945A KR20030051047A KR 20030051047 A KR20030051047 A KR 20030051047A KR 1020010081945 A KR1020010081945 A KR 1020010081945A KR 20010081945 A KR20010081945 A KR 20010081945A KR 20030051047 A KR20030051047 A KR 20030051047A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- oxide film
- semiconductor device
- manufacturing
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract 2
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 238000005498 polishing Methods 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
Description
본 발명의 반도체 소자의 제조 방법에 관한 것으로, 반도체 소자가 고집적화 되어감에 따라 증가하는 게이트의 저항을 감소시키기 위해서 게이트 전극 상부에실리콘층을 증착시켜 금속 샐리사이드막이 형성되는 부분의 면적을 증가함으로써 저항을 감소시키고 열적 안정성을 높일 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, by increasing the area of a portion where a metal salicide film is formed by depositing a silicon layer on the gate electrode in order to reduce the resistance of the gate, which increases as the semiconductor device becomes highly integrated. The present invention relates to a method for manufacturing a semiconductor device capable of reducing resistance and increasing thermal stability.
고집적 CMOS 소자의 제조에 있어서 게이트의 저항감소는 소자의 속도를 증가시키는 작용을 한다. 종래에 게이트 저항을 감소시키기 위해 여러 가지 방법이 시도되고 있으나 가장 널리 쓰이는 방법이 폴리 실리콘 게이트 상에 금속 샐리사이드막을 형성시켜 저항을 감소시키는 것이다.In the fabrication of highly integrated CMOS devices, the reduced resistance of the gate serves to increase the device speed. Conventionally, various methods have been tried to reduce the gate resistance, but the most widely used method is to reduce the resistance by forming a metal salicide film on the polysilicon gate.
도 1 은 종래 기술에 따른 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 1에 도시한 바와 같이, 트랜치(2)가 형성된 반도체 기판(1)상에 게이트 산화막(Gate oxide)(3) 및 폴리 실리콘(Poly-Si)(4)을 증착하고 게이트 전극(Gate electrode) 패터닝 하여 게이트 전극(5)을 형성한 후 LDD이온 주입공정을 실시한다. 전체 구조상부에 산화막(6) 및 질화막(7)을 증착한 후 건식식각을 수행하여 게이트 전극(5) 측벽에 스페이서(Spacer)를 형성한다. 다음으로 소스(Source) 및 드레인(Drain) 이온주입을 실시하고 소정의 공정을 통하여 게이트, 소스 및 드레인부에 금속 샐리사이드막(8)을 증착하여 반도체 소자를 형성한다.As shown in FIG. 1, a gate oxide 3 and a poly-Si 4 are deposited on a semiconductor substrate 1 on which a trench 2 is formed, and a gate electrode is formed. After forming the gate electrode 5 by patterning, LDD ion implantation process is performed. After the oxide film 6 and the nitride film 7 are deposited on the entire structure, a dry etching is performed to form spacers on the sidewalls of the gate electrode 5. Next, a source and a drain ion implantation are performed, and a metal salicide film 8 is deposited on the gate, the source, and the drain portion through a predetermined process to form a semiconductor device.
상기와 같이 게이트 전극(5) 상부에 금속 샐리사이드막(8)을 증착하는 방법은 게이트 저항을 크게 감소시키는 효과를 주지만 최근 게이트 선 폭이 감소함에 따라 저항값 자체가 증가하는 현상과 또한 후속 열공정에서 금속 샐리사이드막(8)이 열화되어 저항이 증가하는 현상이 발생하고 있다.As described above, the method of depositing the metal salicide layer 8 on the gate electrode 5 greatly reduces the gate resistance, but the resistance value itself increases with the recent decrease of the gate line width, and also subsequent columns. In the process, the metal salicide film 8 deteriorates and a phenomenon in which resistance increases is occurring.
따라서 본 발명은 상술한 단점을 해소할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned disadvantages.
본 발명의 다른 목적은 게이트 전극의 상부를 T자형으로 확장하여 게이트 전극과 금속 샐리사이드막이 접촉되는 면적을 증가할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing the area where the gate electrode is in contact with the metal salicide film by extending the upper portion of the gate electrode in a T-shape.
본 발명의 특징에 의하면 게이트 전극 상부에 금속 샐리사이드막이 형성되는 면적을 증가시켜 후속 열공정시 금속 샐리사이드막이 열화되는 것을 방지하고 게이트 전극의 저항을 감소시킬 수 있다.According to an aspect of the present invention, an area in which a metal salicide film is formed on the gate electrode may be increased to prevent deterioration of the metal salicide film during subsequent thermal processes and to reduce resistance of the gate electrode.
본 발명의 특징에 의하면 저 저항의 게이트 전극을 형성함으로써 고속의 동작이 가능한 소자를 제조할 수 있다.According to the characteristics of the present invention, a device capable of high-speed operation can be manufactured by forming a low resistance gate electrode.
도 1 은 종래 기술에 따른 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2a 내지 2j는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도.2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11 : 반도체 기판2, 12 : 트랜치1, 11: semiconductor substrate 2, 12: trench
3 : 게이트 산화막4, 15 : 폴리 실리콘3: gate oxide film 4, 15: polysilicon
8 : 샐리사이드막6, 14, 16 : 산화막8: salicide film 6, 14, 16: oxide film
7, 17 : 질화막8, 13 : 게이트 전극7, 17: nitride film 8, 13: gate electrode
게이트 전극이 형성된 반도체 기판내에 LDD영역이 형성되는 단계, 전체 구조 상부에 제 1 산화막을 증착한 후 평탄화 공정을 수행하여 상기 게이트 전극을 노출시키는 단계, 상기 제 1 산화막의 일부를 제거하여 상기 게이트 전극의 일부를 노출시킨 후 상기 노출된 게이트 전극의 표면에 실리콘층을 형성시키는 단계, 상기 제 1 산화막이 제거된 후의 상기 전체 구조 상부에 제 2 산화막 및 질화막이 증착되는 단계, 상기 게이트 전극의 측벽에 이웃하는 산화막의 측벽에만 일부의 질화막이 잔류 되도록 상기 질화막을 제거하는 공정을 실시하는 단계, 상기 반도체 기판에 이온을 주입하여 소스 및 드레인을 형성하는 단계 및 노출된 제 2 산화막을 제거하는 단계를 포함하여 이루어 진 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Forming an LDD region in a semiconductor substrate having a gate electrode, depositing a first oxide film over the entire structure, and then performing a planarization process to expose the gate electrode, and removing a portion of the first oxide film to remove the gate electrode. Forming a silicon layer on a surface of the exposed gate electrode after exposing a portion of the second electrode; depositing a second oxide film and a nitride film on the entire structure after the first oxide film is removed; Removing the nitride film so that a portion of the nitride film remains only on sidewalls of neighboring oxide films; implanting ions into the semiconductor substrate to form a source and a drain; and removing the exposed second oxide film. It provides a method for manufacturing a semiconductor device, characterized in that made.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2j는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 게이트 전극(Gate electrode)(13)이 형성된 반도체 기판(11)에 LDD(Lighty doped drain) 이온주입을 시행하여 반도체 기판(11)내의 활성 영역에 LDD영역을 형성한다.As shown in FIG. 2A, LDD (Lighty doped drain) ion implantation is performed on the semiconductor substrate 11 having the gate electrode 13 to form an LDD region in the active region of the semiconductor substrate 11. .
도 2b 및 2c에 도시한 바와 같이, 전체 구조 상부에 제 1 산화막(14)을 게이트 전극(13)의 두께보다 200 내지 2000Å 두껍게 증착한다. 상기의 게이트 전극(13)을 식각 정지층으로 하는 CMP(Chemical Mechanical Polishing)를 이용하여 평탄화 공정을 수행한다. 이때 제 1 산화막(14)으로는 TEOS 또는 CVD 및 PVD로 제조되는 산화막이 사용될 수 있다.As shown in Figs. 2B and 2C, the first oxide film 14 is deposited 200 to 2000 Å thicker than the thickness of the gate electrode 13 over the entire structure. The planarization process is performed by using chemical mechanical polishing (CMP) using the gate electrode 13 as an etch stop layer. In this case, an oxide film made of TEOS or CVD and PVD may be used as the first oxide film 14.
도 2d에 도시한 바와 같이, 제 1 산화막(14)의 일부를 제거하여 게이트 전극(13)의 상부를 돌출 시킨다. 구체적으로 제 1 산화막(14)은 BOE 및 HF를 이용한 습식 식각이나 통상적인 건식 식각공정을 통하여 약 50 내지 500Å의 두께만큼제거된다.As shown in FIG. 2D, a portion of the first oxide film 14 is removed to protrude the upper portion of the gate electrode 13. Specifically, the first oxide layer 14 is removed by a thickness of about 50 to 500 kW through wet etching using BOE and HF or a general dry etching process.
도 2e에 도시한 바와 같이, SEG(Selective Epitaxial Growing)공정을 이용하여 선택적 실리콘 증착(Selective Silicon Deposition)을 함으로써 돌출된 게이트 전극(13) 상부에 실리콘(15)을 성장시킨다.As shown in FIG. 2E, the silicon 15 is grown on the protruding gate electrode 13 by performing selective silicon deposition using a selective epitaxial growing (SEG) process.
구체적으로 SEG공정은 500 내지 1000℃의 온도와 1 내지 600Torr의 압력 하에서 DCS, SiH4,Si2HCl2또는 Si2H6를 실리콘 소스가스(Source gas)로 이용하여 게이트 전극(13)의 돌출부의 표면에 실리콘층(15)을 성장시킨다. 상기 돌출부 이외에 성장된 실리콘은 HCl 및 Cl과 같은 식각가스(Etchant gas)를 사용하여 제거한다. 상기와 같은 조건의 SEG공정을 통하여 게이트 전극(13)의 돌출부에 10 내지 500Å의 두께의 실리콘층(15)이 형성된다.Specifically, the SEG process uses the DCS, SiH 4 , Si 2 HCl 2 or Si 2 H 6 as a silicon source gas at a temperature of 500 to 1000 ° C. and a pressure of 1 to 600 Torr. The silicon layer 15 is grown on the surface of the. Silicon grown in addition to the protrusions is removed using an etchant gas such as HCl and Cl. Through the SEG process under the above conditions, the silicon layer 15 having a thickness of 10 to 500 Å is formed on the protrusion of the gate electrode 13.
도 2f 및 2g에 도시한 바와 같이, 제 1 산화막(14)을 제거한 후 전체 기판상부에 제 2 산화막(16) 및 질화막(17)을 증착한다.As shown in Figs. 2F and 2G, after removing the first oxide film 14, the second oxide film 16 and the nitride film 17 are deposited on the entire substrate.
구체적으로 제 1 산화막(14)은 BOE 및 HF를 이용한 습식 식각이나 통상적인 건식 식각공정을 이용하여 제거한다. 제 2 산화막(16)은 HLD(High Temperature Low pressure Deposition)산화막을 증착하여 질화막(17)의 스트레스(Stress)를 해소 시켜주는 버퍼(Buffer)층 역할을 한다. 질화막(17)을 증착하여 게이트 측벽을 보호하고 LDD영역을 확보한다.Specifically, the first oxide layer 14 is removed by wet etching using BOE and HF or by using a conventional dry etching process. The second oxide layer 16 serves as a buffer layer that relieves stress of the nitride layer 17 by depositing a high temperature low pressure deposition (HLD) oxide layer. The nitride film 17 is deposited to protect the gate sidewall and to secure the LDD region.
도 2h 및 2i에 도시한 바와 같이, 건식 식각을 실시하여 질화막(17)의 일부를 제거한다. 반도체 기판(11)에 이온을 주입하여 소스 및 드레인을 형성한다.As shown in FIGS. 2H and 2I, dry etching is performed to remove a part of the nitride film 17. Ions are implanted into the semiconductor substrate 11 to form a source and a drain.
구체적으로 제 2 산화막(16)을 마스크로 이용하여 게이트 전극(13)의 측벽부에 질화막(17)의 일부가 잔존하도록 건식 식각공정을 수행한다. 상기 이온주입 공정시 제 2 산화막(16)이 스크린 산화막의 역할을 하여 이온이 주입되는 영역의 표면이 손상되는 것을 보호한다.Specifically, a dry etching process is performed using a second oxide film 16 as a mask so that a part of the nitride film 17 remains in the sidewall portion of the gate electrode 13. During the ion implantation process, the second oxide layer 16 serves as a screen oxide layer to protect the surface of the region into which ions are implanted.
도 2j에 도시한 바와 같이, 질화막(17)에 의해 보호된 영역 즉 게이트 측벽 및 LDD상부의 제 2 산화막(16)을 제외한 나머지 부분의 제 2 산화막(16)을 제거하여 반도체 소자를 형성한다. 도시되지 않은 전체 구조 상부에 코발트 및 티타늄을 증착한 후 열처리하여 게이트, 소스 및 드레인 상부에 샐리사이드막을 증착함으로써 반도체 소자의 저항을 낮출 수 있다.As shown in FIG. 2J, the semiconductor element is formed by removing the second oxide film 16 in the remaining portion except for the region protected by the nitride film 17, that is, the gate sidewall and the second oxide film 16 over the LDD. The resistivity of the semiconductor device may be lowered by depositing cobalt and titanium on the entire structure, which is not shown, and then thermally depositing a salicide layer on the gate, the source, and the drain.
고집적 소자의 게이트 전극의 열화를 막기 위해 샐리사이드막 형성전 게이트 전극의 상부를 T자형으로 확장시켜 샐리사이드막과 게이트 전극이 접촉하는 면적을 넓힌다. 그럼으로써 낮은 게이트 저항을 얻을 수 있을 뿐만 아니라 후속 열 공정에 대한 열안정성도 향상할 수 있는 고집적 반도체 소자를 제조할 수 있다.In order to prevent deterioration of the gate electrode of the highly integrated device, the upper portion of the gate electrode before forming the salicide film is extended in a T-shape to increase the area where the salicide film is in contact with the gate electrode. This allows fabrication of highly integrated semiconductor devices that not only achieve low gate resistance but also improve thermal stability for subsequent thermal processes.
이와 같이 반도체 소자의 제조 방법은 선택적 실리콘 증착(Selective Silicon Deposition)을 통하여 게이트 전극 상부에 실리콘층을 형성함으로써 게이트 전극상부가 확장된 T형의 게이트 전극을 형성할 수 있다.As described above, in the method of manufacturing a semiconductor device, a T-type gate electrode having an extended upper portion of the gate electrode may be formed by forming a silicon layer on the gate electrode through selective silicon deposition.
또한 게이트 전극상부의 확장된 영역에 샐리 사이드층을 증착함으로써 샐리사이드층과 게이트 전극 상부의 접촉면이 증가함으로 인해 낮은 게이트 저항을 얻을 수 있고 후속 열공정에 대한 열안정성도 크게 향상할 수 있다.In addition, by depositing a sally side layer in the extended region over the gate electrode, a low gate resistance can be obtained by increasing the contact surface between the sally side layer and the top of the gate electrode, and the thermal stability for subsequent thermal processes can be greatly improved.
또한 소스 및 드레인 이온주입 공정시 이온이 주입되는 영역의 표면을 보호할 수 있다.In addition, the source and drain ion implantation process may protect the surface of the region implanted with ions.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0081945A KR100412194B1 (en) | 2001-12-20 | 2001-12-20 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0081945A KR100412194B1 (en) | 2001-12-20 | 2001-12-20 | Method of manufacturing a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030051047A true KR20030051047A (en) | 2003-06-25 |
| KR100412194B1 KR100412194B1 (en) | 2003-12-24 |
Family
ID=29576914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0081945A KR100412194B1 (en) | 2001-12-20 | 2001-12-20 | Method of manufacturing a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100412194B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100612351B1 (en) * | 2005-04-12 | 2006-08-16 | 주식회사 대정 이.피.에이 | Apparauts for separating sand |
| KR100905789B1 (en) * | 2008-01-02 | 2009-07-02 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device with vertical transistor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766406A (en) * | 1993-08-25 | 1995-03-10 | Oki Electric Ind Co Ltd | Self-aligned silicide mosfet and its manufacture |
| JP3308082B2 (en) * | 1993-12-28 | 2002-07-29 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP3811518B2 (en) * | 1995-01-12 | 2006-08-23 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| KR19990084304A (en) * | 1998-05-04 | 1999-12-06 | 김영환 | Semiconductor device and manufacturing method thereof |
| KR100318311B1 (en) * | 2000-01-12 | 2001-12-22 | 박종섭 | Method of forming a silicide layer in semiconductor devices |
-
2001
- 2001-12-20 KR KR10-2001-0081945A patent/KR100412194B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100612351B1 (en) * | 2005-04-12 | 2006-08-16 | 주식회사 대정 이.피.에이 | Apparauts for separating sand |
| KR100905789B1 (en) * | 2008-01-02 | 2009-07-02 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device with vertical transistor |
| US7871913B2 (en) | 2008-01-02 | 2011-01-18 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device having vertical transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100412194B1 (en) | 2003-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100282452B1 (en) | Semiconductor device and method for fabricating the same | |
| US20070210357A1 (en) | Mosfet having recessed channel and method of fabricating the same | |
| JP2000077658A (en) | Manufacture of semiconductor device | |
| JP2003174159A (en) | Manufacturing method for semiconductor device | |
| US5702986A (en) | Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges | |
| KR20030029400A (en) | Method for forming plug in semiconductor device | |
| US6969646B2 (en) | Method of activating polysilicon gate structure dopants after offset spacer deposition | |
| US6524938B1 (en) | Method for gate formation with improved spacer profile control | |
| KR100629606B1 (en) | Method for improving the gate oxidation quality of high voltage device area | |
| KR100412194B1 (en) | Method of manufacturing a semiconductor device | |
| KR100370128B1 (en) | Method for manufacturing of semiconductor device | |
| KR100525912B1 (en) | Method of manufacturing a semiconductor device | |
| KR100451038B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100427535B1 (en) | Method of manufacturing a semiconductor device | |
| US6743690B2 (en) | Method of forming a metal-oxide semiconductor transistor | |
| KR20030050785A (en) | Method of manufacturing a semiconductor device | |
| KR100359162B1 (en) | Method for manufacturing transistor | |
| KR100429229B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR20030050792A (en) | Method for Fabricating of Semiconductor Device | |
| KR20010008564A (en) | Method for manufacturing transistor of a semiconductor device | |
| KR20030050784A (en) | Method of manufacturing a semiconductor device | |
| KR100437829B1 (en) | Method for fabricating of semiconductor device | |
| KR20050009497A (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR20030044145A (en) | Method of manufacturing a semiconductor device | |
| KR20000041953A (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |