KR20030047027A - Memory device in semiconductor - Google Patents

Abstract

PURPOSE: A memory device is provided to reduce a loss of an operating time by controlling the operating time of an address decoder according to the usage of a redundancy circuit. CONSTITUTION: A memory device includes an address latch portion(300), a fuse portion(500), a fuse box comparison portion(600), a repair check portion(700), and a decoder(400). The address latch portion receives an address signal. The fuse portion outputs a repaired address signal and a fuse enable signal. The fuse box signal portion outputs the address signal and the first enable signal to the decoder when the repaired address signal corresponds to the output signal of the address latch portion. The repair check portion outputs the second enable signal to the decoder when the fuse enable signal is in the inactive state. The decoder is used for deciding the address signal according to the first enable signal or the repaired address signal according to the second enable signal.

Description

Memory device in semiconductor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit technology, and more particularly, to a method and a decoder thereof for decoding an address of a memory device having a redundancy circuit.

In general, to solve a problem in which a chip does not operate normally when a defect occurs in some memory cells in a memory device, a spare memory cell is made in advance and the defective cell is left as a spare cell after a test. In this case, the spare cell is called a spare cell, and a circuit that participates in such a replacement operation is called a redundancy circuit.

Once the test is performed, the internal circuit is programmed to select the bad memory cell and replace the corresponding address with the address signal of the spare cell. Therefore, when the address corresponding to the bad line is input in actual use, it is selected as a spare line instead. Will change.

FIG. 1 is a block diagram showing decoding of an address of a semiconductor device having a conventional redundancy circuit, and FIG. 2 is a circuit diagram showing the decode inside of FIG.

Referring to FIG. 1, a block structure for decoding an address includes an electrostatic protection circuit 100 receiving an address from an outside of the chip, an address buffer unit 200 buffering an address passing through the electrostatic protection circuit 100, and And a latch unit 300 for latching an address signal, a fuse unit 500 having a repaired address, a fuse comparison unit 600 for comparing an address of the fuse unit 500 with an address of the latch unit, and a fuse. The decoder 400 determines and decodes an address to be decoded from a latch address and a programmed address of the fuse unit according to a signal of the comparator.

Next, referring to FIG. 2, the decoder 400 includes a selector 420 for decoding an address signal, a controller 430 for buffering a decoded signal according to a decoder enable signal, and a controller 430. And an output unit 440 for outputting an output signal.

Here, the selector 420 is composed of NAND gates 410a, 410b, 410c, and 410d which receive any two signals among the address address <0> signal, the address <1> signal, and the inverted respective signals.

The control unit 430 includes NAND gates 430a, 430b, 430c, and 430d that receive output signals of the NAND gates 410a, 410b, 410c, and 410d and a decoder enable signal.

The output unit 440 includes inverters 440a, 440b, 440c, and 440d which invert and output the outputs of the NAND gates forming the control unit 430, respectively.

Hereinafter, an address decoding operation including a redundancy circuit according to the prior art will be described with reference to FIGS. 1 and 2.

The input address from the outside is latched by the address latch unit 300 to the address value having the voltage level required by the internal circuit via the static electricity protection circuit 100 and the address buffer 200. The latched address is decoded by the decoder 400 to operate a word line corresponding to the input address.

However, when some of the word lines do not perform their original roles due to process problems or the like, they should be replaced with redundancy word lines, which is called a repair. For repair, check the presence of the error through the tester, and then cut the enable fuse in the redundancy circuit to be used when there is an error, indicating that the redundancy circuit is used, and the latch address of the problematic word line. The combination of fuses in the fuse set corresponding to the cut is cut.

After the repair step, the latch address formed in the address latch unit 300 is sent to the fuse comparator 600 and the decoder of the redundancy circuit, which is programmed in the address and fuse set latched by the fuse comparator 600. The repaired addresses are compared to generate a signal for controlling the operation time of the decoder of the decoder.

If the repair address and the latched address do not match, the decoder operates normally to operate the normal word line corresponding to the latch address, but if the latch address and the repair address match, the decoding operation is stopped and the repair decoder configured separately is executed. This causes the redundancy word line to operate.

In this manner, the operation time of the decoder is determined by the output signal of the fuse comparator 600. When the repair is not performed, the fuse comparator 600 is not required even though the operation of the fuse comparator 600 is not necessary. The operation time of the decoder is determined by the output signal of

That is, in the non-repaired device, there is a problem in that the time for generating an output signal by comparing the latch address and the repair address in the fuse comparator 600 regardless of the repair operation is a loss of operation time.

It is an object of the present invention to provide an apparatus of a memory device including a decoder control circuit which reduces an operation time loss by adjusting an operation time of an address decoder according to whether a redundancy circuit is used when decoding an address of a memory device.

1 is a block diagram showing decoding of an address of a semiconductor device having a conventional redundancy circuit.

FIG. 2 is a circuit diagram showing the decode interior of FIG.

3 is a block diagram illustrating decoding of an address of a semiconductor device having a redundancy circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing the repair check unit of FIG. 3; FIG.

Fig. 5 is a circuit diagram showing the decode inside of Fig. 3;

* Description of the main parts of the drawings

300: address latch unit

400: decoder

500: fuse

600: fuse comparator

700: repair check unit

In order to achieve the above object, the apparatus of the memory device of the present invention comprises an address latch unit for receiving an address signal; A fuse unit configured to output a repaired address signal and a fuse enable signal; A fuse box comparator configured to compare the repaired address signal with an output signal of the address latch unit and to output a matched address and a first enable signal to a decoder; A repair checker configured to output a second enable signal to the decoder when the fuse enable signal is inactivated; And a decoder for decoding the address signal according to the first enable signal, or decoding the repaired address signal according to the second enable signal.

The present invention determines whether a repair is performed using a signal having a redundancy circuit in the initial operation of the memory device, and if it is not repaired, operates the decoder regardless of the result of comparing the latch address and the repair address. It is characterized by reducing the operation time of the decoder.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention. In addition, description that abbreviate | omits the above-mentioned description is abbreviate | omitted.

3 is a block diagram illustrating decoding of an address of a semiconductor device having a redundancy circuit according to an embodiment of the present invention.

Referring to FIG. 3, a block structure for decoding an address includes an electrostatic protection circuit 100 receiving an address from an outside of the chip, an address buffer unit 200 buffering an address passing through the electrostatic protection circuit 100, and A latch unit 300 for latching an address signal, a fuse unit 500 having a repaired address, a fuse comparison unit 600 for comparing an address of the fuse unit 500 with an address of the latch unit, and a fuse The decoder 400 is configured to decode and decode an address to be decoded among the latched addresses and the programmed addresses of the fuse unit according to the signal of the comparator 600, and the repair check unit 700 determines whether the fuse is cut.

FIG. 4 is a circuit diagram illustrating the repair check unit 700 of FIG. 3, the configuration of which includes Nand gates 711 to 718 and NAND gates 711 to 718 that receive a plurality of signals (fenb) indicating fuse cutting. Outputs of a plurality of Nor gates 721 to 724 that receive the outputs of 718, NAND gates 731 and 732 that receive outputs of the NOR gates 721 to 724, and NAND gates 731 and 732. It consists of a knock gate 740 that receives the input.

FIG. 5 is a circuit diagram illustrating a decoded interior of FIG. 3. The configuration includes a selector 420 for decoding an address signal, a controller 430 for buffering a decoded signal in accordance with a decode enable signal, and a controller. An output unit 440 for outputting the output signal of the signal and the enable stage 450 for operating the decode irrespective of the decoder enable signal (decoder enable signal).

The enable unit 450 receives the repair check signal and receives the output of the inverters 451 and 452 and the output of the inverter 452 to the work inputs of the NAND gates 430a, 430b, 430c, and 430d that form the control unit. The PMOS transistor 453 to deliver is provided.

Hereinafter, the operation will be described with reference to FIGS. 3 to 5.

First, the input address input from the outside is latched in the address latch unit 300 by the address value having the voltage level required by the internal circuit via the static electricity protection circuit 100 and the address buffer 200.

The fuse comparison unit 600 compares the latch address, which is the output of the latch unit 300, with the repair address, and a fenb indicating whether or not the enable fuse is cut. If not, it is a signal that is fixed high.) By using a combination of signals, the decoder enables a decoder enable signal, and the operation of the decoder is primarily controlled by this signal, and the decoder's redundancy enable signal is additionally controlled. The repair check signal is input to the decoder 400 in the concept of an OR and used as a control signal of the decoder 400.

The repair check signal is a signal that is determined by whether a chip is repaired by receiving an enable signal (fenb signal) of the entire word line-related fuse.

If the corresponding chip is not repaired, the signal is fixed high when the repair is checked at the initial stage of operation, thereby turning on the PMOS transistor through the latch unit of the enable unit 450 of the decoder 400. As a result, the decoder 400 may operate regardless of the decoder redundancy enable signal, which is an output signal of the fuse comparator 600.

In addition, the decoder 400 described above is applicable to bit line repair as well as word line repair.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention, the address decoder of the memory device can be reduced by about 1,5 n to 2 ns compared with the conventional decoder, thereby improving the operating performance of the memory device.

Claims (3)

An address latch unit for receiving an address signal; A fuse unit configured to output a repaired address signal and a fuse enable signal; A fuse box comparator configured to compare the repaired address signal with an output signal of the address latch unit and to output a matched address and a first enable signal to a decoder; A repair checker configured to output a second enable signal to the decoder when the fuse enable signal is inactivated; And A decoder for decoding the address signal according to the first enable signal, or decoding the repaired address signal according to the second enable signal Memory device comprising a. The method of claim 1, The repair check unit, A plurality of NAND gates receiving a plurality of the fuse enable signals; A plurality of NOR gates receiving two of the outputs of the NAND gates; And A plurality of NAND gates receiving two of the outputs of the plurality of NOR gates Memory device comprising a. The method of claim 1, The decoder, A first NAND gate terminal comprising a plurality of NAND gates receiving the address or the repaired address signal and outputting a specific one; A second NAND gate stage including a plurality of NAND gates each having an output of the first NAND gate as one input and a type force of the first enable signal; An inverter stage comprising a plurality of inverters each receiving and buffering an output of the second NAND gate stage; And An enable end configured to receive the second enable signal and apply a power supply voltage to input terminals of the plurality of NAND gates to which the first enable signal is input; Memory device comprising a.