KR20030043156A - A fabricating method of semiconductor devices - Google Patents

Abstract

PURPOSE: A method for fabricating a contact in a semiconductor device is provided to be capable of preventing losses of an interlayer dielectric, open defects and short between electrodes. CONSTITUTION: A plurality of conductive patterns are formed on a substrate(10). The first etch barrier layers(15,16) are formed at both sidewalls of the conductive patterns. The second etch barrier layer(17) and an interlayer dielectric(18) are sequentially formed on the resultant structure. By selective etching of the interlayer dielectric(18) and the second etch barrier layer(17), a contact hole(19) is formed to expose the substrate. The first and second etch barrier layer(15,16,17) are composed of a nitride layer and an aluminum oxide layer, respectively. Preferably, the thickness of the first and second etch barrier layer is 50Å-500Å.

Description

A fabricating method of semiconductor devices

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices. The resolution (resolution, R) of the photosensitive film pattern is proportional to the wavelength? And the process variable k of the light source of the reduced exposure apparatus and inversely proportional to the lens aperture NA, the numerical aperture of the exposure apparatus. That is, since R = k * λ / NA, the wavelength of the light source should be reduced to improve the light resolution of the reduced exposure apparatus. For example, the G-line and i-line reduction exposure apparatuses having wavelengths of 436 nm and 365 nm have a process resolution of 0.7 and 0.5 µm, respectively, and have a short wavelength of ultraviolet rays, for example, 248 nm, to form a fine pattern of 0.5 µm or less. An exposure apparatus using KrF laser or Ar93 laser as a light source as a light source, or using a phase inversion mask as an exposure mask as a process method, and forming a separate thin film on the wafer to improve image contrast Contrast Enhancement Layer (CEL) method, Tri-Layer Resist (TLR) method in which an intermediate layer such as SOG (Spin On Glass) is interposed between two layers of photoresist, or silicide that selectively injects silicon on the photoresist. Development methods have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in the highly integrated semiconductor device having a multi-layered wiring, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin. These contact holes allow misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension (CD) changes during mask fabrication and photolithography processes, or masks to maintain spacing. In order to form a mask in consideration of factors such as interfacing, the self-aligning method (hereinafter referred to as SAC) is introduced as it becomes difficult to secure an effective active area in the direct contact method as the integration degree of the device increases. In order to prevent defects of the device due to short-circuits with conductive layers such as gates during contact etching for forming a landing plug, hard masks and etch barriers using nitride films are used by the SAC. have.

On the other hand, the conventional plug is formed in the vertical direction only at the contact forming portion. Meanwhile, another plug for contact with another conductive pattern to be formed on the plug is formed in order to form a stacked structure of the device for improving the degree of integration. As the size decreases, the density decreases and the possibility of short circuit due to misalignment increases, resulting in a decrease in process margin. Therefore, a landing plug that can be extended to the contact forming area and the surrounding area to increase the contact margin is mainly used. .

However, due to the high integration of semiconductor devices, such landing plug contact sizes become smaller and smaller, resulting in problems such as misalignment and contact open fail. These problems also improve the integration and yield of devices. It remains a challenge to be solved.

1A to 1C are cross-sectional views illustrating a semiconductor device manufacturing process according to the prior art.

First, as shown in FIG. 1A, a plurality of gate polysilicon layers 3 and a gate silicide layer 4 such as tungsten silicide are stacked on a substrate 1 on which various elements for forming a semiconductor device are formed. A gate electrode pattern is formed.

Specifically, in order to form a gate oxide film 2 between the substrate 1 and the gate polysilicon layer 3, to prevent the loss of the gate due to subsequent self-aligned etching or the like on the gate silicide layer 4 The hard mask 5 of the nitride film series is formed.

Subsequently, the nitride film 6 for the gate electrode spacer and the interlayer insulating film 7 are sequentially formed on the entire surface of the substrate including the gate electrode, and then the interlayer insulating film 7 is subjected to a chemical mechanical polishing (CMP) process. After planarization, a photoresist pattern 9 is formed on the interlayer insulating layer 7 to define a contact portion connected to a storage node or a bitline to be formed by a subsequent process.

Next, as illustrated in FIG. 1B, the exposed portion of the interlayer insulating layer 7 is etched by an etching process using the photoresist pattern 10 as an etching mask, and the landing plug contact 8 is formed by the SAC process.

Next, as shown in FIG. 1C, a cleaning process is performed to remove the residues A such as polymers due to contact formation.

On the other hand, since the etching selectivity with the interlayer insulating film 7 is high, the nitride film used as the hard mask 5 and the spacer to minimize the attack of the gate electrode during the SAC process generates a large amount of by-products such as polymer during etching. By inducing the inclination (A) to the contact forming site by such a polymer, the open area such as 'B' is narrowed to act as a factor to increase the overall resistance of the device, or in severe cases the contact such as 'C' As open defects occur, this is likely to become a bigger problem as the integration speeds up, and such polymers are not easily removed through the cleaning process.

In addition, when the cleaning process is increased to increase the area of the contact portion by removing the polymer (A), loss of the interlayer insulating film 7 becomes severe as in 'D', resulting in inter-element isolation, which is an inherent characteristic of the interlayer insulating film. Isolation is dropped, thereby increasing the possibility of short circuit between devices.

Next, although not shown in the drawing, after depositing the polysilicon for the plug contact on the entire surface of the result, the polysilicon layer for the plug contact, the interlayer insulating film 7 and the spacer until the hard mask 5 is sufficiently exposed by the CMP process The molten nitride film 6 is polished to complete the poly contact plug forming process.

On the other hand, when the spacer is omitted in order to solve the problem of the contact open defect, the exposure of the gate electrode occurs during etching, which leads to a short circuit with the subsequent plug, so that the contact open defect and the short circuit between the electrodes are traded-off each other. Trade-off relationship.

The present invention proposed to solve the problems of the prior art as described above, while preventing the loss of the interlayer insulating film according to the subsequent cleaning process, at the same time to prevent contact open defects and to form a contact that can effectively prevent the short circuit between electrodes The purpose is to provide a method.

1A to 1C are cross-sectional views illustrating a semiconductor device manufacturing process according to the prior art;

2A to 2C are cross-sectional views showing a semiconductor device manufacturing process according to the present invention.

* Explanation of symbols for the main parts of the drawings

10: substrate

11: gate insulating film

12: polysilicon layer for gate

13: silicide layer for gate

14: hard mask insulating film

15, 16, 17: etching prevention film

18: interlayer insulating film

19: contact hole

The present invention to solve the above problems, forming a plurality of neighboring conductive patterns on the substrate; Forming a first etch stop layer covering at least the conductive pattern sidewalls; Sequentially forming a second etch stop layer and an interlayer insulating layer along a surface of the substrate including the conductive pattern on which the etch stop layer is formed; And selectively etching the interlayer insulating layer and the second etch stop layer to form a contact hole exposing the surface of the substrate between the conductive patterns.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.

2A to 2C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

First, as illustrated in FIG. 2A, a plurality of gate polysilicon layers 12 and a gate silicide layer 13 such as tungsten silicide are stacked on a substrate 10 on which various elements for forming a semiconductor device are formed. A conductive pattern of, for example, a gate electrode pattern is formed.

That is, a gate insulating film 11 is formed between the substrate 10 and the gate polysilicon layer 12, and a nitride film for preventing the loss of the gate due to subsequent self-aligned etching or the like on the gate silicide layer 13. A series hard mask insulating film 14 is formed.

Subsequently, the etch stop layer 15 for the gate electrode spacer 15 is deposited on the entire surface of the substrate including the hard mask insulating layer 14, and then the spacer layer is formed on the sidewall of the gate electrode pattern through an etching process. Form to cover.

In this case, the etch stop layer 15 is preferably formed to have a thickness of 50 kPa to 100 kPa to prevent contact open defects and gate electrode loss during subsequent contact formation.

Subsequently, an ion implantation mask is formed to form a source / drain junction of the transistor, and then a source / drain junction is formed below the substrate 10 between the gate electrodes through ion implantation, and thus omitted for simplicity. .

Next, as illustrated in FIG. 2B, a thickness of 50 μm to 100 μm is deposited on the entire surface of the substrate 10 including the gate electrode on which the etch stop layer 15 is formed. Subsequently, the anti-etching film 17 is deposited to have a thickness of 50 mW to 100 mW along the entire structure surface. The anti-etching films 15 and 16 and 17 are formed of a laminated structure of the same material, and the entirety thereof is formed. The thickness is to be 100 mW to 1000 mW.

Next, as shown in FIG. 2C, the interlayer insulating film 18 is deposited on the etch stop layer 17 to a thickness of 2000 GPa to 15000 GPa, and then planarized by a CMP process, and then a contact portion to be formed by a subsequent process is defined. To do this, a photosensitive film pattern 19 is formed on the interlayer insulating film 18.

Specifically, the interlayer insulating film 18 is formed of an oxide-based material film such as BoroPhosphorSilicate Glass (BPSG), High Density Plasma (HDP), Phospho-Silicate Glass (PSG), or Advanced Planarization Layer (APL). That is, it is preferable that the thickness of the interlayer insulating film 18 remaining from above the etch stop film 17 is 500 kPa to 5000 kPa.

Subsequently, an interlayer insulating film 18 is selectively etched by an etching process using a photoresist pattern (not shown) as an etch mask to define a region to be formed for contact formation for connecting a charge storage electrode or a bit line. The etch stop layer 17 is exposed between the etch stop layer 17 and the etch stop layer 17 is selectively etched to allow the etch stop layer 17 to remain on the substrate 10 between the gate electrode side walls and the gate electrode. Maintain proper pressure and power and use gas such as C ₄ F ₈ , CH ₂ F ₂ , Ar, O ₂ , Co, or a mixture thereof.

Subsequently, a washing process is performed to remove the polymer, a by-product generated during etching, and a buffered oxide etchant (BOE) in which sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) are mixed. The washing process is carried out using an appropriate time.

Therefore, by depositing the anti-etching film 15, 16, 17 thinner than the conventional, the process margin during the etching is increased, thereby reducing the amount of polymer generated, thereby increasing the area in the contact area and at the same time open another contact in the subsequent process The probability of defects can be minimized.

Subsequently, the etch stop layer 17 is selectively etched to form a contact hole 19 exposing the substrate 10 between the gate electrodes, and then a cleaning process is performed under the same conditions as described above to remove the byproduct polymer. As a result, the polymer is sufficiently removed while minimizing the loss of the interlayer insulating film 18, and as the contact areas are secured in advance by the etch stop layers 15, 16 and 17, problems such as contact open defects can be prevented. The increase in resistance due to the decrease in contact area can be minimized.

Here, when etching to form the contact hole 19, it is carried out under an appropriate pressure and power, using a gas such as CF ₄ , CHF ₃ , Ar, or a mixture thereof.

Next, although not shown in the drawings, the polysilicon for plug contact is deposited on the entire surface of the resultant, and then the polysilicon layer and the interlayer insulating film 18 for the plug contact until the hard mask insulating layer 14 is sufficiently exposed by the CMP process. The contact plug may be formed by polishing the etch stop layer 17 or by filling the inside of the contact hole 19 using the selective epitaxial growth (SEG) method to omit a subsequent CMP process.

The present invention made as described above, by forming a thin layer of the anti-etching layer in the form of a spacer before forming the landing plug contact to ensure a large area of the contact area when forming the contact, and to prevent the loss of the interlayer insulating film due to the subsequent cleaning process At the same time it was found through the embodiment that the contact open defect can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention as described above, by securing a wide contact area when forming a contact, it is possible to prevent contact resistance reduction and contact open defects, and to prevent the loss of the interlayer insulating film due to the cleaning process to minimize the possibility of short circuit between devices, ultimately As a result, an excellent effect of improving the characteristics and yield of the device can be expected.

Claims (7)

Forming a plurality of neighboring conductive patterns on the substrate; Forming a first etch stop layer covering at least the conductive pattern sidewalls; Sequentially forming a second etch stop layer and an interlayer insulating layer along a surface of the substrate including the conductive pattern on which the etch stop layer is formed; And Selectively etching the interlayer insulating layer and the second etch stop layer to form a contact hole exposing the surface of the substrate between the conductive patterns; Semiconductor device manufacturing method comprising a. The method of claim 1, The first and second etch stop layer comprises a nitride film or an aluminum oxide film. The method of claim 1, The first and second etch stop layer is a semiconductor device manufacturing method, characterized in that formed in a thickness of 50 kPa to 500 kPa. The method according to claim 1 or 2, The method of claim 1, wherein the first etch stop layer is formed in multiple layers. The method of claim 1, And forming the interlayer insulating film so as to have a thickness of 2000 kPa to 15000 kPa. The method according to claim 1 or 5, After the interlayer insulating film is formed, Planarizing the interlayer insulating film to have a thickness of 500 mV to 5000 mV from an upper portion of the conductive pattern; And Forming a predetermined photoresist pattern on the interlayer insulating layer to define the contact hole; A semiconductor device manufacturing method further comprising. The method of claim 1, The conductive pattern includes a hard mask insulating film / gate electrode / gate insulating film structure.