KR20030042161A - Repair fuse circuit - Google Patents

Abstract

PURPOSE: A repair fuse circuit is provided to reduce a cut fuse number by comparing a decoded fuse cutting address with address signals and then performing a repair operation. CONSTITUTION: The first unit(F301) outputs a fuse enable signal according to cutting information based on normal and redundancy operations. The second unit(I303,302) outputs the first and second control signals according to the fuse enable signal and state data of a repair fuse. The repair fuse corresponds to a pair of the address signal and an inverted address signal. The first switch unit(N301,N302) adjusts a potential of an output node according to the address bar signal and the first control signal. The second switch unit(N303,N304) adjusts a potential of an output node according to the address signal and the second control signal.

Description

Repair fuse circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair fuse circuit. In particular, one repair fuse is configured for a pair of an address signal and an address bar signal, and a fuse enable signal according to a cutting state of an address fuse and a control signal according to a state of the repair fuse. And a repair fuse circuit for controlling an output of the repair fuse circuit according to the address signal, the address bar signal, and the control signal and the inverted signal thereof.

In general, in order to improve a yield of a semiconductor memory device, a redundancy cell is added to a normal cell to replace a redundancy cell when a bad memory cell occurs.

In high-density large-capacity memory devices using micromachining technology of more than 256M, undesired current paths are formed in the standby state of the memory device due to the bridge phenomenon caused by the lack of planar margin due to the narrowed line width finely processed during the manufacturing process. Defects occur more frequently. To improve this, a redundant memory cell is added to the normal cell, and a repair fuse for selecting the redundant memory cell is used.

1 is a schematic diagram of a memory device having a repair fuse circuit, and its operation will be described below.

The address signal address <0: n> input through the address buffer 11 is transmitted to the repair fuse circuit block 12. In each repair fuse circuit <0: n> of the repair fuse circuit block 12, the cutting information of the fuse, the address signal (address <0: n>) input through the address buffer 11, and the first control signal ( According to control 1), a select signal select <0: n> for selecting a normal operation or a repair operation is generated. The select signal select <0: n> generated in each repair fuse circuit <0: n> of the repair fuse circuit block 12 is transmitted to the normal cell and the redundancy cell select block 13. The normal cell and the redundancy cell selection block 13 use the second control signal control2, information obtained by NAND each selection signal select <0: n>, and an address signal address <0: n>. Outputs a normal enable signal or a redundancy enable signal. When the redundancy enable signal is output, the redundancy cells <0: n> 14 connected to the repair fuse circuit having the fuse cutting information of the corresponding address are selected. In this case, the normal disable signal (normal disable) is selected. The path to the normal cell 15 is blocked to prevent the redundancy cells <0: n> 14 and the normal cells 15 from being selected at the same time. On the contrary, when the normal enable signal is output, the normal cell 15 is selected according to the normal path. In this case, the redundancy disable signal (redundancy disable) blocks the redundancy path so that the redundancy cell <0: n> (14) is selected. ) Is selected.

2 is a repair fuse circuit diagram constituting a repair fuse block of a conventional dynamic logic method.

As illustrated, a first PMOS transistor P101 driven according to the first control signal control1 is connected between the power supply terminal Vcc and the common node common. The fuses F101 to F1n1 and the NMOS transistors N101 to N1n1 connected in series between the common node common and the ground terminal Vss include the address signal add <0: n> and its inverted signal addb <0: n>) constitutes a number of tributaries. For example, the first fuse F101 and the first NMOS transistor N101 driven according to the first address bar signal add0b are connected in series to form a branch, and the second fuse F102 and the first fuse are connected in series. The second NMOS transistor N102 driven in accordance with the address signal add0 is connected in series to form one branch. Therefore, twice as many fuses as the address signals are required. Further, a second PMOS transistor P102 driven according to the potential of the select signal output terminal is connected between the power supply terminal Vcc and the common node common. On the other hand, the select signal select is output at a potential in which the potential of the common node common is inverted through the first inverter I101.

A normal operation and a repair operation of a memory device having a conventional dynamic logic type repair fuse circuit configured as described above will be described with reference to FIGS. 3A and 3B as follows.

Referring to FIG. 3 (a), the normal operation is described. The first PMOS transistor P101 is turned on by the first control signal control1 applied in a low state so that the power supply voltage Vcc turns to the common node. Supplied. Thus, the common node initially remains high. The potential of the common node common that maintains the high state is inverted to a low state through the first inverter I101 and output as a select signal. On the other hand, since the select signal is kept low, the second PMOS transistor P102 is turned on, and the power supply voltage Vcc is supplied to the common node so that the common node is maintained high. do. When the first control signal control1 transitions to a high state, the fuse is not cut according to the fuse cutting information, and the address signal add <0: n> is applied, a common node and a ground in the repair fuse circuit are grounded. The potential of the common node (pass) is passed to the ground terminal (Vss) through one or more of the branches between the terminals (Vss). Therefore, the potential of the common node common is shifted to the low state, and accordingly, the select signal select is output to the high state. The select signal output in the high state is transmitted to the normal cell and the redundancy cell select block, and outputs the normal enable signal by the second control signal control2 that is waiting until the select signal has valid information. Will be performed. However, when using the conventional repair fuse circuit as shown, a predetermined time delay (3td) until the potential of the common node (common) transitions after the first control signal (control1) transitions, the common node ( After the potential of the common transitions, there is a predetermined time delay 2td until the selection signal transitions. In addition, a predetermined time delay 2td is also obtained until the second control signal control2 transitions after the select signal transitions. Here, td representing the time delay is irrelevant to the actual delay time and is expressed in multiples for understanding.

Referring to FIG. 3B, the repair operation is performed. The first PMOS transistor P101 is turned on by the first control signal control1 applied to the low state, and the common node common is initialized to the high state. After the fuse cutting information is input, the first control signal control1 transitions to a high state, and an address signal according to the fuse cutting information is input to cut the fuse of the corresponding address. For example, when the repair operation is performed when the first address signal add <0> is applied in a high state, the second fuse F102 of the branch corresponding to the first address add <0> is cut off. The fuse of the branch corresponding to the remaining address bar signals addb <1: n>, which is applied in a high state except for the first address bar signal add0b, is cut. Therefore, even if the NMOS transistors driven according to the first address signal add <0> and the second to nth address bar signals addb <1: n> applied to the high state are turned on, the fuse of the branch is cut. In this state, the common node is kept high. The potential of the common node common that maintains the high state is inverted through the first inverter I101 to output a low select signal. The select signal output in the low state is transmitted to the normal cell and the redundancy cell select block to enable the redundancy enable signal (redundancy enable) by the second control signal control2 that is waiting until the select signal has valid information. The output will perform a repair operation. However, after the first control signal control1 transitions to the high state, there is a predetermined time delay 7td until the second control signal control2 transitions to the high state. Here, td representing the time delay is irrelevant to the actual delay time and is expressed in multiples for understanding.

FIG. 4 is a repair fuse circuit diagram of a dynamic method having a conventional repair test mode. The configuration of the repair fuse circuit is the same as described with reference to FIG. 2, but a signal in which a potential of a common node is inverted by an inverter and a fuse enable bar signal. Is logically combined by the NOR gate so that the selection signal is output, and that a configuration of the repair test circuit for outputting the fuse enable bar signal is required.

As shown, the first NOR gate 201 logically combines the output signal of the first inverter I201 and the fuse enable bar signal fuse enb that inverts the potential of the common node common to the select signal. Outputs

A repair test circuit configuration for outputting a fuse enable bar signal (fuse enb) will be described below.

When the enable fuse F200 is connected between the power supply terminal Vcc and the first node Q201 and a power supply voltage is applied between the first node Q201 and the ground terminal Vss, power-up is outputted as a predetermined pulse. The NMOS transistor N200 driven according to the bar signal pwrupb is connected. The potential of the first node Q201 is latched by the latch means 202 composed of the second and third inverters I202 and I203 and then input to one input terminal of the second NOR gate 203. The second NOR gate 203 logically combines the output signal of the latch means 202 and the repair test mode signal (repair test) to output the fuse enable bar signal fuse enb.

5 (a) and 5 (b) show timing diagrams of a normal operation and a repair operation of the memory device including the dynamic fuse repair circuit having the conventional repair test mode configured as described above. . Unlike the circuit shown in FIG. 2, the circuit shown in FIG. 4 logically combines a fuse enable bar signal and an inverted signal of a common node to output a select signal. Accordingly, as shown in FIG. 5A, the select signal is shifted to the low state during the normal operation, and as shown in FIG. 5B, the select signal is the high state during the repair operation. As it transitions.

That is, when the repair test mode signal is applied to the high state after checking whether the repair operation is abnormal by only cutting the address fuse before enabling the fuse, the repair fuse can be tested regardless of the state of the enable fuse. After cutting the address fuse, the enable fuse enters the test mode without cutting and if the high signal is applied to the repair test circuit, the repair fuse operates as if the repair fuse is blown. Therefore, since it is possible to check whether there is an error and cut the enable fuse, it is possible to prevent a defect due to a mistake in cutting the fuse.

However, the conventional repair fuse circuit described with reference to FIGS. 2 and 4 may be implemented in the form of dynamic logic based on the fuse information to be cut, and thus, in the operation of the repair fuse for distinguishing a normal cell from a redundant cell. There is a delay. In addition, a large number of cutting fuses are required because the cutting fuses are used by the undecoded fuse cutting information.

It is an object of the present invention to provide a repair fuse circuit that can reduce the number of cutting fuses by performing repair by comparing the decoded fuse cutting address with an address signal.

Another object of the present invention is to provide a repair fuse circuit that can reduce the delay time caused by the operation of the repair fuse.

In the present invention, the static logic to take the output of the cutting fuse implemented by the conventional dynamic logic and to obtain the fuse cutting information in advance when the initial power is applied to the repair fuse circuit block for selecting a normal cell or redundancy cell and compare with the address information. Implement in the form of. To do this, an enable fuse is added at the output of the repair fuse circuit, and a mode for repair test is implemented.

1 is a schematic block diagram of a memory device having a repair fuse circuit.

2 is a repair fuse circuit diagram of a conventional dynamic logic method.

3 (a) and 3 (b) are timing diagrams for explaining the operation of a memory device having a conventional dynamic fuse circuit.

4 is a repair fuse circuit diagram of a dynamic method having a conventional repair test mode.

5A and 5B are timing diagrams for describing an operation of a memory device including a dynamic fuse fuse circuit having a conventional repair test mode.

6 is a repair logic circuit of a static logic method having a control unit according to the present invention.

7A and 7B are timing diagrams for describing an operation of a memory device including a static fuse repair fuse circuit having a control unit according to the present invention.

Figure 8 is a static fuse repair circuit diagram with a repair test mode according to the present invention.

9A and 9B are timing diagrams for describing an operation of a memory device including a static fuse repair circuit having a repair test mode according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 Address buffer 12 Repair fuse circuit block

13: Normal cell and redundancy cell selection block

14: redundancy cell 15: normal cell

The repair fuse circuit according to the present invention comprises a plurality of first means for outputting a fuse enable signal according to cutting information according to normal operation and redundancy operation, and a plurality of address signals, the address signal and its inverted signal. Second means for outputting first and second control signals in accordance with the state of the repair fuse configured as one for the pair of and the fuse enable signal, and the first bar of the address bar signal and the second means. First switching means for adjusting the potential of the output node in accordance with a control signal, and second switching means for adjusting the potential of the output node in accordance with the second control signal of the address signal and the second means. It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

6 is a repair logic circuit of a static logic method having a control unit according to the present invention. The configuration thereof is as follows.

The first PMOS transistor P301 driven according to the first control signal control1 is connected between the power supply terminal Vcc and the common node common. A second PMOS transistor P302 driven according to the output signal of the first inverter I301 for inverting the potential of the common node common is connected between the power supply terminal Vcc and the common node common. The output signal of the first inverter I301 is inverted by the second inverter I302 and output as a select signal.

The repair fuse circuit according to the present invention is configured such that one fuse is connected according to a pair of address signals add <0: n> and address bar signals addb <0: n>. The configuration of the first fuse means 31 among the fuse means 31 to 3n constituted by one block for convenience in accordance with one address signal add <0: n> and its inverted signal addb <0: n>. For example, as follows.

A first NMOS transistor N301 and a first fuse output bar signal fout0b driven according to the first address bar signal add0b at a branch between the common node common and the ground terminal Vss. Two NMOS transistors N302 are connected in series. A fourth NMOS driven according to the third NMOS transistor N303 and the first fuse output signal fout0 driven according to the first address signal add0 to another branch between the common node common and the ground terminal Vss. The transistor N304 is connected in series.

A configuration of a circuit for outputting a first fuse output signal fout0 and an inverted signal thereof is as follows.

The first fuse F301 is connected between the power supply terminal Vcc and the first node Q301. A fifth NMOS transistor N305 driven according to the power-up bar signal pwrupb is connected between the first node Q301 and the ground terminal Vss. The potential of the first node Q301 is, for example, latched by a latch means 301 consisting of two inverters, and then inverted by the third inverter I303 and output as the first fuse output bar signal fout0b. The signal is input to one input terminal of the first NAND gate 302. The first NAND gate 302 logically combines the fuse enable signal fuse en and the first fuse output bar signal fout0b to output the first fuse output signal fout0.

A circuit configuration for outputting a fuse enable signal (fuse en) is indicated by a reference numeral 30 like the selection signal output terminal for convenience, and the configuration thereof is as follows.

The enable fuse F300 is connected between the power supply terminal Vcc and the node Q300. An NMOS transistor N300 driven according to the power-up bar signal pwrupb is connected between the node Q300 and the ground terminal Vss. The potential of the node Q300 is for example latched by a latch means 300 consisting of two inverters and then output as a fuse enable signal fuse en.

A normal operation and a repair operation of a memory device including a static fuse type repair fuse circuit having a control unit according to the present invention configured as described above will be described with reference to FIGS. 7A and 7B. As follows.

Referring to FIG. 7 (a), a normal operation method is described. Each node includes a power-up bar signal pwrupb that maintains a low state after initializing an initial voltage of a node to which a voltage is applied to a memory device. NMOS transistors N300, N305, ..., N3n4 connected between Q300, Q301, Q3n0 and ground terminal Vss are turned on so that each node Q300, Q301, Q3n0 maintains a low potential After that, the power-up bar signal pwrupb transitions to a low state, and the NMOS transistors N300, N305,..., N3n4 are turned off. Since the enable fuse F300 is not cut for normal operation, the power supply voltage Vcc is supplied to the node Q300 through the enable fuse F300, so that the node Q300 maintains a high state. The potential of the node Q300 maintaining the high state is latched through the latch means 300 composed of two inverters, and then outputs a fuse enable signal of the low state.

When the first control signal control1 is applied in the low state, the first PMOS transistor P301 is turned on to supply the power supply voltage Vcc, thereby maintaining the high state. Since the fuse is not cut because of the normal operation, the power supply voltage is supplied to the first to nth nodes Q301,..., Q3n0 through the first to nth fuses F301,..., And F3n0 to maintain a high state. The potentials of the first to nth nodes Q301,..., And Q3n0 maintaining the high state are inverted to a low state through the first to nth latch means 301,..., 3n0, and the third to nth inverters ( Inverted through I303, ..., I3n0 to output the first to nth fuse output bar signals fout <0: n> b in a high state. The first to nth fuse output bar signals fout <0: n> b in the high state and the fuse enable signal fuse en in the low state are first to nth NAND gates 302, 304,..., 3n1. Input and logical combination to output the first to nth fuse output signals fout <0: n> in the high state. On the other hand, for example, when the first address add0 is applied in a high state and the remaining addresses add <1: n> are applied in a low state, the third and fourth NMOS transistors N303 and N304 are turned on. Since the current path is generated, the common node remains low. The potential of the common node common that maintains the low state is output as a select signal of the low state through the first and second inverters I301 and I302. The select signal output in the low state is transmitted to the normal cell and the redundancy cell select block, and the normal enable signal (normal enable) is applied by the second control signal control2 that is waiting until the select signal has valid information. It outputs to perform normal operation.

Referring to FIG. 7 (b), a repair operation method is described. Each node includes a power-up bar signal pwrupb that maintains a low state after initializing an initial voltage of a node to which a voltage is applied to a memory device. The NMOS transistors N300, N305, ..., N3n4 connected between Q300, Q301 through Q3n0 and the ground terminal Vss are turned on so that each node Q300, Q301 through Q3n0 maintains a low potential. Then, the power-up bar signal pwrupb transitions to a low state, and the NMOS transistors N300, N305,..., N3n4 are turned off. Since the enable fuse F300 is cut for the repair operation, the node Q300 is kept low because the power supply voltage Vcc is not supplied through the enable fuse F300. The potential of the node Q300 maintaining the low state is, for example, latched through the latch means 300 composed of two inverters, and then outputs a high fuse enable signal.

When the first control signal control1 is applied in a low state, since the first PMOS transistor P301 is turned on to supply the power voltage Vcc, the common node common maintains a high state. When the fuse cutting information is input and, for example, all the fuses F302 to F3n0 except for the first fuse F301 are cut, the first address signal add0 is applied in a high state, and the second to nth address signals ( addb <1: n> is applied in a low state. Accordingly, the first address bar signal add0b is applied in a low state, and the second to nth address bar signals add <1: n> b are applied in a high state. Looking at the first fuse means 31 in which the fuse is not cut, the power supply voltage is supplied to the first node Q301 through the first fuse F301 to maintain the high state. The potential of the first node Q301 that maintains the high state is inverted to the low state through the first latch means 301, and is inverted to the high state through the third to inverter I303 to output the first fuse in the high state. The bar signal fout0b is output. A first fuse output bar signal fout0b in a high state and a fuse enable signal fuse en in a high state are inputted by a first NAND gate 302 to logically combine a first fuse output signal fout0 in a low state. Output Accordingly, the first NMOS transistor N301 is turned on by the first address bar signal add0b in the low state, and the second NMOS transistor N302 is turned on by the first fuse output bar signal fout0b in the high state. . The third NMOS transistor N303 is turned on by the first address signal add0 in the high state, and the fourth NMOS transistor N304 is turned off by the first fuse output signal fout0 in the low state. On the other hand, since the fuses F302 to F3n0 of the second to nth fuse means 32 to 3n are cut, the fuse output bar signal foutb <1: n> in the low state and the fuse output signal in the high state (fout <1: n>) is output. Therefore, since no current path is formed through the ground terminal Vss, the common node maintains a high state and outputs a high select signal. The selection signal output in the high state is transmitted to the normal cell and the redundancy cell selection block, and the repair operation is performed by outputting the normal enable signal by the second control signal control2 that was waiting until the selection signal has valid information. Will be performed.

As described above, in the repair fuse circuit according to the present invention, the fuse which is connected to each of the fuses according to the conventional address signal add <0: n> and the address bar signal addb <0: n> is replaced with the address signal and the address. Place one for each pair of bar signals.

Since the fuse output signal fout and the fuse output bar signal foutb are configured in the form of static logic by the power-up bar signal pwrupb at the initial power-up, different levels are determined according to the cutting state of the fuse. Will have Accordingly, in the conventional method, the state of the common node may be determined faster than the method of confirming the fuse cutting information of the dynamic logic type by the control signal and determining the state of the common node. In addition, in the conventional repair fuse circuit, if a time of 3td is required until the common node has valid information after the first control signal transitions, the repair fuse circuit according to the present invention applies the initial power to the fuse cut information. Because it is decided when, it is reduced to 2td time.

On the other hand, when repairing all addresses having a high state, the initial value of the repair fuse is set to a high state, thereby preventing the common node from becoming the same as normal operation. That is, if a fuse that generates a fuse enable signal is not cut, the repair fuse does not operate regardless of whether other fuses are cut. This is a very useful method, and if you accidentally cut the fuse by mistake, you couldn't modify it in the previous way, making the memory device unusable. However, the use of a fuse enable signal prevents the use of a repair fuse that has been incorrectly modified by cutting the fuse.

FIG. 8 is a static fuse repair circuit diagram having a repair test mode according to the present invention. The configuration of the repair fuse circuit is the same as described in FIG. 6, but a circuit for outputting a fuse enable signal is repaired. Driven by a test signal (repair test), the configuration is described as follows.

A fuse F400 is connected between the power supply terminal Vcc and the node Q400. An NMOS transistor N400 driven according to the power-up bar signal pwrupb is connected between the node Q400 and the ground terminal Vss. The potential of the node Q400 is, for example, latched in a latch means 400 consisting of two inverters and then input to the NOR gate 410 with a repair test signal. The NOR gate 410 outputs a signal obtained by logically combining these signals, and the signal is inverted by the inverter I4n1 to output a fuse enable signal fuse en.

9 (a) and 9 (b) show timing diagrams of a normal operation and a repair operation of a memory device including a static fuse repair circuit having a repair test mode according to the present invention. As shown, the same operation as the circuit of FIG.

As described above, according to the present invention, the number of the cutting fuses can be reduced by using the address fuse coding method, and the operation speed of the common node can be faster than the conventional dynamic method by using the static logic. In addition, by using the enable fuse to generate a fuse enable signal it is possible to rescue even if the fuse is incorrectly cut. In other words, after entering the repair test mode and checking whether there is an error in the repair operation, the repaired fuse may be disabled.

Claims (9)

In the repair fuse circuit, One repair fuse is configured for a pair of address signals and address bar signals, a fuse enable signal according to a cutting state of an address fuse and a control signal according to a state of the repair fuse are output, and the address signal and address bar signal And an output of the repair fuse circuit in accordance with the control signal and its inverted signal. First means for outputting a fuse enable signal in accordance with the cutting information according to the normal operation and the redundancy operation; A plurality of address signals, one for each pair of the address signal and its inverted signal, and data for the first and second control signals according to the fuse enable signal and data according to the state of the repair fuse. Second means, First switching means for adjusting a potential of an output node according to the address bar signal and the first control signal of the second means; And second switching means for adjusting a potential of an output node in accordance with said address signal and said second control signal of said second means. 3. The apparatus of claim 2, wherein the first means comprises: an address fuse connected between a power supply terminal and a first node and operated according to cutting information according to normal operation and redundancy operation; An NMOS transistor connected between the first node and a ground terminal and driven according to a power-up signal; And a latch means for latching the potential of the first node to output a fuse enable signal. 3. The apparatus of claim 2, wherein the first means comprises: an address fuse connected between a power supply terminal and a first node and operated according to cutting information according to normal operation and redundancy operation; An NMOS transistor connected between the first node and a ground terminal and driven according to a power-up signal; Latch means for latching a potential of the first node; And a logic means for inputting and logically combining the output signal of the latch means and the repair test mode signal to output a fuse enable signal. 5. The repair fuse circuit as claimed in claim 4, wherein the logic means comprises an NOR gate and an inverting means for inverting an output signal of the NOR gate. 3. The apparatus of claim 2, wherein the second means comprises: a repair fuse connected between the power supply terminal and the first node and driven according to the cutting information; An NMOS transistor connected between the first node and a ground terminal and driven according to a power-up signal; Latch means for latching a potential of the first node; Inverting means for inverting the output signal of the latching means and outputting the first control signal; And logic means for logically combining the first control signal and the fuse enable signal to output the second control signal. 7. The repair fuse circuit of claim 6, wherein the logic means is a NAND gate. 3. The apparatus of claim 2, wherein the first switching means are first and second NMOS transistors connected in series between the output node and the ground terminal and driven according to the address bar signal and the first control signal, respectively. Repair fuse circuit. 3. The repair device as claimed in claim 2, wherein the second switching means are first and second NMOS transistors connected in series between the output node and the ground terminal and driven according to the address signal and the second control signal, respectively. Fuse circuit.