KR20030029207A - Method of formimg semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device is provided to prevent deterioration of a gate insulation layer and use each exposure process on gate electrodes. CONSTITUTION: A hard mask layer is formed on two transistor regions including gate layers with different structure. The first hard mask(81) pattern for the first gate formation is formed by patterning one of the transistor regions. A layer of stacked gate layer is etched. Patterning the other of the transistor region, the second hard mask pattern(83) is formed. The etching for the first and second type gate formation is done using the first and second mask pattern.

Description

Method of forming a semiconductor device {METHOD OF FORMIMG SEMICONDUCTOR DEVICES}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of patterning a gate electrode of a semiconductor device having a gate electrode having a different stacked structure together.

The gate electrode of the semiconductor device using the MOS transistor may be formed of various materials as needed, and may be formed of two or more conductive layers, but the gate electrode structure in one semiconductor device is usually the same. On the other hand, in an EPROM, an EEPROM, a flash memory, etc. using a floating gate, a high voltage transistor such as a cell memory transistor to which a high voltage is applied for cell memory operation and a low voltage transistor constituting a logic circuit of a peripheral part coexist on the same chip. . The gate electrode of the cell transistor and the gate electrode of the low voltage transistor constituting the peripheral circuit have a difference in their lamination structure due to the difference in operating principle and the need for breakdown voltage.

1 is a cross-sectional view comparing a double gate stacked structure of a cell memory region and a simple gate stacked structure of a logic circuit region in an example of a nonvolatile memory device employing a floating gate.

Referring to FIG. 1, the double gate of the cell memory region is spaced apart from the substrate 10 by a thick gate insulating film 20 of about 250 angstroms. The first polysilicon layer 40 and the ONO dielectric film 50 for the floating gate are spaced apart from each other. And a control gate film composed of the second polysilicon layer 70 and the tungsten silicide layer 80. The simple gate of the logic circuit region is formed of a gate film spaced apart from the substrate 10 by a thin gate insulating film 30 of about 70 angstroms, and the gate film is formed of the second polysilicon layer 60 like the control gate film. And tungsten silicide layer 70. The gate films of the cell memory region and the logic circuit region are covered with a hard mask layer 80 to form a hard mask pattern thereon.

This structure uses a patterning process including one exposure process to form gate insulating films of different thicknesses in the active region, forming and patterning polysilicon layers and dielectric layers to form floating gates, and metals such as polysilicon layers and tungsten silicide layers over the dielectric layers. This may be achieved through a process step of stacking a control gate film of silicide.

These memory devices having different gate electrode structures on one chip also have a smaller device size in the periphery or core region as well as the cell region due to the necessity of high integration, and the conditions of the process for processing and forming fine elements become increasingly strict. Under stringent conditions, differences in electrode structures within the chip make processing difficult, including gate electrode formation, in these memory devices compared to memory devices with single gate structures. For example, in these memory devices, it is increasingly difficult to form two types of gate electrodes having different stacked structures at the same time by performing a single exposure process while performing each function without any problem.

Therefore, the operation of patterning the entire gate electrode of the cell transistor having the stacked structure of the floating gate, the dielectric film, and the control gate and the patterning of the gate active of the peripheral logic circuit region transistor having the simple stacked structure are performed through a separate exposure process. You lose. In order to form a highly integrated semiconductor device, instead of using a thick organic photoresist as an etch mask, a hard mask layer is formed of a silicon oxide film or the like, and then a pattern is formed on the hard mask layer, and the hard mask pattern is etched. The method used is used.

However, when the gate electrode of the dual structure is patterned first and the simple gate electrode is subsequently patterned while using the hard mask pattern, the thick gate insulating layer exposed in the gate electrode patterning process of the dual structure patterns the simple gate electrode. The process is etched and degraded. For example, in the process of etching the tungsten silicide layer forming the upper portion of the simple gate electrode, not only the tungsten silicide but also the thick gate insulating layer may be damaged by the physical impact force of the accelerated etchant ion.

In addition, the gate insulating film of the deteriorated high voltage transistor region cannot properly function as an ion implantation buffer in the ion implantation step performed after the gate pattern is formed, and causes a leakage current when a high voltage is applied.

As described above, the present invention is to solve the problem of deterioration of the gate insulating film resulting from a separate gate electrode forming process in a semiconductor device having a different gate electrode structure, while forming a gate electrode for each region using a separate exposure process. An object of the present invention is to provide a method for forming a semiconductor device which does not deteriorate the gate insulating film in any one region.

1 is a cross-sectional view comparing a double gate stacked structure of a cell memory region and a simple gate stacked structure of a logic circuit region in an example of a nonvolatile memory device employing a floating gate.

2 through 6 are cross-sectional views illustrating important process steps according to the method of the present invention divided into a cell memory transistor region in which a first type gate is formed and a peripheral circuit low voltage transistor region in which a second type gate is formed.

In order to achieve the above object, a method of forming a semiconductor device according to the present invention may include forming a hard mask layer on an entire surface of two kinds of transistor regions in which gate layers having different layer structures are stacked, and patterning one of two kinds of transistor regions. Forming a first hard mask pattern for forming a first type gate; etching a portion of the layer forming the stacked gate film by using the first hard mask pattern; and patterning a second hard mask by patterning the other transistor region And forming a pattern, and completing etching of the first type and the second type gates using the first and second hard mask patterns.

In the present invention, the process of etching a portion of the second type gate may be continuously performed in the step of forming the second hard mask pattern before completing the etching for forming the gate.

In the present invention, the etching of some layers of the first type gate or the etching of some layers of the first type gate and the etching of some layers of the second type gate through etching process to complete the etching for forming the gate It is desirable to leave only residual layers that give the same etching burden for specific etching conditions. For example, it is desirable that only residual layers of the same material and the same thickness remain common in both kinds of transistor regions. It is also possible to leave residual layers of different layer configurations having the same etching time for the same etching conditions in each of the two kinds of transistor regions.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 through 6 are cross-sectional views illustrating important process steps according to the method of the present invention divided into a cell memory transistor region in which a first type gate is formed and a peripheral circuit low voltage transistor region in which a second type gate is formed.

Referring to FIG. 2, a hard mask layer 80 and a photoresist layer 90 are formed on a gate layer having another layer structure as shown in FIG. 1. Referring to the process of forming a layer structure as shown in FIG. 1, a high voltage gate insulating film 20 having a thickness of, for example, 250 angstroms is formed on the entire active region of the substrate 10 on which the device isolation layer is not shown. The gate insulating film 20 is removed in the low voltage region of the peripheral portion through the patterning of the high voltage gate insulating film 20. Substrate thermal oxidation of the exposed low voltage region is performed to form a low voltage gate insulating film 30 of, for example, about 70 angstroms. The first polysilicon layer 40 and the dielectric layer 50 to form the floating gate are formed, and the first polysilicon layer 40 and the dielectric layer 50 are removed through patterning in regions other than high voltage regions such as cell regions. The control gate layer of the second polysilicon layer 60 and the tungsten silicide layer 70 is stacked on the entire surface of the substrate 10 over the dielectric film 50. The control gate layer is patterned in the cell memory region to form a control gate, and forms a simple gate in the low voltage peripheral circuit region. As is well known to those of ordinary skill in the art, such a structure can also be formed through some modified process.

The hard mask layer 80 is usually formed of a CVD silicon oxide film, and a silicon oxynitride film serving as an antireflection film may be further stacked on the silicon oxide film. A portion of the upper portion of the hard mask layer 80 may be removed through etching while acting as an etching mask. The dielectric film 50 is usually formed of an oxide nitride oxide (ONO) film.

Referring to FIG. 3, a first hard mask pattern 81 is formed in a cell memory region through patterning using the photoresist layer 90 of FIG. 2. The first hard mask pattern 81 is formed to correspond to the first type gate. At this time, the hard mask layer 80 in the peripheral low voltage region is preserved. The photoresist pattern used to form the first hard mask pattern 81 is removed. Ashing or wet stripping may be used to remove the photoresist pattern.

Referring to FIG. 4, a part of a gate layer, that is, a tungsten silicide layer 70 and a second polysilicon layer 60 are stacked using a first hard mask pattern 81 as an etching mask and a lower portion thereof. The dielectric film 50 is etched. Therefore, the first polysilicon layer 40 to form the floating gate is exposed in the portions where these films are etched away.

Referring to FIG. 5, the photoresist is laminated on the entire surface of the substrate 10 in the state of FIG. 4. The second hard mask pattern 83 is formed by etching the hard mask layer 80 in the peripheral circuit low voltage region through a patterning operation using the photoresist layer 100. In addition to forming the second hard mask pattern 83, the tungsten silicide layer 70, which is the upper layer among the control gate layers including the tungsten silicide layer 70 and the second polysilicon layer 60, is continuously etched to form a lower second poly Silicon layer 60 is exposed. In this case, the cell memory transistor region is protected by the photoresist layer 100.

Referring to FIG. 6, the photoresist layer 100 remaining on the substrate in the state of FIG. 5 is removed and the first and second hard mask patterns 81 and 83 are etched in both the peripheral circuit low voltage transistor region and the cell memory transistor region. The second polysilicon layer 60 and the first polysilicon layer 40 remaining in these areas are etched using the mask. Accordingly, the low voltage gate insulating film 30 and the high voltage gate insulating film 20 are exposed in these regions, respectively, and the first type gate 111 of the cell memory region and the second type gate 113 of the peripheral logic circuit region are formed. And the etching process is completed.

In addition, the etching conditions including the etching gas for each material layer constituting the layer structure of the gate through the present invention is well known to those skilled in the art, and a method of anisotropic dry etching, which is mainly used, may also be made in a general range. As a method of removing only a part of the entire gate layer structure through etching, a method of controlling time using an etching characteristic and a thickness of a material, and an EPD (End Point Detection) that detects a component change of an etching chamber exhaust gas according to a layer change is detected. ) Method and the like can be used.

In the present embodiment, when the first polysilicon layer and the second polysilicon layer are formed to have similar thicknesses, the time required for etching these layers under the same etching conditions is not significantly different. Since the silicon oxide film and the polysilicon layer constituting the gate insulating film can maintain a sufficient etching selectivity, the etching damage to the lower gate insulating film is very difficult in the step of etching the first and second polysilicon layers to complete the gate electrode patterning. Becomes smaller.

According to the present invention, due to the gate electrode layer structure of each region in the same semiconductor chip, it is possible to solve a problem in which one region is damaged by an etching process of another region, resulting in abnormal function and characteristics. In particular, it is possible to solve the problem of no additional exposure process.

Claims (5)

Forming a hard mask layer over the two kinds of transistor regions in which gate layers having different layer structures are stacked; Forming a first hard mask pattern for forming a first type gate through patterning in one of the two transistor regions; Etching some layers of the gate layer by using the first hard mask pattern; Forming a second hard mask pattern for forming a second type gate through patterning on one of the two transistor regions; And completing an etching to form the first type and the second type gates using the first and second hard mask patterns. The method of claim 1, Before the etching of the gate forming step, the step of forming the second hard mask pattern using the same photoresist pattern is performed to etch a part of the layer forming the layer structure of the second type gate in succession. A semiconductor device formation method. The method of claim 2, The etching of the partial layer of the gate layer using the first hard mask pattern and the etching of the partial layer forming the layer structure of the second type gate through the etching process to complete the etching for forming the gate may include A method of forming a semiconductor device, in which only a residual layer of the same material is left in common in the transistor region. The method of claim 1, The etching of the partial layer of the gate layer using the first hard mask pattern and the etching of the partial layer forming the layer structure of the second type gate through the etching process to complete the etching for forming the gate may include A method of forming a semiconductor device, comprising leaving residual layers of different layer configurations having the same etching time for the same etching conditions in each transistor region. The method of claim 1, The layer structure of the first type gate includes a control gate layer including a first polysilicon layer for floating gate, an ONO dielectric layer, a second polysilicon layer, and tungsten silicide on the gate insulating layer, and partially using the first hard mask pattern. In etching the layer, only the first polysilicon layer is left, The layer structure of the second gate includes a second polysilicon layer and a tungsten silicide layer, and when the second hard mask pattern is formed, the tungsten silicide layer is continuously etched and only the second polysilicon layer remains. A semiconductor device formation method.